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This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed. [ABSTRACT FROM AUTHOR]

Control of overlay errors in lithography process in semiconductor manufacturing uses in-process measurements of overlay errors from markers distributed across a wafer to adapt controllable process parameters on the relevant lithography tools in order to minimize future errors. Intuitively speaking, the use of a larger number of measurement markers should lead to improvements in one’s ability to control the overlay errors. However, those gains come with simultaneous increases in the metrology times, which negatively impacts throughput. Therefore, one should carefully and strategically select markers which most efficiently enable suppression of overlay errors. This paper proposes a novel optimization framework that couples a recently introduced approach for robust control of overlay errors in photolithography processes with a strategic selection of overlay measurement markers to enable improved control of overlay errors using a reduced number of measurements. Application of the newly proposed method to the data and models from an industrial-scale semiconductor lithography process shows that the newly proposed combination of the robust overlay control paradigm and optimized marker selection enables improved overlay control, even with a significantly reduced number of markers. Thus, the new methodology enables reduction of measurement times and subsequent overall cycle times, without deteriorating the outgoing product quality. [ABSTRACT FROM AUTHOR]

The thicker photoresists are usually used in the manufacture processes of micro electro mechanical systems (MEMS), bipolar CMOS DMOS (BCD), and insulated gate bipolar transistor (IGBT), due to the thicker film need to be etched, high-dose implant process or other extreme processes have been widely used. This paper deal with the double coating process using the single commercial photoresist, this is an effective and simple approach to achieve the thicker photoresist thickness for the lithography process. We focus on the prediction of the thickness of the double-layer photoresist, which has seldom been reported in past studies. Although the final photoresist cross-section looks like one layer, we divide it theoretically into two layers, refer to as the first layer photoresist and the second layer one. Combined this model, first, an original equation for predicting the final thickness is deduced from the model developed by Emslie et al. Second, we conduct the experiment with different photoresists, soft bake temperatures, and soft bake times, and compare the theoretical predicted thickness to the actual one obtained from the experiment, moreover, a modified equation with satisfied accuracy is proposed, we can prepare the required photoresist thickness quickly and accurately by using this equation, not only can development cost be saved, but also can development cycle be shortened. [ABSTRACT FROM AUTHOR]

This paper studies an unrelated parallel machine photolithography scheduling problem with dual resource constraints (DRC). This is an emerging problem in the semiconductor industry, where the masks can be transferred from one working station to another, increasing the flexibility of production through sharing the auxiliary resource. It gives rise to a complex DRC scheduling problem involving jobs, machines, and masks, restricted by sequence-dependent setup time and station-dependent mask transfer time. This study proposes two mixed-integer programming (MIP) models (Model 1 and Model 2) and an improved naked mole-rat algorithm that hybrids with a genetic algorithm (GA) and variable neighborhood search algorithm (VNS). Numerical experiments show that Model 2 performs better compared with Model 1, and the improved naked mole-rat algorithm brings a significant improvement over GA and VNS. [ABSTRACT FROM AUTHOR]

Thin film lithium niobate on insulator (LNOI), as an emerging photonic material, provides a promising platform to realize compact, high-speed, and high-efficient electro-optic (EO) modulators. However, due to the large coupling loss caused by the large mode field mismatch between standard single mode fibers and LNOI single mode waveguides, edge or grating couplers are indispensable to LNOI modulators. In this paper, we propose a novel edge coupler employing staircase structure. The proposed coupler is feasible with i-line lithography and avoids high precise alignment. Moreover, such coupler can be applied to wafer-scale manufacture with low cost. The simulation results show a low coupling loss less than 1.60 dB can be achieved at 1.55 μm wavelength for transverse electric (TE) polarized light signals. Specifically, benefited from the novel staircase design, the proposed edge coupler shows a unique property of polarization extinction ratio larger than 10 dB, which will further improve the modulation efficiency and extinction ratio of the EO modulators based on X-cut LNOI. [ABSTRACT FROM AUTHOR]

VLSI layout patterns provide critical resources in various design for manufacturability research, from early technology node development to back-end design and sign-off flows. However, a diverse layout pattern library is not always available due to long logic-to-chip design cycle, which slows down the technology node development procedure. To address this issue, in this paper, we explore the capability of generative machine learning models to synthesize layout patterns. A transforming convolutional auto-encoder (TCAE) family is developed to learn vector-based instantiation of squish pattern topologies. We show our TCAE models can capture simple design rules and enlarge the existing squish topology space under certain transformations. With adaptive configurations, the proposed G-TCAE framework allows both massive pattern generation and context-specific pattern generation. Geometry information of each squish topology is obtained from an associated linear system derived from design rule constraints. Experiments on $7nm$ EUV designs show that our framework can more effectively generate diverse pattern libraries with DRC-clean patterns compared to a state-of-the-art industrial layout pattern generator. [ABSTRACT FROM AUTHOR]

Fogging and proximity effects (FPEs) are two major factors that cause inaccurate exposure and layout pattern distortions in e-beam lithography. In this article, we propose an analytical placement algorithm that considers both FPEs. We formulate the global placement problem as a separable minimization problem with linear constraints, where different objectives can be tackled one by one in an alternating fashion. Then, we propose a novel proximal group alternating direction method of multipliers (ADMM) to solve the separable minimization problem with two subproblems, where the first subproblem (associated with wirelength and density) is solved by the steepest descent method without line search, and the second one (associated with the FPEs) is handled by an analytical scheme. We prove the property of global convergence of the proximal group ADMM method. Finally, the FPEs-aware legalization and detailed placement are employed to legalize and improve the placement result. The experimental results show that our algorithm is effective and efficient for the addressed problem. Our algorithm achieved 5.7% smaller fogging variation, 6.8% lower proximity variation, and 5.4% lower runtime with a minor wirelength overhead compared with the state-of-the-art work. [ABSTRACT FROM AUTHOR]

This work introduces a practical reinforcement learning (RL) techniques to address the complex scheduling challenges in producing Active Matrix Organic Light Emitting Diode displays. Specifically, we focus on autonomous optimization of the photolithography process, a critical bottleneck in the fabrication. This provides an outperforming scheduling method compared with the existing rule-based approach which requires diverse rules and engineer experience on adapting dynamic environments. Our purposing RL network was designed to make effective schedules aligning with layered structures of the planning and scheduling modules for mass production. In the training phase, historical production data is utilized to create a representative discrete event simulation environment. The RL agent, based on the Deep Q-Network, undergoes episodic training to learn optimal scheduling policies. To ensure safe and reliable scheduling decisions, we further introduce action filters and parallel competing schedulers. The performance of RL-based Scheduler (RLS) is compared to the Rule-Based Scheduler (RBS) over actual fabrication in a year-long period. Based on key performance indicators, we validate the RLS outperforms the RBS, with a remarkable improvement in step target matching, reduced setup times, and enhanced lot assignments. This work also paves a way for the gradual integration of AI-based algorithms into smart manufacturing practices. [ABSTRACT FROM AUTHOR]

Since the invention of transistors and integrated circuits, the development of semiconductor processes has advanced rapidly. Current microchips contain hundreds of millions of transistors. The remarkable development of semiconductors thus far has also led to difficulties in designing tightly packed lithography patterns without unwanted defects called hotspots in the manufacturing process. Therefore, research areas focusing on these problems have received much attention. In particular, predicting hotspots during the design stage is essential for high productivity in the semiconductor industry. In this study, we developed a deep learning-based SEM image generation model to predict hotspots from layout patterns at the design stage. Our model combines a segmentation network and an image-to-image translation network based on a conditional generative adversarial network in parallel. Our proposed model can predict and display potential hotspots in scanning electron microscopy images generated from given layouts. Additionally, the model leverages prior knowledge of the optical diameter to predict patterns that are prone to hotspots. Our model shows improved performance over baseline models when evaluated on real-world industrial data. [ABSTRACT FROM AUTHOR]

Nanopatterns formed by dense nanoscale (20–30nm diameter) block copolymer lithography and subsequent selective area MOVPE were utilized to realize room temperature operation of quantum dot (QD) active region laser diodes on InP substrates, by employing a carrier-injection layer adjacent to the QDs. Initial studies focused on InGaAs QDs grown on GaAs substrates, which exhibit relatively broad photoluminescence (PL) emission linewidths (FWHM~93meV at RT). Atomic force microscopy measurements reveal that a wide distribution of QD thickness variations correlates well to the observed broad PL linewidths, based on the simulated range of QD transitions. The fabricated edge-emitting devices on InP substrate exhibit lasing emission near $1.57\sim 1.67~\mu \text{m}$ at room temperature with a threshold current density as low as 1.6 kA/cm2 for 4mm-long devices. The observed dependency of device characteristics, such as threshold current density and lasing wavelength, on the cavity length and on the heat sink temperature suggests the dominant lasing transition energy corresponds to the QD excited state, except for the longest cavity length devices (L = 4mm) which operate on the QD ground state transition near room temperature. We believe these data represent the only reports of lasers in this wavelength region employing QDs formed by diblock co-polymer lithography and selective area MOVPE growth. These data also suggest that QD height variations need to be further reduced, through MOVPE growth optimization, to achieve higher optical gain from the QD ground state transition. [ABSTRACT FROM AUTHOR]

The electrical validation of a generalized space error model is reported. This was achieved by comparing inline e-beam “direct” space metrology measurements with an end-of-line, yield-based, space error metric. This electrical test (e-test) of the space error is derived from the conductance of metallized test structures with programmed interlayer offsets between line and block layers used for patterning. Local space variation was extracted from voltage contrast arrays, and from inline metrology statistics. A good match was observed between the predicted space error from the weighted sum of the local and non-local terms, and the measured e-test space error. A model is proposed for the experimental validation of the local term (stochastic) of the space error model. [ABSTRACT FROM AUTHOR]

Color defect detection was improved with the development of a Machine Learning (ML) method for after develop inspections in lithography. For coating defects, the method exhibited two times the sensitivity and three times the specificity in a trial comparison against the reference method. Using the ML method for disposition along with recipe optimization, predictive maintenance, and rework for coating defects, reduced yield loss from splatters in the long run by over 20x. Herein we describe learnings on the use of image enhancement for training and disposition, an Explainable AI application to support understanding, and a process flow to train augmentation based on performance. [ABSTRACT FROM AUTHOR]

A set of good test patterns is a key for accurate lithography modeling. We address three sub-problems in test pattern extraction: (1) Each pattern is associated with one or more gauges, where CD is measured and modeling is performed. We perform gauge clustering in feature space, while the goal is to minimize the number of chosen patterns. (2) Sample patterns do not usually guarantee enough coverage, so once coverage of chosen patterns is identified, some synthetic patterns are systematically generated to fill the empty region in feature space. (3) Pattern representation defines the feature space. We propose to use some Gaussian convolutions (or a few of their principal components) together with image parameter set (IPS) to reflect exposure for optical model and both PEB and development for resist model. Experiments with 1xnm DRAM design demonstrate that lithography modeling through our test pattern extraction and generation is performed with 35% smaller number of test patterns while CD error is reduced by 55%, with pattern extraction in feature space of IPS parameters as a reference. [ABSTRACT FROM AUTHOR]

A new methodology for realizing fabrication-tolerant planar directional couplers is proposed and experimentally demonstrated. Performance of power splitting and WDM couplers can be made highly tolerant to typical process errors when an appropriate center-to-center spacing is chosen due to changes in the mode area compensating waveguide edge to edge variation along a very specific design locus. Using this approach, 2–3% index contrast waveguide couplers were fabricated and tested, demonstrating the predicted improved fabrication tolerances. High index contrast silicon-on-insulator systems are also shown to exhibit the same mechanism. The high fabrication tolerance demonstrated is of particular importance for vertically stacked hybrid integration of different materials platforms, where achieving tight critical dimension control over significant physical topology is problematic. Additionally the method will be of utility in circumstances where tight tolerances are required on coupling ratios such as coupled resonator filter devices etc. [ABSTRACT FROM AUTHOR]

Silicon sensors date back to before 1960 with early Hall and piezoresistive devices. These used simple processing that was part of the early integrated circuit (IC) industry. As the IC industry developed, silicon sensors could benefit from the technological advances. As silicon sensors advanced, there came the need for new technologies specifically for microsystems. This led to a range of 3-D structures using micromachining and enabled the development of both sensors and actuators. The integration of sensors with electronics on a single chip also presented new challenges to ensure that both sensor and electronics would function correctly at the end of the processing. In recent years many new technologies and new materials were introduced to enhance the functionality of microsystems. Some sensors are still based on silicon, but others introduce new materials such as carbon nanotubes and graphene. Technologies that have been used in other applications for many years are now integral part of the microsystem technology portfolio. These include screen printing and inkjet printing. Moving more into the third dimension, 3-D printing presents many new opportunities to fabricate novel structures on a silicon substrate. This tutorial focuses on the additional technologies which have been developed to supplement standard IC processes to create MEMS structures. [ABSTRACT FROM AUTHOR]

Spin-transfer torque (STT) magnetic random access memory (MRAM) is gaining commercial traction in low-density embedded and standalone memories, but the available market opportunities would grow exponentially if STT-MRAM could approach dynamic random access memory (DRAM) bit density. Of course, achieving DRAM density will require, among other things, demonstrating the ability to pattern MRAM bits at an extremely tight pitch. Here, an experimental demonstration of fabrication and electrical testing of a STT-MRAM bit array are reported. By optimizing the hard mask and ion beam etching (IBE) processes, MRAM bit arrays with a full pitch down to 50 nm are fabricated, in which the bits are individually tested using a novel bottom-point-contact method. [ABSTRACT FROM AUTHOR]

This work presents an in-depth study of simulation and measurement results of laterally excited shear bulk acoustic resonators (XBAR) in Lithium Niobate, at 5 GHz with high electromechanical coupling factor ($k_{t}^{2}$) as high as 25%, and with impedances at resonance close to $2~\Omega $. Loaded Quality factors of up to 340 and 150 are obtained at resonance and anti-resonance, respectively. Experimental00 dispersion behaviors of main mode and spurious are presented. Several geometric parameters affecting resonator performance are studied in order to improve figure of merits (FoM) of the device for 5G filter applications. The modified fabrication process presented shows a high yield of over 90% of devices which can be scalable for mass production of high frequency, sub-6 GHz, wide band filters. [2021-0202] [ABSTRACT FROM AUTHOR]

Speedy and on-time detection of coronavirus disease 2019 (COVID-19) is of high importance to control the pandemic effectively and stop its disastrous consequences. A widely available, reliable, label-free, and rapid test that can recognize tiny amounts of specific biomarkers might be the solution. Nanobiosensors are one of the most attractive candidates for this purpose. Integration of graphene with biosensing devices shifts the performance of these systems to an incomparable level. Between the various arrangements using this wonder material, field-effect transistors (FETs) display a precise detection even in complex samples. The emergence of pioneering biosensors for detecting a wide range of diseases especially COVID-19 created the incentive to prepare a review of the recent graphene-FET biosensing platforms. However, the graphene fabrication and transfer to the surface of the device is an imperative factor for researchers to take into account. Therefore, we also reviewed the common methods of manufacturing graphene for biosensing applications and discuss their advantages and disadvantages. One of the most recent synthesizing techniques - laser-induced graphene (LIG) - is attracting attention owing to its extraordinary benefits which are thoroughly explained in this article. Finally, a conclusion highlighting the current challenges is presented. [ABSTRACT FROM AUTHOR]

Combining multiple patterning lithography (MPL) and optical proximity correction (OPC) pushes the limit of 193-nm wavelength lithography to go further. Considering that layout decomposition may generate plenty of solutions with diverse printabilities, relying on conventional mask optimization (MO) process to select the best candidate for manufacturing is computationally expensive. Therefore, an accurate and efficient printability estimation is crucial and can significantly accelerate the layout decomposition and MO (LDMO) flow. In this article, we propose a convolutional neural network (CNN)-based prediction and integrate it into our new high-performance LDMO framework. The optimization process can be considerably improved as the decomposition quality has been inferred in the early phase. To facilitate the network training and ensure better estimation accuracy, we develop sampling strategies for both layout and decomposition. Moreover, we enhance the layout sampling approach by adopting autoencoder to distance evaluation that promises superior sampling results. The experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms. [ABSTRACT FROM AUTHOR]

Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decomposition (MPLD) is critical to design closure. Due to the $\mathcal {N} \mathcal {P} $ -hardness of the general decomposition problem, various efficient algorithms have been proposed with high-quality solutions. However, with increasingly complicated design flow and peripheral processing steps, developing a high-quality layout decomposer becomes more and more difficult, slowing down further advancement in this field. This article presents $\mathsf {OpenMPL}$ (2020), an open-source layout decomposition framework, with well-separated peripheral processing and core solving steps. Besides, previous algorithms or techniques are inspected and several issues are discovered. We then propose corresponding new algorithms to resolve these issues. The experiments demonstrate the effectiveness of our proposed algorithms and the efficiency of $\mathsf {OpenMPL}$. [ABSTRACT FROM AUTHOR]

We report the fabrication of a novel multimodal biosensor combining plasmonic and electrochemical detection. The plasmonic sensors are based on monitoring the propagation of Bloch long-range surface plasmon polaritons (LRSPPs) along thin narrow Au stripes, integrating grating couplers as input/output means. The electrochemical sensors use the same Au stripes as working electrodes with nearby Pt stripes integrated on-chip as counter electrodes. The structures are fabricated on a truncated 1D photonic crystal comprised of a 15-period stack of alternating layers of SiO2/Ta2O5. The Au and Pt stripes are fabricated using bilayer lift-off photolithography, and the gratings are fabricated using e-beam lithography. The structures are arranged into arrays targeting multichannel biosensing. The wafer is covered with CYTOP as the upper cladding with etched microfluidic channels providing access to the sensing surfaces and is wafer-bonded to a Borofloat silica wafer to encapsulate the fluidic channels and enable edge (in-plane) fluidic interfacing. The wavelength response of the grating-coupled plasmonic waveguide sensors is presented along with surface sensing results. Cyclic voltammetry measurements using the Au and Pt stripes as the working and counter electrodes are also presented. [2021-0103] [ABSTRACT FROM AUTHOR]

Directed self-assembly (DSA) is one of the leading candidates for extending the resolution of optical lithography to sub-7 nm and beyond. By incorporating DSA in multiple patterning lithography (DSA-MP), the flexibility and resolution of contact/via patterning can be further enhanced by using multiple block copolymer (BCP) materials. Prior work faces the dilemma between solution quality and efficiency and is unable to handle 2-D templates. In this article, we capture the essence of template and mask assignment in DSA-MP by a new graph model and a new problem reduction: Our graph model explicitly represents spacing conflict edges and template hyperedges; thus, extra enumeration and manipulation of incompatible via grouping edges can be avoided, and arbitrary 1-D/2-D templates can be natively handled. We further reduce the assignment problem to exact cover, which is encoded by a sparse matrix. Our concise integer linear programming (ILP) formulation and fast backtracking heuristic achieve substantially superior solution quality and efficiency to the state-of-the-art work. Moreover, our problem and graph modelling is flexible and extensible to utilize dummy vias to improve manufacturability. To narrow down the search region of dummy vias, we devise a conflict core finding technique, which is general and applicable to conflict core analysis of exact cover and other multiple patterning layout decomposition problems. Experimental results show the effectiveness and efficiency of our approach. [ABSTRACT FROM AUTHOR]

Intracortical neural probes are a key enabling technology for acquiring high fidelity neural signals within the cortex. They are viewed as a crucial component of brain–computer interfaces (BCIs) in order to record electrical activities from neurons within the brain. Smaller, more flexible, polymer-based probes have been investigated for their potential to limit the acute and chronic neural tissue response. Conventional methods of patterning electrodes and connecting traces on a single supporting layer can limit the number of recording sites which can be defined, particularly when designing narrower probes. We present a novel strategy of increasing the number of recording sites without proportionally increasing the size of the probe by using a multilayer fabrication process to vertically layer recording traces on multiple Parylene support layers, allowing more recording traces to be defined on a smaller probe width. Using this approach, we are able to define 16 electrodes on 4 supporting layers (4 electrodes per layer), each with a 30 μm diameter recording window and 5 μm wide connecting trace defined by conventional LWUV lithography, on an 80 μm wide by 9 μm thick microprobe. Prior to in vitro and in vivo validation, the multilayer probes are electrically characterized via impedance spectroscopy and evaluating crosstalk between adjacent layers. Demonstration of acute in vitro recordings in a cerebral organoid model and in vivo recordings in a murine model indicate the probe’s capability for single unit recordings. This work demonstrates the ability to fabricate smaller, more compliant neural probes without sacrificing electrode density. [2021-0017] [ABSTRACT FROM AUTHOR]

Photolithography is the bottleneck for quality improvement in semiconductor manufacturing processes. The decreasing critical dimensions of the semiconductor product requires more effective run-to-run control technology. Currently, Exponential Weighted Moving Average (EWMA) control scheme is widely used in the overlay control of lithography processes. In this article, we address three shortcomings of the current EWMA run-to-run control scheme: (i) the weight parameter λ used in the EWMA control scheme is set as a fixed value instead of adjusted adaptively according to the process changes; (ii) the conventional EWMA control scheme fails to take the model and parameter uncertainties into consideration; and (iii) the adjustable range of the control variables is not considered in the conventional EWMA control scheme. To meet tighter overlay specifications, we propose a new adaptive run-to-run control scheme to address these three limitations. The effectiveness of the new controller is validated through simulation studies. [ABSTRACT FROM AUTHOR]

Blazed gratings are widely used in optical detection devices with the unique property of concentration of light energy to a desired diffraction order. However, traditional substrates for fabricating blazed gratings are easily damaged with the wear and tear in long-term usage under harsh conditions. Here, we propose the fabrication of blazed gratings on sapphire with high mechanical stability by femtosecond laser lithography combined with subsequent reactive ion etching (RIE). Various sapphire blazed gratings with periods from 2 μm to 10 μm and heights from 260 nm to 2 μm were realized to concentrate light energy (wavelengths of 405 nm, 532 nm and 633 nm) to different diffraction orders (1st, 2nd, and 3rd). The results provide great insights for the construction of micro-optical devices that have potential applications under harsh conditions. [ABSTRACT FROM AUTHOR]

Layout hotpot detection is one of the main steps in modern very-large-scale-integration (VLSI) chip design. A typical hotspot detection flow is extremely time consuming due to the computationally expensive mask optimization and lithographic simulation. Recent researches try to facilitate the procedure with a reduced flow, including feature extraction, training set generation, and hotspot detection, where feature extraction methods and hotspot detection engines are deeply studied. However, the performance of hotspot detectors relies highly on the quality of reference layout libraries which are costly to obtain and usually predetermined or randomly sampled in previous works. In this article, we propose an active learning-based layout pattern sampling and hotspot detection flow, which simultaneously optimizes the machine-learning model and the training set that aims to achieve similar or better hotspot detection performance with much smaller number of training instances. Experimental results show that our proposed method can significantly reduce lithography simulation overhead while attaining satisfactory detection accuracy on designs under both DUV and EUV lithography technologies. [ABSTRACT FROM AUTHOR]