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When properly controlled, thermostatically controlled loads (TCLs) can shift their electricity consumption by storing heat in the thermal masses. This capability makes them proper resources to provide variety of services in power grids, specifically intrahour ancillary services. Because TCLs have diverse thermal characteristics, their capabilities of service provision can be different. Therefore, their contribution in service provision and their monetary reward might be different as well. This paper presents a reward allocation mechanism for a load serving entity to determine the payment made to TCLs according to their contribution in the provided intrahour ancillary services. A service provision capability index is proposed to quantify the TCLs capability and prioritize them accordingly. Based on the prioritization results, a reward curve is constructed to determine the TCLs payment according to their contribution to the overall provided service. The proposed rewarding system is demonstrated and verified through numerical simulations using a group of 10 000 heterogeneous heat pumps. [ABSTRACT FROM AUTHOR]

This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%–13.5% switching energy, compared to the state-of-the-art works. In addition, the SR switching scheme effectively reduces the differential nonlinearity and integral nonlinearity to be 1/2, compared to the conventional approach under the same matching conditions. With the proposed SR DAC switching scheme, this paper can handle the same input swing using a half supply and consume smaller power consumption. A cascade-input comparator is developed to consume only 49% of the power and 66% of the decision time with a threefold front-stage gain boost. The test chip occupies a core area of 0.035 mm2 in 90-nm CMOS technology. The prototype consumes 187 nW at 600 kS/s with a single 0.3-V supply voltage. The achieved effective number of bits and spurious-free dynamic range at Nyquist input are 9.46 bits and 73 dB, respectively. The resultant Walden’s figure of merit (FoM) and Schreier’s FoM are 0.44 fJ/conversion-step and 180.8 dB, respectively. [ABSTRACT FROM AUTHOR]

Applications in data-parallel computing typically consist of multiple stages. In each stage, a set of intermediate parallel data flows (Coflow) is produced and transferred between servers to enable starting of next stage. While there has been much research on scheduling isolated coflows, the dependency between coflows in multi-stage jobs has been largely ignored. In this paper, we consider scheduling coflows of multi-stage jobs represented by general DAGs (Directed Acyclic Graphs) in a shared data center network, so as to minimize the total weighted completion time of jobs. This problem is significantly more challenging than the traditional coflow scheduling, as scheduling even a single multi-stage job to minimize its completion time is shown to be NP-hard. In this paper, we propose a polynomial-time algorithm with approximation ratio of $O(\mu \log (m)/\log (\log (m)))$ , where $\mu $ is the maximum number of coflows in a job and $m$ is the number of servers. For the special case that the jobs’ underlying dependency graphs are rooted trees, we modify the algorithm and improve its approximation ratio. To verify the performance of our algorithms, we present simulation results using real traffic traces that show up to 53% improvement over the prior approach. We conclude the paper by providing a result concerning an optimality gap for scheduling coflows with general DAGs. [ABSTRACT FROM AUTHOR]

This paper proposes an accurate impedance model for line commutated converter (LCC) in the stationary frame. The commutation overlap process caused by the transformer leakage inductance complicates the modeling for LCC. Traditional impedance models are derived in positive sequence and negative sequence frame based on the simplified commutation overlap process, which degrades the modeling accuracy and limits the description of frequency coupling. This paper systematically analyzes the effects of the commutation overlap process on the impedance model, and the impedance model with the accurate commutation overlap process is established in the dq-frame. For clearly revealing the frequency coupling phenomenon of the LCC, the complex space vector is employed to extend the impedance model in the dq-frame to the complex αβ-frame. A closed-loop model on PSCAD/EMTDC is used to verify the proposed impedance model in the time-domain and the frequency-domain. The consistency between the simulation results and theoretical analysis effectively verifies the accuracy of the proposed model. [ABSTRACT FROM AUTHOR]

The linearity of high-resolution current-steering digital-to-analog converters (DACs) is often limited by inter-symbol interference (ISI). While dynamic element matching (DEM) can be applied to convert a portion of the ISI to uncorrelated noise instead of nonlinear distortion, DEM alone fails to prevent ISI from at least introducing strong second-order nonlinear distortion. This paper addresses this problem by proposing, analyzing, and experimentally demonstrating a low-cost add-on technique, called ISI scrambling, that, in conjunction with DEM, causes a DAC’s ISI to be free of nonlinear distortion. The ISI scrambling technique is demonstrated in a 1-GS/s, 14-bit DEM DAC implemented in 90 nm CMOS technology. The DAC’s measured linearity is in line with the state-of-the-art and its measured output power spectra closely match those predicted by this paper’s theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents an optimization framework for sequential reconfiguration using an assortment of switching devices and repair process in distribution system restoration. Compared to existing studies, this paper considers types, capabilities and operational limits of different switching devices, making it applicable in practice. We develop a novel multi-phase method to find the optimal sequential operation of various switching devices and repair faulted areas. We consider circuit breakers, reclosers, sectionalizers, load breaker switches, and fuses. The switching operation problem is decomposed into two mixed-integer linear programming (MILP) subproblems. The first subproblem determines the optimal network topology and estimates the number of steps to reach that topology, while the second subproblem generates a sequence of switching operations to coordinate the switches. For repairing the faults, we design an MILP model that dispatches repair crews to clear faults and replace melted fuses. After clearing a fault, we update the topology of the network by generating a new sequence of switching operations, and the process continues until all faults are cleared. To improve the computational efficiency, a network reduction algorithm is developed to group line sections, such that only switchable sections are present in the reduced network. The proposed method is validated on the IEEE 123-bus and 8500-bus systems. [ABSTRACT FROM AUTHOR]

This paper presents an on-line monitoring method of IGBT module bond wires aging based on the phase-frequency characteristics (PFCs) of differential mode (DM) interference signal. Firstly, the collector current variation during IGBT chip switching is analyzed, and the relationship between the aging degree of bond wires and the PFCs of DM interference signal is studied; Secondly, a phase angle characteristic measurement system of DM interference signal is built and used to online monitor the aging of bond wires in IGBT module; Finally, taking the buck converter composed of IGBT module as the equipment under tested, the interference signal is extracted by the RF current probe and processed by the low-pass filter and signal amplifier, then the phase angle characteristics are measured by the oscilloscope board to realize the on-line monitoring of the bond wires aging of IGBT module. The experimental results show that compared with buck converter with healthy IGBT module, the phase angle of DM interference signal in Buck Converter with aging IGBT module is reduced. The proposed method does not need expensive equipment such as spectrum analyzer, and only needs to monitor the aging state of bond wires in IGBT module online through oscilloscope board. Besides, the research method in this paper provides an approximate linear monitoring method for bonding wire lift-off. [ABSTRACT FROM AUTHOR]

Light-emitting diodes (LEDs) are widely used in street lighting, landscape lighting, liquid crystal display (LCD) backlighting, healthcare, etc. As an important part of LED lighting products, LED driver plays a vital role in maintenance costs reduction, energy saving and lifetime prolongation. In this paper, a single-stage LED driver is proposed, which is integrated by a totem-pole bridgeless power factor correction (PFC) unit and several modular LCL-T resonant rectifiers. The totem-pole bridgeless PFC unit and the LCL-T resonant rectifiers are integrated by sharing switches, which can simplify the circuit and reduce the system cost. The output current can be regulated by applying the variable inductor control. Constant duty cycle and fixed switching frequency operation can be achieved as well. The operating principle and the performance of the proposed converter are analyzed in this paper. In addition, a precise parameter design method is proposed by considering the high-order harmonics. At last, an experimental prototype is established to validate the proposed parameter design and variable inductor control method. [ABSTRACT FROM AUTHOR]

This paper presents the possibilities of reducing emergency situations and reducing the time of failure in the power grid. The paper contains a detailed description of the method (algorithm) of operation in emergency situations on the example of a Gas-Insulated Switchgear (GIS) located in one of the system-forming (node) stations in the power grid. The level of detail contained in this paper, which has not been previously encountered in previous publications, favors an in-depth understanding of the possible solutions that result from these emergencies. The above method (algorithm) of activities has been developed based on three levels of research: simulation, theoretical and practical. This means that the simulation analysis that was performed based on theoretical information was experimentally tested as part of an emergency situation in one of the system-forming (nodal) stations in the power system. In order to achieve the result described in this article, one of the most promising types of devices used in power systems was selected - the GIS. This has been confirmed by numerous analyzes of the effectiveness of these devices included in this article. The paper contains a detailed description of the individual steps in the field of corrective actions and aimed at minimizing downtime. In addition, this article provides guidance to monitor possible emergencies that are designed to increase the reliability of the power grid. [ABSTRACT FROM AUTHOR]

The degradation of the electrical contact in a gas insulated switchgear (GIS) is closely related to overheating at the contact. However, the disconnector contact is one of the hot contacts in GIS. Therefore, in this paper, the finite element method was used to solve the three-dimensional multiphysics coupling temperature rise field and flow field in the Single Phase in One Tank (SPIOT) type GIS disconnector under different operating conditions. From the perspective of temperature rise field and flow field, this paper analyzed the temperature rise characteristics under different working conditions and explored the feasibility of the direct application of air, CO2 and C4F7N/CO2 mixed gas to an electrical device. The disconnector temperature rise experiment platform was then built to verify the simulation. The results showed that the temperature rise field and the flow field distribution were similar in four gas environments. SF6 gas had the smallest temperature rise, followed by C4F7N/CO2 mixed gas, and the temperature rise of CO2 and air was relatively large. Therefore, from the perspective of the temperature rise field and flow field, it was feasible to directly apply C4F7N/CO2 mixed gas to an electrical device in order to meet insulation requirements. [ABSTRACT FROM AUTHOR]

This paper presents a new photovoltaic (PV) power systems laboratory module that was developed to experimentally reinforce students' understanding of design principles, operation, and control of photovoltaic power conversion systems. The laboratory module is project-based and is designed to support a renewable energy course. By using MATLAB real-time software tools in combination with digital signal processor (DSP) hardware tools, the module enables students to: 1) design and build dc–dc and dc–ac power converters; 2) design and implement control algorithms for maximum power point tracking (MPPT) and voltage and current regulation; and 3) design and fabricate a printed circuit board for voltage and current sensing, isolation, and gate driving. In these hands-on experiments, by designing and building their hardware and software integrated systems themselves, students learn by doing and experience the engineering transformative process of building a product out of an idea. This paper is motivated by the dearth of literature on the application of project-based learning methodology to PV systems. The module description, the pedagogical and evaluation methodologies adopted, and reflections on the implementations are discussed. [ABSTRACT FROM PUBLISHER]

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study. [ABSTRACT FROM AUTHOR]

Millimeter wave (mmWave) wireless networks are envisioned to bring a very high degree of spatial reuse, i.e., multiple links can operate simultaneously without interference. The vision, however, is becoming doubtful, as recent studies found that non-negligible interference exists due to imperfect beam patterns. In this paper, we extensively measure the spatial reuse issue in a dense 60 GHz mmWave network consisting of multiple access points (AP) and users. Our measurement quantifies the impact of interference on network performance and finds that the existing prediction based on interference-resolving approaches are insufficient. Motivated by the findings, we propose MDSR, which enhances the spatial reuse in 60 GHz mmWave networks. Instead of relying on interference prediction, MDSR takes a new measurement principle of building a conflict graph that implicitly takes into account the impact of both beam imperfection and reflections. Using the conflict graph, MDSR improves the spatial reuse from three dimensions: AP association, user scheduling, and beam selection, which can determine the optimal AP-user-beam combination and minimize interference in each scheduling cycle. We prototype and evaluate MDSR on the testbed using commodity mmWave radios. The evaluation results demonstrate that MDSR improves network throughput by multi-folds compared with the state-of-the-art one. [ABSTRACT FROM AUTHOR]

In the conventional sliding mode control, the four-leg distribution static compensator (DSTATCOM) currents are controlled based on a current error in each phase. However, the four currents in a four-wire system can not be independently controlled variables and hence one of the four controllers is redundant in conventional schemes. Further, the current dynamics of a DSTATCOM converter are coupled through converter pole voltages in the natural reference frame. This leads to cross-coupling in the sliding variable equations with respect to four manipulated input variables. Considering the above points, in this paper, the current due to Thevenin’s equivalent load neutral-point voltage is considered as a fourth independent controlled variable and the corresponding system dynamic equations are presented. To get a decoupled feature, a new sliding surface function is structured. The performance of a DSTATCOM with the proposed control scheme under various operating conditions is validated through a detailed simulation study and experimental results, obtained from a laboratory prototype of four-leg DSTATCOM. [ABSTRACT FROM AUTHOR]

This paper presents a memristive device model capable of accurately matching a wide range of characterization data collected from a tantalum oxide memristor. Memristor models commonly use a set of equations and fitting parameters to match the complex dynamic conductivity pattern observed in these devices. Along with the proposed model, a procedure is also described that can be used to optimize each fitting parameter in the model relative to an I–V curve. Therefore, model parameters are self-updated based on this procedure when a new cyclic I–V sweep is provided for model optimization. This model will automatically provide the best possible match to the characterization data without any additional optimization from the user. In this paper, multiple cyclic I–V characterizations are modeled from ten different tantalum oxide devices (on the same wafer). Additionally, studies were completed to demonstrate the amount of variation present between devices on a wafer, as well as the amount of variation present within a single device. Methods for modeling this variation are then proposed, resulting in an accurate and complete, automated, memristor modeling approach. [ABSTRACT FROM AUTHOR]

In this paper, the stability problem of delayed neural networks is investigated by adopting some switching methods. First, the delay interval is divided into many smaller variable intervals, and when the smaller variable interval is regarded as a mode of the delay, delayed neural networks are modeled as switched systems. Then, by using some switching methods, less conservative stability criteria are derived to ensure the stability of delayed neural networks. Finally, one example is provided to show the effectiveness of the obtained criteria. [ABSTRACT FROM AUTHOR]

DC shipboard power systems have been considered as a promising solution for stricter environmental regulations on ships due to their main benefits in fuel savings with variable speed engines and easy integration of energy storage systems. In order to employ the dc solution in the shipboard power systems, the dc power systems have to be protected from a system fault with protection selectivity to minimize impacts of the fault or to avoid other undesirable situations in the system. For low-voltage dc shipboard power systems, a three-level protection has been proposed: 1) fast action (first)—bus separation by solid-state dc bus-tie switch; 2) medium action (second)—feeder protection by high-speed fuse; and 3) slow action (third)—generator–rectifier fault controls. This paper proposes a new method by means of additional bus capacitance added in main dc buses to help reliable operation of the three-level protection. The principle of the proposed method is introduced and the sizing of the additional bus capacitance is addressed in this paper. With the modeling of the dc shipboard power systems, the analyses of voltage drops for the bus separation failure and fault clearing time for the feeder protection are carried out to verify the proposed method. The results show that the proposed method not only mitigates the voltage drop for the bus separation failure, but also achieves the selectivity and the sensitivity for the feeder protection. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

This paper presents a two-stage microgrid scheduling strategy in which the frequency control reserve (FCR) is incorporated to ensure economic, reliable, and stable microgrid operation in a joint energy and ancillary service market environment. In addition, to using such reserve to limit frequency excursions caused by uncertainties of active loads and renewable generation, this paper is focused on determining the optimal provision of reserve for microgrid operation mode switching to assure sufficient reserve is available and readily deployable at the disposal of the microgrid operator. The scheduling problem is formulated as a two-stage chance-constrained programming (CCP) model where the power balance chance constraints are used to determine the trade-off between operational economy and stability risk exposure. The chance-constrained formulation is then approximated as a deterministic mixed-integer linear programming (MILP) model for solution. Two sets of policy studies are performed through simulation to evaluate the effectiveness of the proposed strategy in enhancing the operational performance of a microgrid through optimal scheduling. [ABSTRACT FROM AUTHOR]

First harmonic analysis (FHA) is arguably the most widely used analytical technique for wireless power transfer (WPT) circuits due to its simplicity. Although FHA can provide closed-form solutions, the existence of rectifier diode forward voltage drop and higher order harmonics, especially the second and third harmonics at variable duty cycle operation, can significantly deteriorate its accuracy. This paper presents an accurate and efficient method called enhanced multiple harmonic analysis (eMHA) for the optimal design and optimal control of WPT systems. The eMHA method considers the nature of nonlinear rectification networks under nonsinusoidal current and reexamines the concept of the equivalent load. As a result, the rectified WPT system is transformed into a series of linear systems with complex load impedances. The steady-state electric quantities can be then explicitly calculated. This enables eMHA to seamlessly work with numerical optimization algorithms to facilitate the automated design and optimization of WPT systems. An example of optimal design and optimal control of a 10 W WPT system is demonstrated. The results obtained by eMHA and FHA are also compared. A prototype of the designed circuit was constructed. The accuracy and effectiveness of eMHA are verified by experimental measurements. This paper is accompanied by a MATLAB-based analytical tool with a graphical user interface demonstrating the effects of circuit variables on electrical quantities and waveforms. [ABSTRACT FROM AUTHOR]

A new single stage three-phase ac–dc converter with four switches and galvanic isolation is proposed in this paper. The new converter is simple and uses fewer switches than previously proposed ac–dc converters of the same type. It is a bridgeless converter that can operate with continuous input current and with any pulsewidth modulated method suitable for a standard three-phase six-switch voltage source rectifier. In this paper, the operation, control, analysis, and design of the proposed converter are explained and its features are discussed. Experimental results obtained from a prototype that confirm the feasibility of the converter are presented as well. [ABSTRACT FROM AUTHOR]

The paper confirms that removing antiparallel silicon carbide (SiC) Schottky barrier diodes (SBDs) from SiC-based inverters offers positive effects without critical impact on inverter loss and electromagnetic interference (EMI) issues, moreover, the removal of SBDs reduces the inverter losses in many cases and noise emissions. This conclusion leads to the possibility to improve the power densities by removing SBDs. However, the removal of SBDs may cause some disadvantages such as an increase of the reverse conduction loss and influence of the body diode recovery phenomenon. Therefore, a comprehensive investigation of these advantages and disadvantages is necessary. In this paper, design criteria are proposed to clarify the conditions in which SiC-based inverters without SBDs have advantages over those with SBDs from the viewpoint of losses. On the other hand, to achieve the removal of SBDs, it is also necessary to confirm that removing SBDs does not cause severe EMI issues. The paper confirms that switching noises are reduced by the removal of SBDs; this is due to the larger damping effect of the SiC mosfets without SBDs than that of SiC mosfets with SBDs. The validity of the theoretical analyses and design criteria is confirmed with comprehensive experimental results. [ABSTRACT FROM AUTHOR]

The demand for multitasking GPUs increases whenever the GPU may be shared by multiple applications, either spatially or temporally. This requires that GPUs can be preempted and switch context to a new application while already executing one. Unlike CPUs, context switching in GPUs is prohibitively expensive due to the large context states to swap out. There have been a number of efforts on reducing the overhead of preemption, through reducing the context sizes or overlapping context switching with execution. All those techniques are reactive approaches, meaning that context switching occurs when the preemption request arrives. In this paper, we propose a dynamic and proactive mechanism to reduce the latency of preemption. We observe that kernel execution is almost always preceded by known commands in both CUDA and OpenCL implementations. Hence, a preemption can be anticipated before the actual request arrives. We study such lead time and develop a prediction scheme to perform an early state saving. When the actual preemption is invoked, an incremental update relative to the previous saved state is performed, much like the conventional checkpointing mechanism. Our design can also choose to drain or checkpointing dynamically and accurately according to the feature of kernels in the runtime. This design effectively reduces the stall time of the preempting kernel due to context switching by 58.6%. Moreover, through careful handling of the saved state, we can also reduce the overall size of saved state by an average of 23.3%, compared with a full context switching. [ABSTRACT FROM AUTHOR]

The main drawbacks of conventional direct torque control (DTC) drives are erratic switching frequency and high torque ripples. The multilevel inverter fed DTC drives are proved to be an alternative for eliminating these drawbacks. Apart from the commonly used three-level inverter fed drives, this paper presents an even-level inverter fed DTC drive. In this paper, a space vector modulated DTC algorithm for a four-level DTC drive is proposed and is implemented by feeding both ends of an open-end-winding induction motor with two-level inverters. The space vector modulation (SVM) algorithm uses a fractal based design for switching voltage vector generation and allied computations are performed in 60 degree co-ordinate system. Representation of vectors as integer values in 60 degree co-ordinate planes avoids fractional arithmetic, which simplifies the algorithmic computations. Detailed analyses of the drive performance under dissimilar operating modes are presented. The loading performance of the drive is experimentally verified on a 5-HP induction motor with a strain gauge type mechanical loading system. No-load experimental results were obtained from a laboratory model 2-HP induction motor drive operated in closed loop mode. [ABSTRACT FROM AUTHOR]

Partial shading condition drastically reduces the maximum power output of photovoltaic array. Partial shading occurs due to several factors, such as flying birds, trees, and passing clouds. Many ways can be mitigated partial shading problems in photovoltaic (PV) array. One among the way is reconfiguration techniques, namely reconfigure the location of PV modules in PV array based on irradiance levels in order to distribute shading effects and increasing maximum power. This paper proposed an optimal SuDoKu reconfiguration pattern for $9\times 9$ total-cross-tied (TCT) PV array to improve maximum power under partial shading conditions. In this approach, the physical location of PV modules in TCT array are rearranged based on optimal SuDoKu style without altering the electrical connections, so that the shading effects can distribute over the array. Further, the performance of proposed pattern investigated with existing SuDoKu pattern under different shading conditions by comparing the global maximum power point, mismatch losses, fill-factor, and efficiency using MATLAB-Simulink. Based on the results of this paper, it concluded that the proposed optimal SuDoKu reconfiguration arrangement is reducing the wiring arrangement and increasing the shading distribution over the array as compared to SuDoKu arrangement. [ABSTRACT FROM AUTHOR]

This paper presents an FPGA-based Digital Real-Time Simulation (DRTS) environment for the analysis of Electromagnetic Transients (EMTs) of power systems that include multiple Power Electronic Converters (PECs). The main features of the proposed DRTS platform are that it i) employs two-value resistor switch model for PECs and thus avoids inaccuracies of Associate Discrete Circuit (ADC) model and ii) does not require separation of PECs by transmission lines (stub lines) and thus accurately represents PECs in close electrical proximity of each other. These features respectively result in a time-variant and large system admittance matrix which significantly increases the computation burden in each simulation time-step and can render it infeasible for real-time applications. To overcome this problem this paper introduces i) Switching-Network Partitioning (SNP) method which is tailored for PECs representation in FPGA and ii) Reformulated Modified Nodal Analysis (RMNA) method to enable computational parallelism between the solution of network and component models in FPGA. SNP enables solution-level partitioning of the PECs and the rest of the system. The developed DRTS platform enables sub-microsecond simulation time-step and provides a fixed hardware irrespective of the system configuration. Performance of the platform is evaluated for a study system and verified versus off-line simulation studies. [ABSTRACT FROM AUTHOR]

In this paper, an overload and short-circuit protection method is proposed for voltage source inverter-based uninterruptible power supply (UPS) system. In order to achieve high reliability and availability of the UPS, short circuit and overload protection scheme are necessary. When overload or short circuit happens, using the proposed control method, the amplitude of the output current can be limited to a constant value, which can be set by the customer to avoid the destruction of the power converter, and to obtain a faster recovery performance as well. The detailed principle of the proposed protection method is discussed in this paper. It mainly contains three parts in the control diagram for current limit, first is the anti-windup in the voltage and current controllers, then the feedforward of the capacitor voltage to the current control loop, the last is the fast reset of the resonant part of the current controller when overcurrent happens. The procedure of developing the control method is also presented in the paper. Experimental results on a commercial UPS system are presented to verify the effectiveness of the control method. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel control strategy to significantly reduce the high-frequency transformer loss in a modular solid-state transformer (SST) based converter system. The modular SST design is based on an ac–dc power-electronic building block comprised of an H-bridge at the ac input and a bidirectional soft-switching isolated dc–dc converter with a medium-voltage insulated high-frequency transformer. The ac terminals of input H-bridges are connected in series and directly coupled to the medium-voltage ac line, while the output dc terminals are all connected in parallel at a low voltage. The key innovation described in this paper, without sacrificing the output performance, is the control scheme that reduces core and winding losses associated with the dc–dc resonant stage by turning off the selected dc–dc converters in synchronism with the line voltage. The prototype for the test described in this paper is based on a modular SST where each module is rated at 50 kVA, with a 200 kHz transformer using 1.7 kV silicon carbide discrete mosfets, but the described control concepts are more broadly applicable to similar topologies. [ABSTRACT FROM AUTHOR]

This paper deals with a multilevel ac–ac double conversion system that uses the intercell transformer (ICT) for applications which include generating systems and the interfacing of renewable energy sources with the utility grids. Each phase of the proposed configuration is formed through the ICT interleaving operation of two multilevel 5-level E-type legs to achieve the 3-phase 5-level back-to-back E-type converter (3Φ5L BTB E-type converter). The analytical procedure to select the inductance and capacitance values of both the input and output filters is described in the paper. Furthermore, the design and implementation of the input/output ICTs and inductors is discussed. The simulation and the experimental results on the 20-kVA interleaved 3Φ5L BTB E-type converter prototype are presented to validate the proposed analysis. [ABSTRACT FROM AUTHOR]

With the rapid development of photovoltaic and fuel cell stacks, high voltage gain converters are urgently demanded. Conventional boost is limited by the exaggerated duty cycle, it is impossible to obtain a high voltage gain while ensuring efficiency. Therefore, a zero-voltage switching (ZVS)-modified SEPIC converter that combines a voltage multiplier cell with traditional SEPIC is proposed in this paper. With detailed parameters design process, this presented converter works at zero voltage switching (ZVS), while obtaining high voltage gain without extremely high duty cycle. Besides, voltage stress is also reduced and low-voltage component with lower parasitic parameters can be used, thus efficiency is maintained. In order to further improve the power density, an integrated inductor scheme is adopted in this paper without changing intrinsic working states of the two inductors. A 36-W prototype is built, and experiments are conducted to verify the advantages of the proposed converter. The efficiency is up to 91.5% at full load. [ABSTRACT FROM AUTHOR]

The flexibility in transmission networks is not fully utilized in existing energy management systems (EMSs). Corrective transmission switching (CTS) is proposed in this two-part paper to enable EMS to take advantage of the flexibility in transmission systems in a practical way. This paper proposes the following two EMS procedures: first, Procedure-A connects real-time security-constrained economic dispatch (RT SCED) with real-time contingency analysis (RTCA), which is consistent with industrial practice; and second, Procedure-B, an enhanced version of Procedure-A, includes CTS in EMS with the proposed concept of branch pseudo limit used in RT SCED. Part-I of this paper presents the methodology, whereas Part-II includes detailed results analysis. It is demonstrated that Procedure-A can effectively eliminate the base case overloads and the potential post-contingency overloads identified by RTCA, and Procedure-B can achieve significant congestion cost reduction with consideration of CTS in RT SCED. Numerical simulations also illustrate that integrating CTS into RT SCED would improve social welfare. [ABSTRACT FROM AUTHOR]

Contribution: This paper introduces the real-world limitations and non-technical aspects of power electronics (PEs) projects to students through innovative tutorial activities. Background: Many electrical engineering curricula offer a PE courses (PECs) for third- or fourth-year undergraduate students. Prior research on PEs education mainly focused on improving students’ experimental skills through developing practical experiments, laboratory activities, and problem/project-based learning. An instructional approach that instead employs real-world knowledge and skills is worth evaluating. Intended Outcomes: Students should be able to consider real-world technical and non-technical limitations when applying theory to design PE circuits and converters, and be able to select and carry out appropriate tests to troubleshoot circuits. Application Design: Prior research on engineering education emphasized the importance of introducing real-world limitations to the students as part of their curriculum. This paper suggests that the tutorial activities presented in a PEC can help students acquire skills in designing and troubleshooting a circuit or system according to desired technical aspects, real-world limitations, and available data. Findings: Evidence of the validity of this approach in a PEC at two Australian universities, over four academic years, is provided. Students receiving the new tutorial activities had percentage scores some 10–15 points higher than those who had traditional tutorials. Another evaluation reveals the students’ vibrant participation in the activities during the new tutorial sessions. [ABSTRACT FROM AUTHOR]

This paper presents a self-learning strategy to control the deactivation of cylinders in large displacement automotive engines. Cylinder deactivation is a useful strategy to reduce emissions and improve fuel consumption without limiting the maximum engine power. A cylinder deactivation algorithm has to balance the target of reducing emissions with drivability concerns. Changing the cylinder configuration at the wrong time or too often negatively affects drivability and fuel efficiency. The paper proposes a self-learning algorithm inspired by the Markov Chain formalism. The proposed algorithm predicts the future fuel consumption and determines the best cylinder configuration based on that prediction. The prediction algorithm is learnt online using past inputs and thus adapts to the specific driver and conditions. Two versions of the algorithm are proposed that use two different inputs. The approaches are validated in simulation on an engine test-bed, showing that the self-learning algorithm yields fuel savings up to 10% without affecting drivability in the New European Driving Cycle. [ABSTRACT FROM AUTHOR]

Resource allocation in mmWave small cell is a key issue of the fifth generation (5G) systems. To solve this problem, we first present a hybrid beamforming structure for base station of small cell, which consists of orthogonal frequency division multiplexing (OFDM), identity matrix and switched-beam. Next, we formulate the joint allocation of the beam and transmitted power on the sub-carriers into a mixed integer non-linear programming problem (MINLP). Due to the non-convexity of this problem, we decompose it into two subproblems which are the beam selection and the power allocation. For the beam selection, we propose an algorithm based on cooperative games. For the power allocation, we present an optimal and sub-optimal solution based on Lagrange duality and non-cooperative games respectively. Simulation results show that the beam allocation algorithm proposed in this paper can effectively improve the sum rate of the system, and the optimal power allocation solution is far superior to the sub-optimal one in sum rate. [ABSTRACT FROM AUTHOR]

Graphene has attracted great interest for its distinctive band structure and physical properties. Results from previous studies show that a graphene cathode can provide stable field emission and intense emission in a vacuum. In this paper, a graphene cathode was fabricated using chemical vapor deposition (CVD) on copper electrodes, and the breakdown of the cathode in a high-pressure gas was studied. A low-jitter, self-breakdown gas spark switch based on a graphene cathode is proposed in this paper. The impulse-breakdown characteristics of this switch in a quasi-uniform electric field were studied. When the gap length is 5 mm, and the gas pressure is 0.6 MPa, the average breakdown voltage ($U_{\mathrm {BD}}$) is nearly 85.9 kV, and the voltage jitter is only 3.2%; these values are much lower than those for pure copper cathodes and graphite cathodes. The graphene cathode is found to be a suitable choice for use as a high-power gas switch in applications requiring an intense emission source. [ABSTRACT FROM AUTHOR]

This paper presents a balancing algorithm for the so-called Director Switch, a controlled, reverse conducting, self-powered, high-voltage switch, using series-connected insulated gate bipolar transistors (IGBTs). This is a key component on two new voltage-source, high-voltage direct current (HVDC) converter topologies. These, which promise efficiency, cost, and size reductions, are an alternate arm converter and a series bridge converter. One of the main design challenges of the director switch is how to supply the IGBT gate drivers, and other auxiliary electronics while overcoming the high-voltage insulation barrier to ground level. In this paper, this is achieved by using the energy stored in a capacitive clamp snubber circuit, which also helps with the overvoltage mitigation during rare hard-switching events. However, the clamp capacitor and by proxy the IGBT voltages become highly unbalanced during operation, compromising the integrity of the switch. This paper presents a balancing strategy that consists in applying a controlled delay in the switching of the IGBT levels, in a way that forces a voltage balance on all the switch levels. The paper explains the unbalance. Then, the balancing strategy is explained and validated on simulation and on a high-voltage experimental rig, on switches comprising two and three series-connected IGBTs, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

A high-frequency high voltage gain discontinuous conduction mode coupled-inductor boost LED driver based on planar component is presented in this paper. GaN switch is adopted with lower conducting resistance and higher switching speed. Zero voltage switching (ZVS) is achieved at the same time to reduce high switching loss caused by high switching frequency. Compared with the previous work, the voltage gain is higher and efficiency is higher because of ZVS. This paper focuses on high efficiency; therefore, resonant gate driver is adopted and efficiency is increased by 0.6%. In terms of the coupled-inductor, planar component is used and parameter optimization is also proposed to realize lower loss, including wingding loss and fringing loss caused by the air gap. A 500 kHz 36 W prototype has been designed to demonstrate theoretical analysis. In addition, comparison of drive loss between the resonant gate driver used in this paper and conventional driver implemented by Si8271 is made, revealing advantages of the resonant driver. Obtained efficiency was up to 92.1% at full load. [ABSTRACT FROM AUTHOR]

The use of electronic equipment and other dc-compatible appliances in homes and offices is increasing at a very fast rate, as well as the distributed generation of energy. These two statements will most likely trigger, in a near future, the adoption of district-scale dc grids, connecting dc microgeneration plants and consumers, in an effort to cut the number of conversion steps required to deliver power to dc appliances. DC–DC converters will be fundamental in these systems, allowing the establishment of several voltage levels. The reliability of these converters plays a critical role, ensuring service continuity of the loads connected to them. With the increment of reliability in mind, this paper proposes a simple yet effective open-circuit fault diagnostic method suitable for interleaved dc–dc boost converters, but equally functional for other dc–dc converter topologies. The improvements introduced in this paper greatly simplify the diagnostic action, while making the correct diagnostic of faults independent of the switching duty cycle. Moreover, an alternative reconfiguration scheme is proposed to mitigate the adverse impacts of such faults. To prove the effectiveness of these strategies, a three-phase interleaved boost converter prototype was used in the experiments. [ABSTRACT FROM AUTHOR]

This paper presents a linearity-enhanced 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a high-speed and low-noise comparator. A p-well floating technique for linearity improvement of sampling switch is proposed. The total parasitic capacitance of the sampling switch is depressed compared to conventional structures. Also, the variation of parasitic capacitance is reduced. Furthermore, a substrate voltage boosting technique is proposed to depress the noise of comparator at a high conversion rate. In addition, an improved parallel SAR logic is exhibited to increase the speed of SAR feedback loop and enhance the settling of digital-to-analog converter (DAC). Last, an adaptive sampling technique is utilized to increase the sampling time of SAR ADC. The proposed SAR ADC is fabricated in the 65-nm CMOS process, consuming 2 mW at a 1.2-V power supply. It achieves a signal-to-noise distortion ratio (SNDR) >55.6 dB and spurious-free dynamic range (SFDR) >69 dB at 160 MS/s. The ADC core occupies an active area of 0.023 mm2, and the corresponding figure-of-merit (FoM) is 25.4 fJ/conversion-step at Nyquist input. [ABSTRACT FROM AUTHOR]

In this paper, two novel $4 \times 6$ filtering Butler matrices with uniform and nonuniform power distribution are proposed. The matrices, consisting of a network of coupled resonators and two phase shifters, provide power division and phase shift together with a bandpass transfer function. The analytical synthesis procedures for the $4 \times 6$ filtering Butler matrices are presented. To verify the concept experimentally, two $4 \times 6$ filtering Butler matrices, operating at 2.4 GHz, with uniform and nonuniform power distribution are designed, fabricated, and measured. Simulated and measured results are found to be in good agreement with each other. Multibeam antenna arrays are realized by using the Butler matrix, and the theoretical analysis has been confirmed by measurements of multibeam antenna arrays, which show reduced sidelobe level (SLL). [ABSTRACT FROM AUTHOR]

A common method for load sharing is using frequency and voltage droop controllers because there is no need to have communication links in the microgrid (MG). However, the droop control strategy has a drawback, that is, it imposes voltage and frequency deviations, which can be fixed by adding a secondary control loop. On the other hand, if the MG operates connected to the grid, a tertiary controller for regulating the injected power must be added. This paper proposes a multitask fuzzy secondary controller (FSC) applied to ac MGs acting only on the secondary control layer. The proposed controller allows stand-alone and grid-tied operations, regulating the voltage and frequency in the secondary and the active and reactive powers, simultaneously, without a tertiary controller. Stability analysis are presented showing that the FSC keeps the MG stable while operating within a proposed operation range. A MG simulation test bed based on power inverters is presented to validate the FSC operation and to compare to conventional hierarchical controller. The proposed FSC fixes the deviations in the same way as the conventional controller during the islanded operation tests and allows the MG to inject power into the grid. [ABSTRACT FROM AUTHOR]

This paper presents a new signal representation called frequency invariant transformation of periodic signals (FIT-PSs) in the context of non-intrusive load monitoring (NILM). Compared to former approaches where a conglomeration of different signal forms are used, the presented approach is based on a single signal form containing all information. The core idea of this paper is to use the original current waveform relative to the reference voltage as a signature for NILM. In general, the relation of sampling and grid frequency is subject to continuous fluctuations. Therefore, FIT-PS converts uncorrelated sample data to a fixed multiple of the grid frequency. The advantages are that the information of the current signal, as well as the phase shift between voltage and current signal, are completely contained in the FIT-PS signal representation. For classification, a neural net was applied to the home equipment laboratory dataset 1. Features created by FIT-PS are superior to the standard features. With 18 different devices, a detection rate of up to 90% is achieved. In particular, when several consumers are active at the same time, the new signal representation is much more robust and leads to a better detection rate. However, a long short-term memory net with FIT-PS signal representation provides the best results. [ABSTRACT FROM AUTHOR]

The concept of demand response (DR) is relatively well-known. There is an extensive literature on possible DR system services and evaluation of regulative potential, based on statistical analyses of data concerning loads suitable for provision of the service. Some of the presented concepts have been implemented in real applications. However, as far as the authors know, this paper presents the first attempt at an implementation of a decentralized active DR system (DADR), without communication between devices, in the form of a laboratory setup consisting 1000 devices enabling primary regulation support. The proposed implementation covers an original hardware design, a software platform for flexible system development, a laboratory arrangement enabling an objective assessment of the quality of service provided by the DADR system, as well as results of a pilot test in real power system. The practical realization of the DADR system is based on an earlier elaborated and theoretically investigated control algorithm, presented in previous papers. [ABSTRACT FROM AUTHOR]

Inverter-based Volt/Var control (VVC) methods can effectively address issues of voltage deviations and constraint violations, as well as reduce network power losses in active distribution networks. Conventional VVC mainly relies on rule-based, mathematical, or heuristic methods. However, these methods can be inefficient or even infeasible for large-scale systems, especially when operational uncertainties are considered at both spatial and temporal scales. To this end, firstly, this paper formulates a multi-region coordinated VVC optimization problem to simultaneously minimize bus voltage deviations and network power losses. Furthermore, with the problem being formulated as a partially observable Markov Game, a multi-agent deep deterministic policy gradient (MADDPG) algorithm is modified to solve this problem. Each region, which is a sub-network with a control center, is modeled as an agent and learns to optimize inverter reactive power output setpoints through exploration in virtual environment and improved neural network training procedure. Spatial and temporal uncertainties of photovoltaic power generation and loads are modeled by stochastic programming as scenarios in the MADDPG algorithm. This algorithm can address the uncertainties to guarantee solution robustness. Thus, this paper eventually proposes a robust regionally coordinated VVC method, and numerical simulations indicate high computing efficiency and robust optimum. [ABSTRACT FROM AUTHOR]

Large software defined networks use a cluster of distributed controllers to process flow requests from a massive number of switches. To cope with traffic dynamics, this paper studies a new problem of how to improve the residual capacity available at the controllers to handle request bursts experienced at the switches. While the total residual capacity is a constant under a given total capacity of all controllers and a given total workload from all switches, this paper considers the residual capacity available to each individual switch, which depends on how the switches are mapped to the controllers for management. We focus on how to maximize the minimum residual capacity available to any switch. The prior work either provides poor residual capacity or incurs heavy synchronization overhead by simulation results. This paper proposes a new method called indirect multi-mapping that achieves both high residual capacity and low synchronization cost. We formally define a non-linear integer optimization problem for max-min residual capacity under indirect multi-mapping. We then approximate the problem as two sub-problems: switch-controller mapping selection and weight assignment for each switch-controller mapping. We solve these sub-problems and formally analyze their approximate factor. We implement the proposed solution on an SDN testbed for experimental studies and use simulations for large-scale investigation. Our evaluation shows that indirect multi-mapping improves the minimum residual capacity by 49.8% on average and reduces the synchronization cost by 41.9-60.3% on average when compared with the alternatives. [ABSTRACT FROM AUTHOR]

The dc-dc converters with high step-up DC-voltage gain play a vital role in integrating low voltage DC sources. Though several converter topologies are reported in the recent past, attempts have been made to reduce the components, especially the switching devices, passive elements, converter losses, etc., of the converter. A novel DC-DC converter topology, viz., single switched impedance network (SSIN)-based converter with n-stage is proposed in this paper. The operation of the SSIN based converter in continuous and discontinuous conduction modes are discussed. The effect of parasitic elements on DC-voltage gain and efficiency of the SSIN is carried out. The small-signal model of the SSIN converter is derived. The performance of the SSIN converter is compared with the similar converter topologies. The 500 W prototypes of the SSIN with n = 1 and n = 2 are fabricated, and the experimental results are presented in this paper. To improve the converter performance, SiC-based semiconductor devices are used. The SSIN converter with two-stage has low switch loss at 500 W load, improved efficiency during high power and high output voltage operation, the switch stress of Vo/2, etc. [ABSTRACT FROM AUTHOR]

The application of Hall-based BLDC motors ranges from automotive accessory components such as oil and water pumps to high speed compressors. This paper proposes a new twelve-step unsymmetrical 160° commutation strategy using a single Hall-effect sensor method for brushless DC (BLDC) motor drives. The signal from the Hall-effect sensor is used to generate a number of pseudo Hall signals via a proposed speed-position estimator. The pseudo signals are then employed to control switching logic of a voltage source inverter (VSI). The effectiveness of the single Hall sensor method is examined on the unconventional 160° strategy, and on conventional 120°, 150° and 180° strategies with promising results. The paper presents a detailed comparison of the twelve-step unsymmetrical 160° commutation strategy with six-step voltage space vector that is used in conventional 120° and 180° strategies, and twelve-step symmetrical voltage space vector that is used in 150° strategy. Simulation results are validated via experimental measurements on a laboratory set-up using a real time dSPACE control environment, a representative BLDC motor prototype, a VSI and associated control components. [ABSTRACT FROM AUTHOR]