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The power system planning and protection studies are becoming more challenging due to the rapid increase in penetration levels of converter-interfaced renewables. Type-IV wind turbine generators (WTGs) and photovoltaic panels are interfaced to the grid through a full-scale converter, and their short-circuit current contributions are mainly designated by the converter control and associated current limits. This paper proposes a new phasor domain modeling approach for the wind parks (WPs) with Type-IV WTGs, using the concept of control-based equivalent circuits. The proposed model precisely represents the detailed electromagnetic transient (EMT)-type model in steady state, and is able to account for the fault-ride-through function of the WTG control as well as its specific decoupled sequence control scheme in addition to the traditional coupled control scheme. Although the collector grid and WTGs inside the WP are represented with their aggregated models, the overall reactive power control structure of the WP is preserved by taking the central WP controller into account. The accuracy of the proposed model is validated through detailed EMT simulations. [ABSTRACT FROM AUTHOR]

Many applications that use high-energy plasma are realized using microwave tubes (MWT) that operate at peak power in the range of hundreds of MW and frequency in GHz. One failure mode of the MWT is due to the excess energy in the tube during internal arcing events. Crowbar is used to protect the MWT by diverting the energy during fault. To compute the energy released into the MWT, the dc fault current model and the MWT model are essential. An equivalent fuse wire model is utilized for the MWT for the crowbar applications. The paper proposes a model for the dc fault current, the analysis for which is based on Joules Integral energy concept. The model provides flexibility to choose a range of practically observed reactance to resistance ratio ($X{/}R$) of transformer and also allows the use of a range of dc current-limiting resistances that are utilized in the high-voltage (HV) power supply circuits in microwave applications. The nonlinearity of the system due to the multipulse diode rectifier is also considered by introducing a correction factor in the model. This paper shows that the same correction factor can be applied for both dc side parallel- and series-connected rectifier circuits. Both dc fault current and MWT models are verified experimentally. Using the model, a 10 kV, 1 kA crowbar is built to limit the energy in MWT below 10 J. [ABSTRACT FROM AUTHOR]

This paper presents a novel method to estimate the number of shorted turns in a permanent magnet synchronous machine (PMSM) following the detection of interturn short-circuit (ITSC) fault and its location. In this proposed method, PMSM is excited through a low sinusoidal voltage at standstill condition to obtain the winding resistance and synchronous inductance by current response. It is shown that the ITSC fault introduces variation in the current response, which can be used to calculate the number of shorted turns under zero fault resistance assumption. Using this practical procedure, the fault severity can be estimated directly in a straight-forward manner. In other words, the severity estimation for a given machine can be done without complex machine modeling or experiments on ITSC prototype with multiple taps. The findings in this paper are essential for a comprehensive solution including fault mitigation algorithms and postfault operations. In order to verify the findings, a three-phase equivalent circuit model supported by finite element analysis results is used to take saturation and space harmonics into account. In addition, experimental results are presented to demonstrate the validity and practicability of the severity estimation. [ABSTRACT FROM AUTHOR]

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles. [ABSTRACT FROM PUBLISHER]

There are many methods to ground generators. This paper will discuss the advantages and disadvantages of each. This paper will progress from low-resistance grounding of a single source to complex systems with multiple sources. Although this paper is focused on medium-voltage bus-connected generators, there is no reason the techniques could not be utilized in low-voltage multiple-source systems. [ABSTRACT FROM AUTHOR]

To minimize ground fault during a line-to-ground fault condition, it has been a common practice to use high-resistance grounded (HRG) power systems, both at low voltage and at medium voltage (MV). The criteria for designing HRG systems are very well known to the industry; however, the opinion of industry experts has been divided on limiting the use of HRG systems for MV systems to voltages of less than 4.16 kV and phase-ground fault currents of less than 10 A without clarifying that it applies to systems that require continuous operation upon first detecting line-to-ground fault, as it is now in the Recommended Practice for Grounding of Industrial and Commercial Power Systems. This paper will review the background history of HRG power systems and their application to MV systems for specific industries and will make the case that voltages need not be limited to less than 4.16 kV and the phase-ground fault current to less than 10 A, so long as the faulted power system is isolated within ten cycles and that there are no directly connected motors. This paper will discuss the potential damage and protection requirements of HRG systems for MV applications to ensure that a line-to-ground fault is cleared before it involves other phases to make a multiphase arcing ground fault. [ABSTRACT FROM AUTHOR]

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein. [ABSTRACT FROM AUTHOR]

This paper deals with multiple soft fault diagnosis of nonlinear analog circuits and offers a method that allows locating the faulty parameters and evaluating their values. The method works with a system of nonlinear algebraic test equations, which are not given in explicit analytical form, and actually may possess multiple solutions. The solutions are specified by one or several sets of the diagnostic parameter values that meet the test. To find the multiple solutions, an extended systematic search method has been developed. The diagnostic algorithm proposed in this paper exploits this method and brings a new concept for finding the actual solution. As a result, the diagnostic process is considerably improved. It can be applied to bipolar junction transistor and CMOS circuits manufactured in micrometer and nanometer technologies. In the last case, however, the transistors are characterized by intricate models (PSP 103 or BSIM 4). In consequence, the CPU time increases due to very complex sensitivity analyses of the circuits required by the diagnostic method. In such a case, the proposed approach is useful at the preproduction stage, where the CPU time is offline and not crucial. For illustration, two numerical examples are given. [ABSTRACT FROM PUBLISHER]

Digital signal processing (DSP) cores are an integral part of consumer electronics devices. This paper presents a novel methodology for obfuscation of transient fault secured circuits. The approach presented obfuscates fault secured DSP circuits such that the functions of the resulting hardware become non-obvious to an adversary (hindering reverse engineer process). The proposed methodology employs hybrid transformations in succession such as redundant operation removal, resource transformation, and connectivity change using tree height transformation, logic transformation, etc. These are achieved without affecting the functionality of the underlying DSP circuits or requiring significant increase in silicon footprint. The proposed methodology integrates an enhanced fault security feature using multi-cuts that ensures maximum detection capability against transient faults in the DSP circuit. Results of proposed approach indicate stronger obfuscation and enhanced fault security at lower design cost (avg. reduction ~14%), compared to prior art. [ABSTRACT FROM AUTHOR]

Large induction motors used in variable speed industrial applications (digging, traction, etc.) undergo dynamic stresses at high power levels. Their lifetime is reduced as compared with constant speed motors and downtime costs are very high. To monitor the condition of such motors, advanced sensor instrumentation is considered, including installation of Hall effect flux sensors inside the motor airgap. Such an advanced instrumentation enables continuous measurement of the airgap flux in both time and space domains simultaneously. This allows for advanced fault detection algorithms. This paper presents a method for early diagnosis of stator turn-to-turn faults and static eccentricity, and differentiation between these two conditions. The paper demonstrates that the proposed method detects, localizes, and quantifies both faults with high accuracy and sensitivity. Furthermore, each fault can be detected at an incipient stage and its development can be predicted. The results of the presented study have been supported by both simulation and experimental results obtained on a laboratory scale induction motor. Based on the results presented in the paper, a real-time condition monitoring system has been developed. [ABSTRACT FROM AUTHOR]

Doubly fed induction machine (DFIM) is increasingly being preferred in large rated variable speed pumped storage power plants (PSPP), because it provides better energy efficiency due to optimization of pump/turbine efficiency. Increased efficiency results from the flexibility of operating speed at different hydraulic heads. In doubly fed configuration, partial rated power converters feed the rotor circuit. Parallel-connected back-to-back voltage-source converter on rotor side is responsible for starting, braking (dynamic/regenerative), and speed (real power) control of the unit. This paper presents smooth starting and regenerative braking, and assesses performance under power converter and sensor faults of a 250-MW DFIM pump turbine unit to be commissioned in Tehri PSPP, India. Survivability of the unit during faults is analyzed based on current, speed, and dc-link voltage. Further, this paper investigates fault-tolerant operation of 250-MW DFIM unit at open-circuit fault in converters. A 2.2-kW DFIM is tested in the laboratory to corroborate the simulation. [ABSTRACT FROM AUTHOR]

This paper introduces a new approach, based on faster-than-real-time (FTRT) analysis, to predict out-of-step (OOS) condition of a turbine-generator (T-G) unit subsequent to a fault scenario. The proposed FTRT analysis is based on 1) solving a state-space model of the T-G electromechanical system and corresponding controllers without the need for online measurements, and 2) an estimated Thevenin equivalent of the rest of the power system. The measurement-free FTRT analysis is carried out after the Thevenin parameters are estimated subsequent to the fault clearance instant. Equal area criterion is applied on the predicated variables to detect OOS condition. A reliable decision can be made based on this approach, since it does not involve simplifying assumptions contrary to the existing approaches. The FTRT approach accurately considers the impacts of the detailed model of the generator, automatic voltage regulator, prime mover, governor system, and the host power system. This paper provides detailed mathematical formulation for the proposed OOS detection method and verifies its feasibility and accuracy based on single machine and large test systems. The proposed approach is also implemented on an industrial platform and evaluated. The results confirm that the proposed approach can accurately identify OOS conditions, earlier than the rotor angle noticeably increases. [ABSTRACT FROM AUTHOR]

Identical instances of a logic block are included in a design to improve its performance or reliability. This allows instances at close proximity to be tested by comparing their output responses, alleviating the need to know which tests will be applied, or what the fault-free response is. This paper considers an approach to online testing where the primary output sequences of identical finite-state machines that receive the same primary input sequences are compared to detect faults. To address the hardware and delay overheads of bringing one of the machines to the same state as the other before starting the output comparison process, this paper describes an initialization process where only part of the state of one machine is loaded into the other, and subsequences of their common primary input sequences are used for completing the initialization process. A unique feature of this process is that it addresses the situation where the input sequences that are applied during online testing, and the initial state for output comparison, are unknown. With this initialization process it is possible to start the output comparison process at an arbitrary point during functional operation. Experimental results for benchmark circuits demonstrate the percentages of state variables who values need to be loaded from one machine to the other, the fault coverage that can be achieved by output comparison following initialization, and the occurrence of failures in the initialization process. [ABSTRACT FROM AUTHOR]

The development of voltage-source-converter (VSC)-based high-voltage direct current (HVDC) systems has increased significantly. However, the implementation of VSC-HVDC systems is limited for lacking fast, low-loss, and reliable circuit breakers. Hybrid dc circuit breakers (DCCBs) may help to improve this situation. In this paper, an efficient modular multilevel converter (MMC) HVDC system model based on the Zhangbei–Beijing \pm \text500\,\textkV bipolar MMC-HVDC transmission (overhead line) project is first established. Then, the system transient characteristics are investigated involving permanent line-to-ground faults (LGFs), permanent short-circuit faults (SCFs), temporary LGFs, and temporary SCFs with either ac circuit breakers (ACCBs) or DCCBs in service. Finally, the performances, including the fault clearance and recovery, comparison of DCCBs with two different breaking methods, and comparison of ACCBs and DCCBs, in the MMC-HVDC system are presented. This paper provides a deep understanding of LGF and SCF in the MMC-HVDC systems, operation of DCCB, and comparison of faults clearance and recovery under these faults conditions using ACCB and DCCB, respectively. Results also benefit the application of the DCCB and the operation strategies in high-voltage and high-power MMC-HVDC systems with overhead lines. [ABSTRACT FROM AUTHOR]

Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don’t-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k . KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don’t-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers. [ABSTRACT FROM PUBLISHER]

Traditionally, flux distributions in transformer cores are modeled as a 2-D problem. However, experimental studies indicate that 3-D models are needed. The main reason is that limbs of circular cross section are combined with roughly semi-circular yokes. At the joints, this yields shifts of overlap regions as a reason of significant (off-plane) normal direction (ND) induction B\mathrm {ND} . This paper reports a first corresponding 3-D modeling of a two-package one-phase core with the consideration of non-linear characteristics of material. For corners, the so-called critical induction B\mathrm {CRIT} of joints—as arising close to 1.4 T—is considered. Two instants of the cycle of global magnetization are addressed, i.e., B\mathrm {GL} = 1.7 T for normal operation and 1.9 T as a value that may arise for dc bias. For 1.7 T, the results indicate strong inhomogeneity, in particular in the wide main package of the core. On the other hand, 1.9 T is characterized by distinct homogenization. As 3-D effects, the cycle of magnetization involves distinct changes of flux in ND, with values up to more than 0.2 T. Half-cycle saturation is indicated especially for inner (window-sided) corner regions. The corresponding consequences on local magnetostriction (MS) values are over-proportional due to the complex dependence of strain $\lambda$ and induction. The so-called butterfly curve is dynamically passed beyond the turn point and even into its positive range. In particular, this yields distinct distortion of $\lambda$ , which can be assumed as a source of over-proportional rises of A-weighted noise. Apart from MS, further enhancement is to be expected from inter-laminar forces. [ABSTRACT FROM AUTHOR]

This paper proposes a fault location method based on the adaptive control of neutral-to-earth complex impedance in a resonant grounded system, whose neutral point grounds are via an electromagnetic hybrid Petersen coil (EHPC). The EHPC can be equivalent to a parallel circuit of a negative resistance and an inductance, both of which can be adjusted. When a permanent single line-to-earth fault occurs, the ground-fault current will be compensated to almost zero, and the capacitance to earth and leakage resistance of system can be measured accurately for subsequent fault location. Then, the complex impedance of EHPC is adjusted, and the faulty feeder and its faulted section can be identified online based on the characteristics that the measurements of zero-sequence admittances of points along the faulty feeder change with the system's neutral-to-ground complex impedance. The detection criterion is certain and unique, without comparing all of the feeders. This paper also proposes an adaptive jitter adjustment and decoupling control of neutral-ground complex impedance by EHPC, which is adaptive to the grounding transient resistance and is repeatable, and can ensure that the magnitude of the zero-sequence parameter is large enough to be measured while without arc re-ignition, including in high impedance fault states. Simulations and experiments verified the feasibility of this fault location method and its control strategy. [ABSTRACT FROM PUBLISHER]

Security-sensitive usage models, such as implantable and wearable medical devices are prone to algorithmic cryptographic attacks as well as malicious implementation attacks. The cryptographic algorithms in these cryptosystems, such as lightweight block ciphers utilized in constrained applications, face significant tradeoff between the high level of security and the efficiency of their implementation metrics. For thwarting fault analysis attacks, among effective variants of active implementation attacks, and also to detect natural faults, efficient fault diagnosis schemes for these lightweight block ciphers are essential. In this paper, for the first time, we propose error detection schemes for lightweight block cipher, KLEIN, to ameliorate its error resiliency with low hardware complexity. The proposed fault diagnosis architectures are for linear and nonlinear components of this cipher. We also consider the notion of fault space transformation for lightweight cryptography and present its potential complications. The implementation of the proposed schemes through variants of Xilinx field-programmable gate arrays and the error coverage assessed with fault injection simulations show the effectiveness of the proposed schemes with acceptable footprints. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) with nearest level modulation (NLM) is widely used in the high voltage applications for low switching frequency and easy implementation. Existing literature has not provided a complete submodule (SM) fault ride-through scheme for MMC with NLM. In this paper, a strategy including fault detection, localization, redundancy, and recovery is proposed to ensure continuous operation of MMC under IGBT open-circuit faults conditions. It only requires a few hardware and software resources. The features of MMC and SMs with three types of failures are studied, respectively. Based on these, the fault detection method is proposed by using a simple hardware circuit, thus high computation complexity is avoided. Since current fault localization schemes are limited to MMC with carrier phase shifted pulse width modulation, this paper further proposes a strategy for MMC with NLM to locate the faulty SM and identify the fault type. After this, the fault redundancy and the proposed fault recovery method are applied to eliminate the fault and then exit the failure state. Therefore, the ability of SM fault ride-through can be realized. Analysis of failure characteristics are verified in simulation. Experimental results based on a single-phase MMC prototype with 11 SMs per arm are presented to demonstrate the validity of the proposed fault ride-through strategy. [ABSTRACT FROM AUTHOR]

Sympathetic interaction between transformers is a quite normal phenomenon in power systems. For the purpose of preventing transformer differential protection relays from malfunction, this paper proposes a morphological method for the identification of sympathetic inrush, which is the first time when mathematical morphology is applied in this field. Since the waveform of differential current is symmetrical in an internal fault case while asymmetrical in a sympathetic inrush case, the proposed method uses a morphological operator to extract the peaks and valleys of the differential current to distinguish sympathetic inrush. Considering the possible current-transformer (CT) saturation conditions, this paper combines a morphological gradient with a weighted mathematical morphological operator to improve the effectiveness of the proposed method. The proposed method is evaluated on data collected from simulation cases established in PSCAD/EMTDC and from laboratory experiments, respectively. Identification results have verified that by comparing with the traditional second harmonic restrain method, the proposed method can distinguish sympathetic inrush from an internal fault current more accurately and more effectively, even when the CT is fully saturated. [ABSTRACT FROM PUBLISHER]

An industrial medium voltage (MV) system usually consists of multiple power sources such as utility tie transformers and generators. These are normally low-resistance grounding as shown in Fig. 1 . When a ground fault occurs at the generator stator, ground currents from its own neutral circuit and external power sources will flow into the fault and cause damages to the stator winding. The IEEE Generator Grounding Working Group issued a guideline for generator grounding practices, which recommends using a hybrid grounding system to minimize the ground fault damage induced by its own neutral grounding source. This paper will evaluate the total ground fault damages based on the arcing power energy to derive a maximum MV system ground current that would limit the ground damage to 1800 kW-cycle or 30 kJ as the minimum arcing power energy damage as suggested by Conrad and Dalasta [10]. [ABSTRACT FROM PUBLISHER]

An online approach based on application of search coil for transformer winding fault detection is presented in this paper. Earlier attempts report use of search coil for the detection of transformer interturn fault. This paper extends application of search coil for detection of winding displacement in addition to interturn fault identification. Experimental results based on specially designed 10-kVA transformer are presented to analyze search coil voltages during healthy and faulty conditions. The algorithm detects phase ($U$ , $V$, $W$), side (LV, HV), and precise location of the fault. Discrimination between interturn fault and winding radial displacement is also achieved by search coil voltage analysis. The results are experimentally verified based on impedance analyzer plots. Experimental analysis indicates that the proposed method is independent of load on the transformer, vector group, nature of winding, balanced or unbalanced source voltage, source voltage harmonics, inrush, and overexcitation conditions. [ABSTRACT FROM AUTHOR]

High-voltage high-power pulse switches are built with semiconductor devices, preferably thyristor, due to the superior performance that they offer. Triggering methods classify the thyristor as electrically triggered thyristor (ETT) and light triggered thyristor (LTT). Due to the specialized gate constructions and many build-in protections, the cost of LTT is much higher than ETT. The operating modes in applications, such as crowbar, do not require all these build-in protections. In this paper, the operation of a crowbar is analyzed, and the build-in protections of LTT are reviewed. This paper proposes three experiments for the design selection of thyristor, between ETT and LTT, for crowbar applications. The experiments cover the electrical performance as well as electromagnetic emissions in a 10-kV, 1-kA crowbar built with both ETT as well as LTT, which can be used to benchmark the performance of the crowbar circuit. From the three experiments, the performance of ETT-based crowbar is found to be comparable with LTT-based crowbar. Based on the experiments carried out with the proposed benchmarking approaches, this paper shows that ETT-based crowbar is a cost-effective solution for crowbar applications. [ABSTRACT FROM PUBLISHER]

Saturated iron-core superconducting fault current limiters (SISFCL) are becoming increasingly well known for their effective and reliable current limiting capabilities. The device is capable of producing very low impedance during normal operation and substantially high impedance during fault. Its ability of changing impedance can be attributed to the change of magnetic state of the ferromagnetic core of the device from saturation to unsaturation. The SISFCL employs a dc source to maintain the saturated state of the core for normal operation with the help of a superconducting coil. The high ac ampere turns during fault not only bring the core to unsaturation, but also cause alarmingly high voltage to develop across the dc source. Hence, the protection of the dc source is of great concern as the high voltage is capable of destroying the source and additionally, force the superconducting material to quench. In this paper, the SISFCL is analyzed using the finite element method and the field suppression method of dc source protection is discussed and shortcomings are pointed. The novelty of the paper lies in the use of shorted winding for the improved performance of the field suppression system. For the finite element method (FEM) analysis, the ANSYS Maxwell 2D software is utilized. [ABSTRACT FROM PUBLISHER]

Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan chains are partitioned with a higher expansion ratio than normal in scan compression mode and then are gradually concatenated based on a cost function to detect any faults that could not be detected at the higher expansion ratios. It improves the overall test compression ratio since it potentially allows faults to be detected at the highest expansion ratio. This paper introduces a new cost function to choose scan chain concatenation candidates for concatenation for multiple expansion ratios. To avoid TDV and TAT increase by scan concatenation, the proposed method takes a logic structure and scan chain length into consideration. Experiment results show the proposed method reduces TAT and TDV by 53%–64% compared with a traditional scan compression method. [ABSTRACT FROM AUTHOR]

Reliable voltage measurement is a pre-requisite for correct operation of a relay's voltage-dependent functions. The secondary circuit of a relay's voltage transformer (VT) is usually fuse-protected. The blowing of a VT's three-phase fuses prevents correct voltage measurement, commonly referred to as the loss-of-voltage (LOV) condition. Relays are equipped with different methods to detect the LOV conditions and avoid confusing them with grid faults. However, this paper shows that existing LOV detection methods are prone to misoperation in the presence of inverter-based resources (IBRs). The paper's findings are corroborated by hardware-in-the-loop testing of relays with the state-of-the-art LOV detection methods. This paper also develops a new LOV detection method for transmission system relays that addresses the unveiled problem. The proposed method considers the fault behavior of IBRs and detects LOVs by examining certain conditions in three stages, namely phase-voltage-check, phase-current-check, and current-transients-check. Simulation studies are used to verify the dependable and secure operation of this new method for different LOVs, faults, IBRs, and VT configurations. The obtained results demonstrate that this method performs successfully regardless of the type of generation units. Moreover, it is sufficiently fast to prevent relay misoperation during LOV conditions and does not require extra hardware. [ABSTRACT FROM AUTHOR]

Phasor-based differential protection is widely used as the main protection function of the power transformer due to its reliability and ability to discriminate internal from external faults and inrush currents. However, these methods present some delays due to phasor convergence during the fault occurrence and can fail during challenging situations, such as transformer energizations with low second-harmonic content and turn-to-turn and turn-to-ground internal faults. This paper proposes a novel time-domain power transformer differential protection based on Clarke and wavelet transforms with only one differential unit and with automatic setting to be used in any power transformer. Considering both actual and simulation data, the performance validation reveals that the proposed method is efficient, ultra-fast, simple, and independent of the fundamental and harmonic components of the differential current. The method was also implemented in a real-time digital simulator to demonstrate its practical feasibility. [ABSTRACT FROM AUTHOR]

In this paper, novel neutral reactor structures are proposed to mitigate the secondary arc current (SAC) in non-conventional Multi-circuit Multi-voltage Transmission lines (MCMVTLs). The parameters of the reactors in the structure are optimized using the Non-dominated Sorting Genetic Algorithm II (NSGA-II). The optimization algorithm, coded in Python, regulates the multiple runs of an Electromagnetic Transients (EMT) simulation program to minimize the secondary arc current. The optimization trials are run in parallel on a 64 core computer to minimize the solution time. A detailed arc model was tested on the EMT program (PSCAD). Using this model and optimized parameters in the proposed neutral reactor schemes, the SAC is indeed extinguished in acceptable times. The SAC and TRV for neutral reactors with optimized parameters are up-to 68 and 77%, respectively, lower than the ones with parameters calculated by the conventional approach which ignores inter-circuit coupling. Meanwhile, the extinction times are up-to 46% faster. As a result, single-phase auto-reclosing in MCMVTLs is viable. [ABSTRACT FROM AUTHOR]

The inevitable voltage sag events cause losses to distributed generation (DG) and sensitive users. Reasonable planning for both of them helps to mitigate the impact of voltage sag. In this paper, a joint optimal planning method is proposed for DG and large sensitive user (LSU) considering the influence of voltage sag. Firstly, the new models of accelerated trip and chain trip for DG under voltage sag are established, to characterize the influence of DG tripping on other DG and sag characteristics during the sag event accurately. Secondly, a new voltage sag frequency assessment method is proposed, which considers models of accelerated trip and chain trip for DG, the tripping characteristics of distance protection (DP), to quantify the voltage sag severity accurately of DGs and LSUs in the gird which is with DP. Lastly, a joint optimal planning model is established considering the losses of DG and LSU under voltage sag, to support the planning of DG and LSU in different scenarios. The method is applied to IEEE RTS-30 for verification, proving that the method can give a direction of the most beneficial solution for the planner, to reduce the losses of voltage sag to both the power system and users. [ABSTRACT FROM AUTHOR]

This paper presents a new Magnetic Equivalent Circuit (MEC) to model the Variable Reluctance Resolver (VR-Resolver) and study the effect of different windings configurations on its performance. Therefore, VR-Resolver with non-overlapping (constant turn) and overlapping (variable turn) windings are modeled to investigate their effect on the accuracy of obtained results. The proposed method gives the possibility to model both healthy and faulty conditions by a unique model to analyze faults effects on the position error. For this purpose, the inter-turn fault is considered on the excitation winding, and both dynamic and static eccentric rotors (DE and SE) are studied. It is shown that the variable turn VR-Resolver has more accuracy and lower sensitivity to eccentricity fault, while the constant turn type is less sensitive to inter-turn fault. However, the latter may be preferred in some applications thanks to its simpler windings and lower manufacturing costs. Finally, the MEC results are proved by Finite Element Method (FEM) and experimental results. Generally, the model flexibility and shorter processing time can be considered as the proposed MEC advantages over FEM. [ABSTRACT FROM AUTHOR]

Winding faults are the most commonly occurring type of fault in offshore doubly-fed generator units. Such faults are difficult to detect and repair, and therefore higher fault identification accuracy is required. Most of the existing research analyzes stator and rotor winding faults separately, but due to the coupling characteristics between windings, it is necessary to analyze doubly-fed induction generator (DFIG) winding faults in a unified way. This paper proposes a general fault diagnosis method that can be applied to both the stator and rotor winding faults of DFIGs. First, a general mathematical model of a windings short circuit of a doubly-fed generator is established. Then, according to the mechanism of a turn-to-turn short circuit fault of a DFIG and the expression of a bilateral flux linkage between stator winding and rotor winding, a new fault feature-bilateral flux linkage difference vector (FLDV) is obtained by mathematical derivation. Finally, the recommended value for an experimental motor of feature quantity is set. The proposed method for inter-turn fault (ITF) diagnosis of stator and rotor windings provides technical support for the sustainable development of offshore wind power. A simulation and experiment prove that FLDV has high sensitivity and high reliability for windings ITF diagnosis. [ABSTRACT FROM AUTHOR]

Autotransformer (AT) traction network (ATN) expands widely with the rapid development of high-speed railway (HSR). The fault occurrence in ATN will affect the safety and reliability of power supply for electric multiple units (EMUs). However, due to the nonlinear relationship between measured impedance and distance, the accuracy and efficiency of the fault location for ATN is facing serious challenges, especially with the diverse fault types and operation modes. In this paper, the general circuit topology of subsections is given and the characteristics of voltage distribution are analyzed according to the impedance matrix of ATN. Through the decoupling method, a comprehensive equivalent model adopting composite impedance is established, which can illustrate a series of characteristics for all fault types. Furthermore, the fault-location method is proposed to express the mapping between the fault position and the relevant electrical quantities for the subsection, and then a reasonable compensation for the effect of mutual impedance between faulty and non-faulty subsections is provided to improve the accuracy. Consequently, the multi-terminals synchronous information is employed for unified fault-location for ATN. Case studies including simulation and field testing have verified that the method is accurate and quite robust to various fault scenarios. [ABSTRACT FROM AUTHOR]

Offshore wind farms (OWF) are being rapidly integrated to the power systems, which can be primarily attributed to saturation of the mainland onshore area, and high wind speed in offshore sites. However, to maintain stable grid operation, OWFs are required to comply with Low Voltage Ride Through (LVRT) capability. OWF during LVRT period should not only stay grid connected, but also support the grid during the disturbance. In this paper, a new communication-independent LVRT control scheme for HVDC connected OWF has been proposed. Under the proposed strategy, OWFs not only successfully ride through a fault induced voltage dip, but also comply with active power recovery ramp rate during the fault recovery period. Besides complying with LVRT requirement and ramp rate limit, the proposed strategy improves voltage dip induced frequency (VDIF) issue by increasing active power injection from the OWF during LVRT period. The proposed LVRT strategy also exploits the stored energy in HVDC link capacitors in order to reduce the impact of VDIF issue. The proposed and the conventional LVRT strategies for HVDC connected OWF have been implemented and evaluated on IEEE 39 bus benchmark system. [ABSTRACT FROM AUTHOR]

The medium voltage direct current (MVDC) is a promising direction of future shipboard power system (SPS). However, one of the main limitations encountered in its development is the fault isolation of DC side. This paper reveals the evolution process of short-circuit fault in typical MVDC SPS through equivalent circuit and transient simulation. Based on the analysis of protection needs, a superconducting current-limiting switch (SCLS) topology is proposed, which includes one superconducting coupled coil and two DC circuit breakers (DCCBs). The models of SCLS is built on MATLAB/Simulink and the current limiting principle and current sharing principle of SCLS are verified. The results show that the SCLS has effective current limiting performance and fault clearing effect. [ABSTRACT FROM AUTHOR]

DC fault is one of the most important and critical challenges for stable operation of DC microgrids. Resistive type superconducting fault current limiter (R-SFCL) is an ideal protective solution to limit DC fault current. However, the effect of only using SFCL may further deteriorate the DC bus voltage stability. This paper first analyzes the effect of R-SFCL on DC microgrid under different operation modes and different fault locations, and then presents a coordinated control method of SMES-battery hybrid energy storage system (HESS) and SFCL in ground fault. This method can not only reduce the fault current level but also regulate the DC bus voltage. Finally, the comparative study is conducted in PSCAD/EMTDC, the feasibility and superiority of the proposed method is verified. [ABSTRACT FROM AUTHOR]

This paper deals with the protection against earth faults in medium voltage meshed networks with unearthed neutral. A communication-supported protection system is proposed and assessed through numerical simulations. The protection system is based on the use of directional relays installed at both ends of each line of the network. Each relay communicates by sending permissive signals following the so-called directional comparison overreaching transfer trip scheme. Each directional relay implements a new transient fault detection algorithm based on the angle between the zero-sequence voltage and current phasors. The phasors are estimated at the dominant frequency of the network transient-response within the first milliseconds after the fault, which range can be evaluated by means of a simplified circuit equivalent representation. The performances of the protection system and the detection algorithm are evaluated for different network configurations. By using a specifically developed co-simulation tool that interfaces EMTP-RV with Matlab, the influence of the communication latency is also analyzed. A Monte Carlo method is applied to analyze the effects of fault resistance, incidence angle and fault location variations. Results of a real-time simulation obtained in the Opal-RT environment further support the applicability of the algorithm. [ABSTRACT FROM AUTHOR]

The excitation system with a multi-phase annular brushless exciter (MPABE) is widely used in large-capacity nuclear power plants. It is of great significance to realize a reliable protection of the exciter for safe operation. Since the MPABE is adopted with rotary armature structure, the rotor winding short-circuit (RWSC) fault is very difficult to be diagnosed directly. However, it is an effective way to realize fault diagnosis through the characteristics reflected in the stator field winding. In this paper, based on the mutual induction relationship between stator current and rotor current, detailed theoretical analysis of the RWSC fault is conducted and the harmonic characteristics of the stator field current are obtained. Then, related experiments and simulations are carried out, verifying the correctness of the theoretical analysis. Finally, a diagnosis method based on the transient harmonic characteristics of the stator field current is proposed and its sensitivity is also analyzed. The diagnosis method proposed in this paper is simple and feasible, which helps to improve the safety and reliability of the MPABE system in nuclear power plants. [ABSTRACT FROM AUTHOR]

Memristors are an attractive option for use in future memory architectures but are prone to high defect densities due to the nondeterministic nature of nanoscale fabrication. Several works discuss memristor fault models and testing. However, none of them considers the memristor as a multilevel cell (MLC). The ability of memristors to function as an MLC allows for extremely dense, low-power memories. Using a memristor as an MLC introduces fault mechanisms that cannot occur in typical two-level memory cells. In this paper, we develop fault models for memristor-based MLC crossbars. The typical approach to testing a memory subsystem entails testing one memory cell at a time. However, this testing strategy is time consuming and does not scale for dense, memristor memories. We propose an efficient testing technique that exploits sneak-paths inherent in crossbar memories to test several memory cells simultaneously. In this paper, we integrate solutions for detecting and locating faults in memristors. We develop a power aware built-in self-test solution to detect these faults. We also propose a hybrid diagnosis scheme that uses a combination of sneak-path and March testing to reduce diagnosis time. The proposed schemes enable and leverage sneak-paths during fault detection and diagnosis modes, while disabling sneak-paths during normal operation. The proposed hybrid scheme reduces fault detection and diagnosis time by 24.69% and 28%, respectively, compared to traditional March tests. [ABSTRACT FROM PUBLISHER]

Scan design is a de facto design-for-testability (DfT) technique that enhances access during manufacturing test process. However, it can also be used as a back door to leak secret information from a secure chip. In existing scan attacks, the secret key of a secure chip is retrieved by using both the functional mode and the test mode of the chip. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this paper, we perform a detailed analysis on the test-mode-only scan attack. We propose attacks on an advanced encryption standard (AES) design with a basic scan architecture as well as on an AES design with an advanced DfT infrastructure that comprises decompressors and compactors. The attack results show that indeed the secure chips are vulnerable to test-mode-only attacks. The secret key can be recovered within 1 s even in the presence of decompressors and compactors. We then propose new countermeasures to thwart these attacks. The proposed countermeasures incur minimal cost while providing high success rate. [ABSTRACT FROM PUBLISHER]

This paper introduces an enhanced equivalent model of the half-bridge symmetrical monopole modular multilevel converter (MMC) topology for the analyses of the electromagnetic transients. Compared with the existing MMC models, the proposed model reduces the simulation computational time without compromising accuracy, and contrary to the existing models, it provides accurate representation of the MMC behavior with respect to the dc-side fault. This paper also evaluates and verifies the accuracy of the proposed equivalent model under various operating conditions, that is, startup, dc-side pole-to-pole fault, and ac-side three-phase-to-ground fault. The study results indicate that: 1) in contrast to the existing equivalent models, the proposed enhanced model accurately represents the MMC under various operating conditions; 2) the implemented simplifications to the model do not adversely affect the accuracy of the simulation results; and 3) a reduced-level approximated model of the MMC is also adequately accurate for protection studies. [ABSTRACT FROM AUTHOR]

DC circuit protection applications provide a unique market opportunity for wide-bandgap (WBG) semiconductors, which are outside the conventional focus on power electronic converters. This paper presents an overview of emerging dc power systems, the needs for dc solid-state circuit breakers (SSCBs), and the benefits and advantages of various WBG SSCB concepts. Furthermore, a new class of self-powered SSCBs based on SiC or GaN normally-ON switching devices is proposed in this paper. One implementation of the SSCB concept based on a 1200 V SiC JFET experimentally demonstrated turn-off of a fault current of 125 A at a dc voltage of 400 V within $1~\mu $ s without requiring any external power supply. The SSCB detects short-circuit faults by sensing its drain–source voltage rise and draws power from the fault condition to turn off the SiC JFET. Various implementations of the SSCB concept for unipolar and bipolar capability using both SiC and GaN are also discussed from both device and circuit perspectives. It is concluded that very low ON-resistance normally-ON WBG switching devices are excellent candidates for the emerging SSCB applications. [ABSTRACT FROM AUTHOR]

A common practice is to install a service disconnect or a main disconnect for a feeder system in the same enclosure compartment as the downstream overcurrent protective devices. This can result in potential safety risks of shock and arc flash. This paper will address the advantages and disadvantages of isolating a service disconnect for electrical service for industrial and commercial installations from the perspective of prevention through design. This paper will compare shock and arc-flash hazard for both cases when the service disconnect or a main breaker is isolated and when it is in the same enclosure. [ABSTRACT FROM AUTHOR]

This paper proposes a diagnosis technique algorithm for a brushless dc motors under a stator inter-turn fault (ITF) condition using input impedance. The algorithm has early detection and various speed-range detection advantages. To early and accurately detect the ITF, the rotating speed, input current, voltage, resistance, and inductance must be analyzed. Therefore, we choose the input impedance as the detection factor because it includes all these factors. In this paper, the fault-detection system works without requiring a fast Fourier transform and the calculation of the negative-sequence impedance from the comparison of the measured impedance with the database impedance. The proposed technique was verified by the simulation and experiment. [ABSTRACT FROM AUTHOR]

This paper describes a procedure for calculating generator circuit breaker duty. Currently, commercially available software products help in determining the duty for a general-purpose circuit breaker. However, further calculations are needed to determine the duty for a special-purpose generator circuit breaker. IEEE Std C37.010-1999 provides the calculation procedure for general-purpose circuit breakers. In order to evaluate a special-purpose generator circuit breaker, this paper will expand the steps and methodology used in IEEE C37.010-1999 by presenting a procedure and detailed calculations for finding a duty multiplication factor based on the test $X/R$ ratio of generator circuit breakers given in IEEE C37.013-1997 (Standard for AC High-Voltage Generator Circuit Breakers Rated on a Symmetrical Current Basis). This way, engineers can still make a generator circuit breaker assessment although generator circuit breaker evaluation module is not included in many commercial short-circuit programs. [ABSTRACT FROM AUTHOR]

Traditional distance relays often mis-operate for high transient resistance in phase-ground faults by measuring apparent impedance. To solve this problem, a novel distance protection algorithm is proposed in this paper. It is deduced in the RL lumped transmission line model and calculates the fault distance from the measuring point to the fault point by solving a linear differential equation. In addition, a protection criteria based on the comparison result between the calculated fault distance and the protective setting margin rather than the protective zone measured by apparent impedance is set up in this paper. As a result, the proposed method can avoid overreach for the given characteristics that the calculated fault distance is greater than the actual fault distance when the fault occurs next to the opposite terminal. Meanwhile, both the fundamental component and one decaying DC component are needed to solve the differential equation for the proposed distance algorithm, therefore it can trip the breaker fast during the fault transient period. Finally, EMTP simulation results verify the validity of the proposed distance algorithm on RL transmission line model. However, to put the proposed method into field use, the problem caused by the distributed capacitance of the transmission line on the proposed method will be further studied and solved. [ABSTRACT FROM AUTHOR]

In a two-step defect diagnosis process, a fault detection test set is used for initial diagnosis to compute an initial set of candidate faults. When the initial set is large, diagnostic tests are generated based on the candidate faults in the set, and the set is refined based on the extended test set. This paper investigates the ability of functional broadside tests to serve as diagnostic tests for refining initial sets of candidate faults. The paper discusses the advantages of using functional broadside tests for this purpose. These advantages are related to the fact that the tests create functional operation conditions, and thus avoid nonfunctional effects that may make diagnosis less accurate. It also describes a multistep defect diagnosis process that uses functional broadside tests. Experimental results are presented to show the extent to which functional broadside tests can reduce initial sets of candidate faults. [ABSTRACT FROM PUBLISHER]

In addition to field-oriented control and direct torque control, the model predictive control (MPC) is another typical control method for permanent-magnet synchronous machine (PMSM) drives. In some critical applications, fault-tolerant controls are usually required. The faults of PMSM drives in this paper are limited as a single-phase open-circuit fault, which may be caused by open circuit or short circuit of one power switch. In the postfault operation, the neutral point of the PMSM is connected to a redundant leg. As is known, MPC is a model-based control method. Since the PMSM has different mathematical models in both normal and postfault operations, two different MPCs (MPC-I and MPC-II) should be, respectively, designed for both normal and postfault operations according to traditional thinking. However, it is first found in this paper that the faulty PMSM drive can be treated as an equivalent healthy PMSM drive, and MPC-I can be shared by both normal and postfault operations without any modification. The major contribution of this paper is to find this fact, and verify it with theoretical analysis and experimental validation. Obviously, this finding will simplify the whole control method of PMSM drives considering single-phase open-circuit fault. [ABSTRACT FROM AUTHOR]

This paper introduces a three-phase reversible transformer model for the study of low-frequency transients. The model topology is obtained from the direct application of the principle of duality by drawing basic circuit elements on top of the transformer frame. The model parameters are obtained from terminal and physical size measurements as well as the characteristics of the iron core. The implementation of the model is based on standard drag-and-drop circuit elements available in electric circuit simulation programs. The model is validated with inrush current and normal open circuit laboratory measurements. The main advantage of this model is that the parameters remain the same for the simulation of different operating conditions from all terminals. This is true for transients involving deep saturation, normal loading operation, or open circuit. [ABSTRACT FROM AUTHOR]

A defect diagnosis procedure is an important part of the yield improvement process. As defects become more complex, the output responses they produce differ to larger extents from the output responses of modeled faults, and they become more difficult to diagnose. Biases in the defect diagnosis procedure can also cause defects to be more difficult to diagnose. It is important to study and remove such biases in order to ensure that they do not affect the accuracy of the procedure. This paper undertakes a study of the biases of a defect diagnosis procedure and suggests a way to improve it. The study illustrates an approach by which biases in defect diagnosis procedures can be analyzed in general. [ABSTRACT FROM AUTHOR]

The development of new technologies in power generation and application, together with the demand for the reliability and capability of power supply has drawn increasing attention to dc distribution and microgrid technology. This paper introduces the renovation project for a single-circuit XLPE cable line being converted into dc operation after its second failure under 35 kV ac. This is the first time ever in China for this type of system conversion, in which the existing XLPE cable line was put into operation in a bipolar voltage-source converter (VSC) dc system of 10 kV voltage and 150 A current to maintain its 3 MW capacity. The test methods for cable performance that were checked under the designed dc scheme were put forward and conducted on sectioned cable samples. After the cable test and equipment installation, the line was put into operation under the VSC dc topology in 2011. It has now been running for four years without any interruption. Compared with other alternatives for ac operation, this proposal shows advantages in aspects of economy, reliability and engineering. Besides, the theoretical evaluation suggests that the system capacity can be further increased by four times, and the first step is underway for that goal. [ABSTRACT FROM PUBLISHER]