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Although the harmonics interaction plays a vital role in causing commutation failure (CF) in an ultra HVDC (UHVDC) system with hierarchical connection, it has not been sufficiently considered in previous work. In this paper, the electric interaction among the inverter valves of the UHVDC system with hierarchical connection during receiving system fault transient process is demonstrated. Moreover, the mechanism of CFs in UHVDC system with hierarchical connection is also investigated via the analysis of harmonics interaction. After the AC fault occurs, the appearance processes of the local commutation failure (LCF) and concurrent commutation failure (CCF) are divided into several stages and interpreted by schematic diagrams. And the characteristics of each stage are also concluded. In addition, a coordinated CF prevention scheme based on harmonics and DC current detection is proposed to mitigate the CFs in UHVDC system with hierarchical connection. Finally, the effectiveness of the proposed scheme is verified via a $\pm 1100$ kV UHVDC transmission system under various short circuit ratio values and AC-side coupling strengths. [ABSTRACT FROM AUTHOR]

This paper presents a new voltage support (VS) strategy for photovoltaic (PV) systems based on voltage sensitivity analysis to enhance the dynamic voltage stability (DVS) of islanded microgrids (MGs). Every network contains different characteristics. In particular, MGs have unique features compared to utility grids such as high resistance to reactance ratio (R/X). Consequently, injection of both active and reactive current is likely to improve the DVS of the islanded MG. Therefore, instead of engaging the entire capacity to reactive current injection which is performed in conventional voltage support strategy, both the active and reactive current is injected in the proposed strategy. On contrary, without considering the fact that each network contains distinctive characteristics, other strategies with both active and reactive current injection provide fixed active and reactive current which are uniform for all networks. To convey the network distinctive features on VS strategy, voltage sensitivity subject to active and reactive current injection is used in the proposed strategy. As a consequence, unlike other fixed active and reactive current strategies, the proposed strategy provides unique combination of active and reactive current for every network. The concept and derivation of the proposed strategy is clearly described. Network sensitivity analysis is carried out to determine the voltage sensitivity coefficients. The effectiveness of the proposed strategy is theoretically demonstrated and also compared with other strategies. Case studies are carried out on two different islanded MGs. The results show that the proposed voltage support strategy is capable of enhancing the DVS of islanded MGs by mitigating a possible instability, and by restoring the voltage faster than other strategies. [ABSTRACT FROM AUTHOR]

Line-commutated converters are extensively used as the interface between ac grids and classic HVDC systems. At the inverter side, commutation failure of switches is one of the most common faults that can pose threats to the system operation. Practical and reliable study of such phenomena relies on accurate and efficient converter models for simulations. Recently, a parametric average-value model (PAVM) has been presented for ac–dc rectifiers, which considers the internal faults of the converter. In this paper, the PAVM methodology is extended to the dc–ac inverter systems, including the commutation failure of switches. The proposed PAVM also augments an automatic fault detection technique to determine the faulty switches. Using comprehensive simulation studies, the developed model is verified to accurately predict the commutation failure of switches and reconstruct the waveforms consistent with the detailed switching models of inverters while being computationally more efficient. The proposed PAVM is envisioned to be an efficient and accurate asset for simulation of HVDC systems and inevitable when faults of switches need to be considered. [ABSTRACT FROM AUTHOR]

Miniaturization and low cost contribute to the development and popularization of wireless power transfer (WPT). Reducing the number of power conversion stages can reduce the volume and cost of the WPT converter, and even make it possible to improve the efficiency. A single-stage WPT converter with constant current (CC) and constant voltage (CV) output and its asymmetric modulation method are proposed in this paper. A direct AC-AC converter is applied to the primary side of the WPT converter to directly convert line-frequency AC to high-frequency AC. The applied direct AC-AC converter that can replace the commonly used multi-stage primary converter reduces the number of circuit devices, thereby reducing the volume and cost of primary converter. The proposed WPT converter can realize zero voltage switching (ZVS) and power factor correction (PFC). In order to achieve CC and CV output, a switchable hybrid compensation topology is applied to the proposed WPT converter. A 720-W experimental prototype was manufactured to verify the rationality of the proposed WPT converter and the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the control of inverter-based resources (IBRs) for optimal voltage unbalance attenuation (OVUA). This problem is formulated as an optimization program under a tailored dq-frame, which minimizes the negative-sequence voltage at the point of common coupling (PCC) subject to the current, active power, synchronization stability, and feasibility constraints. The program is inherently nonconvex and intractable. So, to guarantee the optimality, a rigorous optimality analysis is performed by leveraging analytical optimization. The analysis is divided into two cases: full mitigation of VU and partial attenuation of VU. For the former case, we directly solve the original program since the resultant VU is immediately deducible. For the latter one, directly solving the problem becomes very hard. Thus, we reformulate the program into an equivalent but more tractable form under certain conditions, by which the analytical optimum can be derived. It is found that the optimum trajectory has three stages (O1–O3), depending on two critical boundary conditions (C1 and C2). We implement the optimum with a photovoltaic (PV)-storage system by developing an OVUA controller. The proposed approach is demonstrated by dynamic simulations under different VU conditions and is compared with several existing practices. Finally, we discuss the extension of the proposed solution in a multi-IBR system. [ABSTRACT FROM AUTHOR]

This paper presents a hierarchical control system to mitigate the variability of solar photovoltaic (PV) power plant and provide ancillary services to the electric grid without the need for additional non-solar resources. With coordinated management of each inverter in the system, the control system commands the power plant to proactively curtail a small fraction of its instantaneous maximum power potential, which gives the plant enough headroom to ramp up production from the overall power plant, for a service such as regulation reserve. This control system is practical for continuously changing cloud cover conditions in partially cloudy days. A case study from a site in Hawaii with one-second resolution solar irradiance data is used to verify the efficacy of the proposed control system. The proposed control algorithm is subsequently compared with the alternative control technology from the literature, the grouping control algorithm; the results show that the proposed hierarchical control system is over 10 times more effective in reducing generator mileage to support power fluctuations from solar PV power plants. [ABSTRACT FROM AUTHOR]

In distribution networks with a high penetration of photovoltaic (PV), a coordination between reactive power compensation (RPC) of PV inverter and active power compensation (APC) of battery energy storage system (BESS) is always used in voltage regulation (VR). Since using a periodical VR inevitably increases communication utilization, how to design a new event-triggered one to reduce communication burden while achieving comprehensive voltage governance with the required minimum BESS sizing? Therefore, an event-triggered hybrid VR method is proposed in this paper. Firstly, an event-triggered communication is designed based on the changes in bus voltage and sensitivity, thereby defining all operating instants into transmission and ordinary sampling types. For the voltage violation issue at the transmission instants, a network-wide coordinated proportional RPC-APC is then designed, which keeps constant during one transmission interval. For the additional voltage fluctuation at the ordinary sampling instants in the interval, a local RPC-APC is additionally designed to yield a fast suppression without using any communication. In addition, the required minimum BESS sizing is obtained by calculating the total APC for VR requirement, which gives a reference in configuring BESS. Finally, the case study is conducted to demonstrate the effectiveness of this method. [ABSTRACT FROM AUTHOR]

When faults occur in the microgrids, high frequency transients will be superimposed on the system currents and voltages. The magnitude of those transients will attenuate as it encounters the discontinuity points in the network such as busbars, or any other impedance discontinuity points. This phenomenon can also be quantified by wavelet energy, which provides a useful tool to detect faults and locate the faulted feeder in the microgrid. In this paper, a novel protection scheme based on the transient wavelet energy of the superimposed current extracted by the Maximal Overlap Discrete Wavelet Transform (MODWT) algorithm is developed to detect faults and locate the faulted feeder in microgrids. Compared with existing protection schemes, the proposed protection scheme has the advantage of being largely immune to the changes in system fault level, fault types and positions, microgrid operating status and the control strategies deployed on the inverters, while presenting much lower requirement on the sampling frequency (10 kHz) compared with travelling wave-based methods. Unlike the conventional differential protection, the proposed scheme does not require synchronized measurement or high bandwidth communication channels, and thus, it can be considered as an economical and promising solution for microgrids. [ABSTRACT FROM AUTHOR]

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

The strength concept is an important tool for voltage stability evaluation of emerging hierarchical-infeed LCC-UHVDC (HIDC) systems. However, the complex inter-inverter interactions in such systems have caused significant difficulties for the strength assessment. This makes the accuracy of earlier strength assessment indices limited due to empirical analysis rather than rigorous theoretical reasoning. Thus in this paper, the hierarchical-infeed voltage interaction factor (HVIF) index is firstly utilized to quantitatively depict the complex inter-inverter interactions in HIDC systems. The use of the HVIF enables these interactions to be effectively incorporated into the subsequent strength assessment by proposing the hierarchical-infeed interactive effective short-circuit ratio (HIESCR) strength index. The critical HIESCR (CHIESCR) defined to delineate the voltage stability limit also evaluates to consistently 1.0 such that the distance between the HIESCR and CHIESCR is naturally an accurate stability margin. Since the HIESCR is developed based on the rigorous theoretical reasoning, it is more accurate than earlier indices for voltage stability evaluation. Moreover, the parametric dependence analysis of the HIESCR versus various system parameters and rated operation variables is conducted. This offers a comprehensive perspective for better understanding of the strength variation characteristics. Finally, case study in the modified IEEE 118-bus system validates the HIESCR. [ABSTRACT FROM AUTHOR]

Optimal protection coordination is usually solved for the original network topology with all lines, loads, and generation intact. However, power grids may experience contingencies due to transient events, e.g., generation or line outages. Low fault currents of inverter-interfaced distributed generators (IIDGs) necessitate a sensitive and reliable protection scheme. This paper proposes a protection scheme for islanded microgrids powered by droop-based IIDGs. The protection scheme utilizes virtual impedance-fault current limiters to limit IIDGs fault currents and achieve protection coordination. A two-stage method for optimal protection coordination (OPC) of directional overcurrent relays (DOCRs) is devised. In Stage I, relays short-circuit currents are calculated. Then, constraints on the operation times of primary and backup DOCRs are formulated for the islanded topology and each possible topology following an N-1 contingency. Lastly, in Stage II, the OPC problem is formulated as a constrained nonlinear programming problem and solved to obtain the optimal DOCRs settings. A radial test microgrid that is part of a Canadian urban distribution system is used to ensure the success of the proposed OPC method. [ABSTRACT FROM AUTHOR]

Behind-the-meter battery energy storage is used to mitigate non-dispatchability of customer-owned renewable sources. While serving their owners’ objectives, their underutilized capacities can be used to provide grid services to justify their cost. However, the integration of these resources extends the size and complexity of the network operation problem, imposing a processing burden on the central control system. In this paper, an agent-based distributed control framework is proposed that enables utilizing of the underutilized behind-the-meter capacities. In this framework, while the prosumer agents initially schedule their resources for daily cost management, a local customer aggregator agent performs day-ahead active and reactive power control on the underutilized behind-the-meter batteries to provide multiple grid services. A novel grouping algorithm is developed based on voltage sensitivity and a modified $k$ -means clustering method to assign customer groups to the local agents and establish the network subsystems. Mixed-integer linear programming is used to model and solve multiple optimization problems. The proposed framework is applied to the 123-bus distribution network. The simulation results show its effectiveness in terms of complexity and optimality, compared to the central control approach in allocating the unused behind-the-meter resources for two common industry needs: network bottleneck congestion relief and grid-edge voltage support. [ABSTRACT FROM AUTHOR]

In this paper, a new pilot protection scheme for AC line connected to LCC-HVDC inverter based on composite-mode model is proposed. First, taking commutation failure into consideration, 1-mode and 2-mode equivalent instantaneous models of inverter in different operating conditions are built. Second, according to the equivalent instantaneous inductances of inverter in different combinations of operating conditions, the equivalent models of inverter are summarized into 4 operation states. Then, the 1-mode and 2-mode equivalent models are combined to establish the composite-mode model of AC/DC hybrid system. And then, using multi-time section information, the instantaneous inductances of backside composite-mode model are calculated. Thus, protection criterion is constructed on the difference between composite-mode models of in-zone faults and that of out-of-zone faults for fault locating. Finally, RT-LAB simulation tests show that, the proposed method offers high sensitivity and reliability, unaffected by commutation failure. [ABSTRACT FROM AUTHOR]

The neutral grounding method is one of the crucial technologies used to ensure the safe and stable operation of distribution networks. With the development of power electronics-based devices, the application of highly controllable inverters to grounding systems has become a new research direction. In this review paper, based on the summary and analysis for the research status, the flexible grounding system is systematically classified according to its control strategy and structure. And then, the following core technologies are summarized: faulted line selection, current component detection, high-resistance ground identification, ground parameter measurement, neutral point voltage control, and fault location. Subsequently, deficiencies of flexible grounding systems are summarized from the following four perspectives: reliability, accuracy, speed, and stability. Finally, some discussions and recommendations for future development and research direction are presented. Especially, the reliability-enhanced hybrid grounding system that combines active inverters and low resistance for high-resistance ground faults is recommended. This paper provides a systematic literature review of the crucial technologies for flexible grounding systems and can be used as a technical reference for future research. [ABSTRACT FROM AUTHOR]

This paper proposes a new methodology for automated design of power electronic systems realized through the use of artificial intelligence. Existing approaches do not consider the system's reliability as a performance metric or are limited to reliability evaluation for a certain fixed set of design parameters. The method proposed in this paper establishes a functional relationship between design parameters and reliability metrics, and uses them as the basis for optimal design. The first step in this new framework is to create a nonparametric surrogate model of the power converter that can quickly map the variables characterizing the operating conditions (e.g., ambient temperature and irradiation) and design parameters (e.g., switching frequency and dc link voltage) into variables characterizing the thermal stress of a converter (e.g., mean temperature and temperature variation of its devices). This step can be carried out by training a dedicated artificial neural network (ANN) either on experimental or simulation data. The resulting network is named as $\text{ANN}_{1}$ and can be deployed as an accurate surrogate converter model. This model can then be used to quickly map the yearly mission profile into a thermal stress profile of any selected device for a large set of design parameter values. The resulting data is then used to train $\text{ANN}_{2}$ , which becomes an overall system representation that explicitly maps the design parameters into a yearly lifetime consumption. To verify the proposed methodology, $\text{ANN}_{2}$ is deployed in conjunction with the standard converter design tools on an exemplary grid-connected PV converter case study. This study showed how to find the optimal balance between the reliability and output filter size in the system with respect to several design constraints. This paper is also accompanied by a comprehensive dataset that was used for training the ANNs. [ABSTRACT FROM AUTHOR]

This paper proposes a modular on-road wireless power transfer system with interoperable power adjustment mechanism. The paper is anticipated to enhance the capability of on-road charging during the movement of automated guided vehicles (AGV), by which the traveling mileage is increased, while the battery volume is decreased. The system design includes an interoperable power adjustment technique based on the detected impedance, and the moving position of AGV can be, hence, comprehended so as to facilitate the adjustment of the output power from each transmission module in a more flexible way. Through the investigation of on-road charging efficiency, all of coil magnetic analysis, misalignment charging evaluation, system stress simulation, and resonant characteristics investigation are performed. Experimental results gained from software simulation and hardware realization are beneficial for AGV charging applications. [ABSTRACT FROM AUTHOR]

This paper presents a compact model of latchup considering design and process dependence. The new approach is more realistic and inspirited from the classical model. This model was used to confirm the single-event latchup (SEL) robustness of D-flip-flops (DFFs) used in Readout Circuit of Infrared-sensors developed by Sofradir. SEL cross sections are presented by the mean of the Monte Carlo tool MUSCA SEP3 in order to validate the new latchup modeling approach. [ABSTRACT FROM AUTHOR]

In this paper, we propose a loss calculation method considering minor hysteresis loops for permanent magnet (PM) motors driven by pulsewidth modulated (PWM) inverters. In the governing equation of the proposed method, both the effects of the major and minor hysteresis phenomena are expressed by a reaction magnetic field. This field is determined by iterative calculations of finite-element analysis (FEA) with a simple hysteresis modeling that considers the minor loops. The proposed method is applied to a PM motor, and the experimental verification is carried out. It is clarified that the minor hysteresis loops affect not only the hysteresis loss but also the eddy current loss because the skin depth varies with the differential permeability of the minor loops. [ABSTRACT FROM AUTHOR]

This paper proposes a general method for the design of multiple node upset (MNU)-tolerant latches. First, two double node upset (DNU)-tolerant latches and one triple node upset (TNU)-tolerant latch are introduced. These proposed latches are highly resilient to DNUs and TNUs in terms of their output nodes. Then, a generalized MNU-tolerant latch structure is introduced based on the construction features of these latches. Massive Hspice simulations using silicon-on-insulator (SOI) technology indicate that none of the proposed latches would output an unrecoverable error. Finally, we compare our latches to the designs in other reports. The DNU-tolerant latch, DNUTL-1, demonstrates considerable advantages in terms of the area, propagation delay, power, and the delay-power-area product. Moreover, the DNUTL-1 master–slave flip-flop has good performance in setup time, hold time, and latching window. [ABSTRACT FROM AUTHOR]

The nine papers in this special section focus on photovoltaic module and sub-module level power electronics. Grid connected photovoltaic energy systems have experienced an explosive growth over the last decade, with a cumulative installed capacity surpassing the 400 GW milestone as of 2017. Among PV system configurations, distributed module-level converter architectures can lead to a higher energy yield by mitigating partial shading, persistent shading (soiling, snow, bird droppings, and fallen leaves), mismatch, and aging, through a higher maximum power point tracking (MPPT) efficiency. Also, distributed electronics might be the key for implementing diagnostic and prognostic actions at a module level. Among these configurations, microinverters (also known as ac-module inverter), which connect a single PV module to the grid, and PV power optimizers, which are dc–dc converters performing the MPPT function at a module level, have attracted the academic and industrial interest in the last decade. So much so, that both microinverters and dc–dc power optimizers are commercialized by tens of companies around the world, with a great variety of circuit topologies, which comprise combinations of one or more power stages, interleaved converters, resonant converters, topologies with and without isolation, etc. [ABSTRACT FROM AUTHOR]

The instability of the switching frequency in an inverter with hysteresis current results in a high failure rate of the power switching components of the inverter. To address this hurdle, a low-cost fault-tolerant control strategy is proposed in this paper to effectively correct the faults. [ABSTRACT FROM AUTHOR]

In order to improve the driving range and reduce the cost of battery electric vehicles through a higher efficiency, this paper proposes to adopt multilevel converters using low-voltage Si mosfets in the electric powertrains. A multilevel Si mosfet inverter, a conventional insulated-gate bipolar transistor (IGBT) inverter, and a SiC mosfet inverter are modeled and compared using a reference vehicle over various driving cycles. The costs of the three solutions are also compared. It is shown that the multilevel Si mosfet inverter has a rather high efficiency and realizes the lowest cost among the three solutions even when the worst case of cost is considered. Sensitivity analysis also shows that the multilevel Si mosfet inverter is suitable for a wide range of vehicle concepts in addition to the reference vehicle. Moreover, the multilevel topology also features lower electromagnetic interference and provides modularity. Therefore, Si mosfet-based multilevel inverters are proved in this paper to be an appropriate option to improve the efficiency and reduce the cost of electric powertrains. [ABSTRACT FROM AUTHOR]

Frequency-dependent coupling (FDC) emerges as a new method to introduce the finite-position transmission zeros (TZs) in the synthesis and design of filtering networks. In this paper, several fundamental building blocks with FDCs are introduced and studied. The higher order filters with many TZs can be constructed by cascading these fundamental building blocks. As compared with the conventional coupled-resonator filters with only constant couplings, the inclusion of FDCs can potentially create more TZs with the same coupling topology. It is also shown that to realize the same TZs, a filter can be realized in a simplified structure with less cross-couplings by using FDCs. In this paper, one complete filter design procedure is illustrated, including the steps of the circuit model synthesis by the method introduced in this paper, physical dimensioning of the filter by the electromagnetic simulation and measurement of the fabricated filter. The measurement results are in very good agreement with the theoretical predictions, which validates the modular design strategy for filters with FDCs. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

The planned China fusion engineering test reactor (CFETR) needs one or more negative-ion-based neutral beam injectors (N-NBIs) with a beam energy of 500 or even 1000 keV. In order to prepare for CFETR, a prototype of CFETR N-NBI is being designed. The prototype needs an acceleration grid power supply (AGPS) rated at 200 kV/25 A with a maximum pulselength reaches to 3600 s. The AGPS adopted a single-stage inverter-type high-voltage power supply (HVPS). The output voltage ripple is an important specification of the AGPS, which can affect the efficiency and stability of N-NBI system by influencing the beam divergence. However, the conventional methods cannot be used to limit the output voltage ripple of the inverter-type HVPS used as AGPS of CFETR N-NBI prototype. This paper simplified the AGPS to an insulated three-phase three-level (TPTL) dc–dc converter connected with a dual dc link. The working process of the TPTL dc–dc converter with duty-cycle modulation has been analyzed, and two main continuous conduction modes are described. The influence of key parameters such as duty cycle of inverter, leakage inductance of transformer, and output current on output voltage ripple is analyzed. Based on the analysis results, a so-called combined control strategy was proposed to keep the output voltage ripple at a level. The proposed strategy is suitable for the cases where the object output voltage is below 175 kV. Some simulations were carried out by using MATLAB/Simulink. The results showed that the analysis in this paper is reliable and the proposed control strategy has a good performance. [ABSTRACT FROM AUTHOR]

Industrial induction heating (IH) is a key manufacturing process due to its benefits in terms of efficiency, accurate output power control, and high performance. These features have made possible the extension of this technology to a wide range of industries from automotive to aeronautic, domestic, or renewable energies. One of the main challenges still present is the design of a high-performance and cost-effective process for those induction targets with complex geometries exposed to the magnetic field, being the most representative example gears present in most mechanical systems. Usually, in order to optimize the heating process, multifrequency IH systems are used, being often expensive and/or difficult to tune and control. The aim of this paper is, consequently, to propose a family of power converters able to supply the inductor system with two simultaneous frequencies in order to improve the heating process of the induction target. The proposed converter takes advantage of a multiresonant network allowing full control of the output power delivered at each frequency and, at the same time, a compact and cost-effective implementation. The proposed converter is analyzed, designed, and implemented, and experimental verification of its operation is provided in this paper. [ABSTRACT FROM AUTHOR]

Due to the uncertainty of feeder impedance, conventional droop control-based power sharing scheme presents poor reactive power sharing accuracy in microgrid. As microgrid configuration becomes more and more complicated, reactive power sharing between various distributed generation (DG) equipment is very challenging. To achieve proper power sharing with a simple control method in microgrid, a new structure and power sharing method is proposed in this paper. Instead of using complicated reactive power sharing scheme, this paper proposes separated energy server (ES) units to provide reactive power. Then, active power supplying and reactive power supplying can be achieved separately by energy routers (ERs) and ESs, respectively. With the introduction of ES, the power sharing between DG units can be easily achieved without any supplementary communications or control algorithms. In addition, to reduce costs,a hybrid reactive power compensation configuration with capacitor banks and ESs is provided. Operation principle and power control strategy for DG units and ESs are explained and analyzed in this paper. In order to properly select the coefficients of the power controllers, sensitivity and stability of the system are investigated. Simulation and experimental results are presented to prove the validity of the proposed power sharing method, showing that ERs can effectively share the active power and ESs can effectively share the reactive power according to their capacity. [ABSTRACT FROM AUTHOR]

In this paper, flexible compensation of negative and zero sequences current in three-phase distribution power system by using single-phase distributed generations (DGs) smart inverters is proposed. In the proposed control strategy, power factors of the DGs are controlled without modifying the active powers production. The instantaneous power analysis from single-phase perspective is developed and used to achieve the objective function for negative and zero sequences current compensation. In the proposed strategy, voltage regulation of three phases and available reactive powers of the single-phase DGs are considered as constraints of compensation problem. The developed objective function subjected to the constraints is minimized on-line by using Karush–Kuhn–Tucker optimization method. After determining the required reactive power in each phase, this power demand is shared among DGs in that phase based on their available power ratings. In this paper, comprehensive studies on the effects of voltages regulation and DGs available reactive power ratings on the proposed control strategy are conducted. An IEEE 13-node test system with seven integrated single-phase DGs has been adopted for case studies. [ABSTRACT FROM AUTHOR]

This paper deals with the sliding mode estimation for microgrid with time delays. Delay has a great impact on large power grids’ management for microgrid, which terribly reduces the stability and quality of microgrid. Random delay caused by load dependent congestion, constant transmission delay and constant delay in microgrid are considered in this paper. To eliminate the adverse effects of delays, a novel sliding mode estimation-based controller is designed to predict time delays and microgrid states, and to reject the disturbance of estimation errors. The mathematical inverter model containing electrical characteristics is regarded as the model of practical microgrid system. Delay estimation with learning parameter and state estimation are derived according to the inverter model. By regarding estimation errors as disturbance of sliding mode control (SMC), the control signal of SMC is adaptively changed in the sliding mode estimation-based control loop to ensure the stability of system and accuracy of estimation. Exponential reaching law (ERL) is implemented to improve the chattering issues and reaching performance of SMC. Lyapunov approach is exploited to analyze the stability of sliding motion. Finally, the proposed SMC strategy is validated by simulation experiments of a microgrid with time delays. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency single-phase T-type boundary conduction mode (BCM) microinverter. The conventional full-bridge BCM microinverter has achieved zero voltage switching (ZVS) and thereby improved the efficiency, but it suffers from high switching losses under light load conditions. The proposed T-type BCM microinverter reserves ZVS and uses a multilevel technique to further decrease the switching losses. The BCM operation with multilevel technique will have too low switching frequency when the grid voltage approaches half of the dc link voltage. To solve this problem, this paper adopts a third operation mode for the T-type switching leg to maintain the switching frequency above a minimum value. The corresponding mode transitions are also detailed to ensure a smooth operation. Because of the turn-offdelay of the freewheeling transistor, the actual lower current boundary deviates from the programmed one, which will distort output current. To address this issue, this paper also proposes a boundary compensation method. A prototype has been built for performance verification, which can test both full-bridge and T-type topology. Compared with the full-bridge BCM microinverter, the proposed T-type BCM microinverter has a higher efficiency over the whole load range. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital multiplying delay-locked loop (MDLL) with a leakage-based oscillator for ultra-low-power sensor platforms. The proposed digital control of channel leakage current achieved ultra-low-power consumption in frequency generation with a fine resolution. The leakage based oscillator was modeled as an RC-based oscillator, analyzed, and the analyses were verified by simulation. The proposed oscillator was applied to the MDLL with a fast frequency relocking scheme which adaptively performs an optimal lock process according to the amount of frequency drift during the sleep state. The MDLL was implemented in 65 nm CMOS and consumed 423 nW for 3.2 MHz generation, and had an energy efficiency FoM of 0.132 \muW/MHz. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

In this paper, several fundamental pseudo-CMOS digital circuits with n-type indium tin oxide-stabilized ZnO thin-film transistors (TFTs) were implemented and investigated. The optical transmittance of circuits varied from 77% to 92% throughout the visible wavelength band. Electrically, the operation frequency of inverters, nor gates, nand gates, D latches, and D flip flops were all found to exceed 10 kHz with a supply voltage of 10 V. Besides, 13-stage ring oscillators could be operated at 42 kHz with a propagation delay time of $0.92~\mu \text{s}$ when the supply voltage was set as 20 V. Among the state-of-the-art transparent designs, these proposed circuits based on the ITO-stabilized ZnO TFTs exhibited high-speed performance, which were promising as building blocks for transparent electronics with moderate frequency requirements. [ABSTRACT FROM AUTHOR]

This paper presents a novel configuration for a high-Q tunable waveguide (WG) filter with a constant absolute bandwidth (BW). The key feature of this filter is that it is tuned by a single tuning element. This paper investigates the theory of coupling behavior of single septum and double septa to achieve constant absolute BW. The theory is presented for both the coupling matrix-based and inverter-based filter topologies. The filter design methodology is lucidly presented covering the design strategy adopted for interresonator coupling, input–output coupling and tuning element. The tuning mechanism of the proposed filter is explained with measurement results presented for a $Ku$ -band tunable WG filter designed at 15 GHz with a 2% BW to achieve 15% tuning range. The filter promises to be useful in emerging 5G millimeter-wave applications, where the filter size is very small to accommodate many mechanical tuning elements. Furthermore, the proposed design methodology is scalable, i.e., the tuning mechanism is independent of the filter order. [ABSTRACT FROM AUTHOR]

Soft-switching techniques of transformerless photovoltaic grid-connected inverters (TLIs) can significantly reduce switching losses, as well as soften switching processes. Conventional dc–ac soft-switching configurations proposed by Dr. Deepakraj M. Divan are invalid in TLIs because of the leakage current problem. In order to develop soft-switching techniques in TLIs, this paper proposes a new soft-switching configuration and a procedure to guide the invention of soft-switching TLIs. First, this paper proposes two basic resonance tanks related to dc bus polarities, and then, uses these basic tanks to elevate four popular full-bridge-type TLIs according to the proposed guideline. As a result, four soft-switching TLIs are gained. Second, this paper picks obtained soft-switching highly efficient and reliable inverter concept (HERIC) as example to analyze its soft-switching operation principle and performance. As a consequence, all active switches of the gained soft-switching HERIC circuit are switched under both of zero-current turn-on and turn-off conditions; the reverse recovery problem of freewheeling diodes is alleviated owing to the zero-current turn-off of diodes; meanwhile, the common-mode voltage at the switching frequency scale is still constant. Finally, some experimental results from a 3-kW universal prototype at 50-kHz switching frequency are provided to verify the effectiveness of the main contributions of this paper. [ABSTRACT FROM AUTHOR]

The active power distribution network operation with the integration of various renewable distributed generations (DGs), storage units, and dynamic loads are attracting a lot of interest due to substantial benefits in maximizing the penetration of available renewable energy resources (RES). However, the risk of voltage violation in the active distribution system (ADS) is exacerbated due to increasing penetration of DGs. It has become a bottleneck to maximize the DG penetration into the system. This bottleneck can be handled by effective voltage regulation and reactive power support into ADS. Nowadays, power electronic devices are frequently used for voltage and reactive power support over the conventional approaches. In this paper, an approach to maximize the penetration of RES, such as solar, wind, etc., into ADS by maximum utilization of existing solar photovoltaic inverters (SPVI) in the system is presented. Optimal utilization of SPVI may enhance the voltage stability of the ADS and wind power penetration into the system. The proposed SPVI control approaches are depended on active power generation of solar photovoltaic (SPVG), rating and capability of SPVI, and required reactive power in the ADS. In this paper, the problem of maximum penetration of RES is formulated as an optimal power flow embedded nonlinear optimization problem subject to the physical limitations of the SPVI. The results of the analysis performed on an IEEE 33 bus system show that the proposed SPVI control strategies can improve the voltage profile of the ADS with minimization of curtailment of wind power generation. [ABSTRACT FROM AUTHOR]

This paper presents theoretical and experimental discussions on low-voltage-ride-through operation of a modular multilevel single-delta bridge-cell (SDBC) inverter intended for utility-scale photovoltaic (PV) systems. Modern grid codes require grid-tied inverters to provide dynamic grid support during grid-fault events by injecting reactive current. This paper discusses decoupled positive- and negative-sequence reactive-current control, focusing on asymmetric voltage sags with imbalanced magnitude and phase relationships. The main objective is to present a feedforward control method based on calculation of the zero-sequence current required for achieving power balance during normal and grid-fault conditions. Moreover, this paper demonstrates a practical method that minimizes overcurrent stress in the three inverter clusters by adjusting active power drawn from PV arrays. Experimental results on a three-phase 12.6-kVA system prove that the SDBC inverter is capable of seamlessly operating through asymmetric voltage sags. [ABSTRACT FROM AUTHOR]

Time-based circuit design is becoming increasingly popular due to its ability to overcome the challenges imposed by technology scaling such as supply voltage reduction and finite output impedance. In this paper, we present synchronous circuit techniques for the design of discrete-time time-mode filters based on the operational simulation of LC ladders or a cascade of bilinear/biquads. Operating with a 130-kHz clock frequency, two low-pass filter prototypes have been constructed in a 1.2-V, 130-nm IBM CMOS process. The measurements confirm the validity of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper proposes a novel comprehensive model of a rectifier-controlled induction motor drive for use in positive-sequence transient stability simulation (PSTSS) programs. The model is implemented to approximately capture the behavior of the point-on-wave drive model, and applied to investigate the dynamic performance of the advanced drive loads in system-level simulations. This positive-sequence drive model is systematically developed by reducing the detailed three-phase electrical and control representations into $dq$ axes positive-sequence formulations. For the positive-sequence model, the line-side rectifier is interfaced to the grid through a voltage source with separate $dq$ axes controls to regulate the active and reactive power of the drive. The machine-side inverter control system is represented based on rotor flux oriented control. The dc-link of the drive converter is implemented by employing the average model of the pulse width modulated converter, and is utilized to integrate the line-side rectifier and machine-side inverter. The proposed motor drive model is validated by comparing the performance with the electromagnetic transient point-on-wave drive model. The VAr support capability of the drive load model is investigated by incorporating the developed model into a composite load structure in PSTSS programs. Multiple units of the developed drive models are represented in large-scale transmission systems to examine the system-level responses of drive loads. [ABSTRACT FROM AUTHOR]

This paper focuses on power distribution systems with inverter-interfaced renewable energy sources (RESs), and develops a distributed control framework to steer the RES output powers to solutions of ac optimal power flow (OPF) problems. The design of the distributed control algorithm is based on suitable linear approximation of the ac power-flow equations, and leverages the so-called alternating direction method of multipliers (ADMM). Convergence of the RES-inverter output powers to solutions of the approximate ac OPF problem is established under suitable conditions on the mismatches between the commanded setpoints and actual RES output powers. Overall, since the proposed scheme can be cast as an ADMM with inexact primal and dual updates, the convergence results can be applied to more general distributed optimization settings. [ABSTRACT FROM AUTHOR]

In this paper, the conventional I- and T-type three-level neutral-point-clamped (3L-NPC) inverter for low-voltage renewable energy systems is first investigated. Literature research shows that the T-type inverter improves I-type's insulated-gate bipolar transistor (IGBT) $+$ IGBT current paths. However, the IGBT $+$ diode paths are the same. The calculation in this paper further reveals that the IGBT $+$ diode current paths dominate the conduction losses and even the whole semiconductor losses. Based on the aforementioned recognitions, a novel T-type inverter is presented as an alternative to be applied in the low-voltage renewable energy systems. In the proposed 3L-NPC, four CoolMosfets replace the IGBT $+$ diode middle bidirectional switch. In the proposed topology, there is no diode involved in the current path supposing the unity power factor. In this way, the conduction loss is expected to be reduced compared with that from the conventional T-type 3L-NPC, particularly in the low and medium power ranges. [ABSTRACT FROM PUBLISHER]

Embedded SRAMs are continuing to be one of the most critical components that limit the performance and energy budget of today's systems. To enable better system level optimization, this paper introduces an embedded energy monitoring circuit that measures the absolute energy consumption of a 128 kbit SRAM circuit that is fabricated using a 65 nm low-power CMOS process. Monitoring circuit results are measured to be accurate within 10% of the actual energy consumption and it works with minimal overhead (below 1% active power). Secondly, to achieve energy-efficient and high-performance SRAM operation, various circuit techniques are employed. 8T bit-cells with word-line voltage boosting is used to enable operation for a wide supply range from 370 mV to 1.2 V. Since variation effects are more prominent at low-voltages, SRAM performance is improved by using a two stage sensing scheme. Global sensing is performed by offset compensated sense amplifiers that leverage body biasing to achieve up to 2× offset reduction for only 3.5% area overhead compared to SRAM area. [ABSTRACT FROM AUTHOR]

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a hierarchical control architecture for the regulation of frequency and nodal voltages of a microgrid in islanded operation. Considering systems with both dispatchable and nondispatchable generation, as well as noncontrollable loads, the suggested approach allows to coordinate the MG devices in order to maintain the network variables inside the desired operational ranges. Moreover, the proposed algorithm, based on model predictive control, introduces the possibility to define different resource management strategies while taking into account the constraints of the available devices. Simulation examples are reported and described in the final part of this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a reactive power flow control pursuing the active integration of photovoltaic systems in LV distribution networks. An alternative power flow analysis is performed according to the specific characteristics of LV networks, such as high resistance/reactance ratio and radial topologies. The proposed solution gives high performances, in terms of rms-voltage regulation, by estimating the reactive power reference on each node considering the influence of the rest of the nodes in terms of active and reactive power demanded/generated by them. The local control of each photovoltaic system is based on the power converter control, interfacing these units with the grid and the loads respectively. The local control is designed on the basis of locally measured feedback variables. Photovoltaic units thus guarantee universal operation, being able to change between islanding-mode and grid-connected mode without disrupting critical loads connected to them, and allowing smooth transitions. Exhaustive results are also included and discussed in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents hybrid design of a Ternary Inverter (TI) circuit by integrating an Ovonic-Threshold-Switching (OTS) based Phase-Change-Memory (PCM) cell between Complementary-Metal-Oxide-Semiconductor (CMOS) transistors. Volatile OTS behaviour of the PCM structure helps to generate the ternary state. Reliability of the proposed TI design has been demonstrated through the Monte-Carlo simulations in Cadence-Spectre simulator incorporating both Process and Mismatch variability at all corners. The proposed inverter cell consumes 10.44 $\mu$ W power and 1.47 ns delay on UMC-180 nm technology node. Moreover to demonstrate the scaling potential, we have simulated the proposed inverter at various technology nodes i.e 180/90/65/28 nm. At advanced feature sizes, power and delay are improved by significant amount. For benchmarking, we have compared the proposed TI design with various state-of-the-art hybrid structures. Furthermore, to demonstrate potential applications, we designed and simulated ternary universal logic gates i.e NAND/NOR. Benefits of the proposed TI in circuit applications are shown through a Ternary Multiplier (TMUL) arithmetic circuit implementation. Finally, a Ternary-Static-Random-Access-Memory (TSRAM) is proposed with two back-to-back connected CMOS-PCM TIs with three bit storing capability. [ABSTRACT FROM AUTHOR]