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We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized "permanently on" series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. [ABSTRACT FROM AUTHOR]

We propose a new IDDQ testing signature, the graphical IDDQ signature. We discovered that noise, in the entire set of current measurements for a chip, is a vastly superior feature for classifying chips as good or bad, compared to present methods. The measured IDDQ current as a function of vectors is defined here as the signature. We examine the shape of the waveform defined by the total set of the IDDQ measurements, to extract the number of bands that all of the current measurements cluster into, the width and separation of the bands and current glitches or noise among all IDDQ measurements. We examined the IDDQ signatures of all SEMATECH experiment chips that were classified as good or bad by a combination of functional, delay, and scan voltage tests. A single IDDQ threshold, whether absolute or differential, cannot separate good/bad chips reliably. Good chip signatures contain discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. The graphical IDDQ classifier shows very high accuracy for SEMATECH test data with a test escape rate of 5.97%, compared with 7.5% for the single threshold method, 7.6% for current differences and 7.5% for the ΔIDDQ method. The graphical IDDQ method had a 1.2% test overkill, compared with 2.3% for the single threshold method, 6.1% for current differences and 7.0% for ΔIDDQ. [ABSTRACT FROM AUTHOR]