Search

This paper presents a novel structure and design of a full custom digital chip that generates the three-phase sinusoidal pulse width modulation (SPWM) waveform with variable voltage and variable frequency (VVVF) control. The voltage and frequency are simultaneously controlled with constant v/f ratio. The frequency range is from 5Hz up to 75Hz and the voltage also changes proportionally. In this way, three modes including fix, manual setting and closed loop control have been defined that provide simple implementation and high flexibility for the IC. The synchronous modulation is used (p=63) in which there are 63 pulses for every complete sinusoidal cycle. Considering the dead time between the complementary signals that reach the switches on an inverter’s leg, the result of the simulation shows the elimination of low order harmonics with value of 40 dB for each of the SPWM outputs. The method used for generating sinusoidal waveform and variable frequency generator circuit and also the approach taken for controlling amplitude and frequency simultaneously are completely novel. The chip has been designed using 0.35µm CMOS standard technology with approximately 15000 transistors on chip. The complete circuit consumes 680µm × 570µm of chip area and 48mW of power dissipation.

A continuous‐time offset cancelation and gain calibration strategy is proposed for open‐loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide‐bits digital processor for offset and gain‐error correction. Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input‐referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Post‐layout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14‐bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB. [ABSTRACT FROM AUTHOR]

The conversion error of a pipelined A/D converter using inaccurate comparators is analyzed. Error bounds are established, and it is shown that the error can be compensated using simple analog circuitry combined with some digital logic. The resulting system is especially useful for fast converters in which accurate comparators would require a large chip area and large de power. Simulations are presented to verify the efficiency of the proposed error correction scheme., An analysis of the conversion errors caused by defective comparators in a pipeline analog-to-digital converter is presented. Error bounds are derived and, together with a knowledge of the pipeline converter's inherent features, used to develop error correcting algorithms that minimized hardware requirements while reducing the complexity of digital error compensation in such comparators. Computer simulation results are given to showthe efficacy of the proposed scheme.

Summary: A 12‐Gb/s 0.18‐μm complementary metal oxide semiconductor (CMOS) serial link transceiver with embedded clock signal in data stream using dual‐mode pulse amplitude modulation is presented. The 6‐bit data and the clock signal are both transferred through the same transmission channel. In the proposed modulation technique, the clock signal is easily recovered using a conventional phase‐locked loop without any complex encoders in the transmitter circuit. The transmitter includes multiplexers, an output driver, and pre‐emphasis circuitry with 127‐mW power consumption. The receiver is composed of a phase‐locked loop for clock recovery and demodulator blocks for data recovery, and it dissipates 45 mW of power. [ABSTRACT FROM AUTHOR]

In this paper, the design and simulation results of a general-purpose fuzzy logic controller (FLC) with mixed-signal (analog and digital) inputs and digital outputs are presented. Based on a new strategy, it provides simplicity and high speed from the analog prospective and a total digital system advantages with unchanged digital system properties. A novel and reliable structure with respect to other topologies for the fuzzifier section is designed which enhances the accuracy and the velocity. In order to detect minimum and maximum of the input currents at the same time, an inference engine consisting of a min & max circuit is an addition. The benchmark for the defuzzifier in the proposed design is simplicity and through a simple approach, the center of area (COA) is attributed to the defuzzifier. The proposed controller circuit consists of two inputs, sixteen rules and one output designed in 0.35μm CMOS standard technology and simulated with MATLAB systematically. The total controller circuit is simulated with HSPICE simulator (BSIM3v3 parameters) and the layouts were extracted with Cadence Virtuoso v 5.1. The inference speed of the controller is about 41.3 MFLIPS (fuzzy logic inference per second) and power consumption is 3.2 mW. [ABSTRACT FROM AUTHOR]

This brief presents a new method to estimate the interstage gain error and sub-DAC nonlinearity in pipelined ADCs, regardless of the number of bits per stage. The method is based on the effect of error on the ADC output histogram and estimates errors in the background. It means that no special input signal is required and no interruption occurs during the estimation process. The method imposes no limitation on input bandwidth nor on its distribution. The proposed method is robust against noise and memory error of comparators. The estimation process is very fast and its implementation is simple compared to other techniques. [ABSTRACT FROM AUTHOR]

This study presents a spread spectrum clock generator (SSCG) circuit for high‐speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage‐controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum‐spreading profile. The control unit consists of an analogue charge pump‐based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high‐speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non‐spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works. [ABSTRACT FROM AUTHOR]

In this article, a new current-mode, accurate, and fully programmable Interval Type-2 (IT2) membership function generator (MFG) in 0.18 m CMOS technology is presented. This IT2 fuzzifier is based on a Type-1(T1) fuzzifier that uses a new method for slope tuning. The proposed slope tuning method, leads to smaller active area and also significantly smaller total die area by reducing the number of required pins in comparison with previous methods. Small area, low power consumption, and especially suitable programming method, makes the proposed IT2 MFG suitable for fuzzifier block of general-purpose Fuzzy Logic Controllers (FLCs). The proposed IT2 MFG has an average power consumption of 570Wand has an area of 0.0183mm2. Simulation results using HSPICE in a typical 0.18 m CMOS technology are presented to analyze the behavior of designed circuits. [ABSTRACT FROM AUTHOR]

A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6-4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process. [ABSTRACT FROM AUTHOR]

In this paper a new solution for a highly linear, high speed open loop (OL) residue amplifier for applications in high‐speed pipelined analogue‐digital converters is proposed. The proposed amplifier has a voltage gain of 4 (V/V) with <0.2% non‐linearity error and 1.2 Vp‐p output swing. The amplifier is compensated for process variations by using a novel gain control mechanism, thus maintains the linearity in all process conditions and also in the presence of a mismatch. The proposed amplifier is designed in 0.35 μm complementary metal‐oxide semiconductor process, and the settling time is approximately 2 ns when driving two 1 pF single ended capacitive loads. It consumes 38 mW power from a 2.8 V supply and occupies 0.073 mm2 of die area. Simulations are performed in HSPICE using level 49 models. [ABSTRACT FROM AUTHOR]

Analog implementation of fuzzy logic controllers (FLCs) is the most efficient method when speed, power, and area are critical. Inference engine (IE) usually takes a large part of total die area when the FLC has a large number of rules. In this paper, a method is proposed to reduce size of the IE in analog implementations of FLCs. Since only a small number of rules may be fired simultaneously, thus a few inference blocks (IBs) may work at the same time in an IE. In the proposed method, reduction in size of the IE is achieved by sharing a few IBs between a large number of rules. To test the proposed method, a standard FLC is designed using both the regular method and the proposed method. By using the proposed method, total power consumption and active area are reduced by factors of 2.31 and 2.15, respectively. Moreover, inference speed is improved by a factor of 3.8 and output error is reduced by a factor of 2.5. All simulations have been performed in HSPICE using level 49 models for 0.35 um CMOS process with a 3.3V power supply. [ABSTRACT FROM AUTHOR]

A novel topology for a high gain two‐stage amplifier is proposed. The proposed circuit is designed in a way that the non‐dominant pole is at output of the first stage. A positive capacitive feedback around the second stage introduces a left half‐plane zero, which cancels the phase shift introduced by the non‐dominant pole, considerably. The dominant pole is at the output node, which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18 µm complementary metal‐oxide‐semiconductor process. It consumes 0.86 mW power from a 1.8 V power supply and occupies 3038.5 µm2 of chip area. The DC gain is 82.7 dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5 pF capacitive load. Also low frequency common‐mode rejection ratio and positive power supply rejection ratio are 127 and 83.2 dB, respectively. They are 24.8 and 24.2 dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, simulations show convenient performance of the circuit in process corners and also the presence of a mismatch. [ABSTRACT FROM AUTHOR]

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology. [ABSTRACT FROM AUTHOR]

An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation. [ABSTRACT FROM AUTHOR]

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched di®erential pairs. Duty cycle of output di®erential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05mm² active area in a 0.18μm CMOS technology. [ABSTRACT FROM AUTHOR]

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 ¡im CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 /¿m technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm-0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply. [ABSTRACT FROM AUTHOR]

A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30-70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30-70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle. [ABSTRACT FROM AUTHOR]

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity. [ABSTRACT FROM AUTHOR]

In this article, an analog fully programmable membership function generator (MFG) is presented. It is capable of generating Gaussian, Triangular and Trapezoidal shapes as well as S or Z shapes. For omitting noise disturbances, differential structures are utilized in input and output stages which are in voltage mode and current mode, respectively. In contrast with conventional MFGs which are controlled digitally or by mixed signal approaches, this structure is a fully programmable analog MFG. It is capable of modifying slope, position and height of output's current. The most distinguishing features of this MFG are its capability of generating ultra-high speed outputs reaching speeds as high as 200 MHz and consuming a very low amount of power. Due to the simple structure of this MFG, it consumes a small active area at the size of 20 μm × 30 μm. It is constructed of only 16 transistors. This MFG has been designed in 0.35 μm CMOS technology. The simulations have been done with Hspice using TSMC, BSIM3 (V3.1) model. [ABSTRACT FROM AUTHOR]

One of the active areas of fuzzy logic applications is control systems. In this paper presents a proposed Fuzzy Logic Controller (FLC) chip utilized a novel Membership Function Circuit (MFC) which can be made programmable. This membership function features of large dynamic range, high current driving, high noise immunity and is simply tunable by setting some voltages on IC pins. Each input of controller has five membership functions and output has seven singletons. A new structure for Min/Max operators, and also, a new current-mode divider circuit with very small area, very low power consumption and high speed and accurate are presented, which are compatible to the proposed MFC, are also given. This controller is a general-purpose two-input one-output fuzzy controller that can be implemented in 0.08-mm2 in 0.35-μm CMOS technology (BSIM3v3). For general control tasks, input-output inference of FLC is voltage/voltage. The maximum delay in output of FLC is about 67-ns that correspond to 15-MFLIPS (Fuzzy Logic Inference per Second) and power consumption is 2.5-mW. [ABSTRACT FROM AUTHOR]

A novel high speed linear tunable transconductor suitable for analog and mixed-signal fuzzy circuits operating in current mode is proposed. Using this OTA, we construct a high speed fuzzifier and implement trapezoidal/triangular functions with all parameters (slope, width, and position) independently and continuously tunable, and excellent for low voltage applications. Computer simulations verify the performance of this circuit, showing high speed (up to 100 MHz) and a high support range (up to 2.5 V). [ABSTRACT FROM AUTHOR]

Abstract: A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture. [Copyright &y& Elsevier]

Abstract: A novel single-stage second-order structure for Gm-C filters is presented. It allows ample reduction in hardware and thus power consumption. Moreover, due to exploiting otherwise parasitic poles, the structure allows much higher bandwidth than in conventional designs, be achieved. To verify effectiveness of new concept, and based on the new approach to implement second-order stages, a third-order and a fifth-order continuous-time low-pass filters were implemented. The filters fabricated in a CMOS process, achieved more than 430MHz, bandwidth and less than THD for a 400m 100MHz input signal. All these accomplished with a factor of about four reduction in hardware and power. The bandwidth, output voltage swing, and dynamic range are far larger than those of any other CMOS low-pass filters thus far reported, which have bandwidth higher than 100MHz. [Copyright &y& Elsevier]

The input differential pair (IDP) is usually a major source of nonlinear distortion in any op-amp. This is especially true if the input signal has a large common-mode component, as is the case when an op-amp functions as a unity-gain buffer or as part of a single-ended sample-hold (S/H) circuit. In this paper, we analyse the distortion of the commonly used cascode current source IDP structure and explain the sources of its nonlinear behaviour. Next, a special design technique is proposed which enhances the linearity of IDPs. The circuit uses a single device current source that has the same channel length while its width is double those of IDP devices. Theoretical analysis, as well as simulation and experimental results, is given to confirm the improved linearity of a unity gain buffer. Simulations predict improvements up to 20 dB. 15 dB total harmonic distortion (THD) reduction was also achieved for a 15 MHz input signal based on measurement of a test chip. The method is valuable as power supply voltages shrink, and the design offers extra voltage headroom at input. [ABSTRACT FROM AUTHOR]