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Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal–oxide–semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

Low-frequency noise is for the first time investigated in 0.12 μm Partially Depleted (PD) Silicon-On-Insulator (SOI) N-MOSFETs in comparison with established results on the 0.25 μm SOI CMOS technology node. The transfer and output characteristics of the devices are first addressed as well as an evaluation of the static performances. Then, we present low-frequency noise measurements carried out in both linear and saturation regimes taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case. A comparison is achieved with previously published results on 0.25 μm PD SOI N-MOSFETs, showing the drain current noise spectral densities, as well as the Kink-related excess noise occurring in the saturation regime. [Copyright &y& Elsevier]

In this paper, the impact of silicon film thickness on the electrical properties of deep submicron SOI devices is thoroughly investigated down to ultra-thin Si layers. Particular attention is paid to the behavior of the low frequency noise and hot-carrier-induced degradation for Si films down to 10 nm. [Copyright &y& Elsevier]

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on $Y$ -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices. [ABSTRACT FROM AUTHOR]

The impact on the extracted low‐frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed. [ABSTRACT FROM AUTHOR]

The impact of dynamic variability due to low-frequency fluctuations on the operation of CMOS inverters, which constitute the basic component of SRAM cell, is investigated. The experimental methodology to characterise the effect of dynamic variability in a CMOS inverter is first established based on fast I-V measurements of the load current following the application of a ramp input voltage Vin(t). It is shown that, for small ramp rise times, the load current characteristics IDD(Vin) exhibit a huge sweep-to-sweep dispersion due to low-frequency noise. The impact of such dynamic variability sources on the inverter's output characteristics Vout(Vin) is finally demonstrated, revealing a 20% noise margin reduction for the smallest inverter cell. [ABSTRACT FROM AUTHOR]

Investigates the low frequency noise behavior in fully depleted SOI/metal oxide semiconductor transistors in both ohmic and saturation regimes. Data on static measurements in the ohmic and saturation regimes; Noise in the saturation regime for SOI transistors.

In this work, we investigate the impact of the source - drain series resistance mismatch on the drain current variability in 28 nm bulk MOSFETs. For the first time, a mismatch model including the local fluctuations of the threshold voltage ( V t ), the drain current gain factor ( β ) and the source – drain series resistance ( R SD ) in both linear and saturation regions is presented. Furthermore, it is demonstrated that the influence of the source – drain series resistance mismatch is attenuated in the saturation region, due to the weaker sensitivity of the drain current variability on the series resistance variation. The experimental results were further verified by numerical simulations of the drain current characteristics with sensitivity analysis of the MOSFET parameters V t , β and R SD . [ABSTRACT FROM AUTHOR]

This work presents an investigation of DC and Low Frequency Noise dispersion in 0.13 μm SiGe:C BiCMOS Heterojunction Bipolar Transistors (HBTs) used for mm-Wave to Terahertz applications. Therefore, DC and Low Frequency Noise measurements have been performed over a half wafer on a large number of transistors. A statistical 1/ f noise compact model is presented as well as a study of the repartition of generation-recombination components. The main Low Frequency Noise sources are found to be homogenously distributed in the intrinsic base-emitter junction. The mean 1/ f noise level, evaluated by the figure of merit K Bmean , is equal to 6 10 −10 μm 2 . [ABSTRACT FROM AUTHOR]