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A modified and improved optical feedback pixel driver circuit with only a few components and a wide range of [V.sub.data] voltages is presented. The performance of the circuit is verified by simulation using the HSPICE simulator, PSIA2 thin-film transistor (TFT) model and light-impact model of polycrystalline TFTs.

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation. [ABSTRACT FROM AUTHOR]

In this paper, a new approach is presented for determining the substrate parameters of an arbitrary doping profile. It is general, technology independent, nonintrusive, and relies on simple direct-current measurements. A single measurement is required for uniform substrates, whereas two more measurements are needed for each additional layer in the multilayer case. Two different kernels are introduced for substrate resistance computation. One features a closed-form analytical solution of the Laplace equations defining the problem under study. The other relies on a geometric formulation of the current streamlines in order to compute the substrate resistance. Both simulations and measurements are exploited in order to show the validity of the proposed scheme. For measurements, data from literature are utilized and also data from a fabricated test chip. The results demonstrate that the proposed method succeeds in computing the substrate parameters fast and with high accuracy. In uniform substrates, the error falls to zero, whereas, in epitaxial substrates, the average error is kept bellow 4%. [ABSTRACT FROM AUTHOR]

Methods for testing both parametric and catastrophic faults in analog and mixed-signal circuits are presented. They are based on the wavelet transform (WT) of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform. The tolerance limit, which affects fault detectability, for the good or reference circuit is set by statistical processing data obtained from a set of fault-free circuits. In the wavelet analysis, two test metrics, one based on a discrimination factor using normalized Euclidean distances and the other utilizing Mahalanobis distances, are introduced. Both metrics rely on wavelet energy computation. Simulation results from the application of the proposed test methods in testing known analog and mixed-signal circuit benchmarks are given. In addition, experimental results from testing actual circuits and from production line testing of a commercial electronic circuit are presented. These results show the effectiveness of the proposed test methods employing the two test metrics against three other test methods, namely, a test method based on the root-mean-square value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum, and a method based on the WT of the measured signal. [ABSTRACT FROM AUTHOR]

A method for calculating capacitive and resistive coupling is developed in this work, and its implementation in commonly encountered practical cases is presented. The method is based on the geometry of the coupling mechanism, and the derived model is therefore, in general, scalable and technology independent. The constraints of any related problem can easily be incorporated into this method, whereas pure 3-D effects, such as capacitive coupling, are fast and accurately computed. The proposed method is validated using measurements from a test chip in the UMC 0.18-µm CMOS lightly doped process, simulation data obtained by two commercial simulators, and theoretical results. The accuracy of the method is shown to be within 2%-10%. [ABSTRACT FROM AUTHOR]

A method using the power supply current for fault detection in analog and mixed-mode circuits is presented. A new unified fault detection procedure is introduced, and its fault detection capability is estimated. The procedure combines the rms value and the magnitude and phase components of the power supply current. Certain required discrimination factors are defined, and their values are adjusted to include circuit parameter deviations and matching dependencies for the efficient application of the method. Representative results from the simulation of an operational amplifier (opamp) and a flash analog-to-digital converter circuit are given, showing the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]