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Because high‐status employees make disproportional contributions to firms, prior literature suggests that their departure would undermine various organizational outcomes. Building on recent literature, however, we suspect that a high‐status employee may have seized disproportional resources and credits from coworkers, thereby restricting them from performing, particularly when the work context is more independent and contested. As a result, the departure of a high‐status employee may bring staying coworkers more resources and incentives to perform, causing their performance to improve. To test this possibility, we examine the effect of high‐status analysts' departure on the individual performance of analysts who remain, using a sample of sell‐side analysts in Chinese financial brokerage firms. Employing a before‐and‐after treatment research design, we find evidence that after the departure of a high‐status analyst, the staying coworkers' individual performance is significantly improved. It is particularly so when they share greater industry overlap with the departing analyst. Our extensional analyses also investigate additional contingencies, which helps provide valuable hints about possible mechanisms. [ABSTRACT FROM AUTHOR]

In this study, we argue that managing technological entrepreneurship effectively is crucial for firms' competitive advantage and high performance. By using an inductive approach of a multiple-case study of Chinese technology-based manufacturing firms, we identify four complementary patterns of technological entrepreneurship (i.e. in-house R&D, R&D acquisition, R&D alliance, and R&D contracting) and find that possessing the uniqueness of knowledge assets and technological capabilities and capturing the value of knowledge assets and technological capabilities are the major determinants for firms to choose these patterns. Our study develops an integrative framework of technological entrepreneurship for emerging economy firms. Implications for theory, practice, and policy are discussed. [ABSTRACT FROM AUTHOR]

A non-linear unrestraint optimization model of mine ventilation network was established which took the minimum total energy consumption of mine ventilation network as optimization objective. In order to improve optimization ability and convergence speed of the model, an opposition-based enhanced fireworks algorithm(OBEFWA) was proposed. Firstly, population initialization strategy based on opposition-based learning and uniform randomization is adopted, and uniform randomization population generated by the strategy is competed with opposition-based population, so that the optimal initial population is selected as starting point of subsequent search. Secondly, fireworks explosion radius is finely controlled, so that explosion radius of fireworks populations of different generations shows non-linear decline, and that of the same population generation is coordinated and distriblted according to their own fitness values. The minimum dynamic threshold is set to decrease waste of search resources. Finally, selection strategy of elite opposition-based learning is adopted to strengthen search for neighborhood of elite fireworks, so as to improve global exploration ability of the algorithm. The experimental results show that total energy consumption of mine ventilation network optimized by OBEFWA decreases about 23.2% which meets adjustment constraints and wind demand of actual ventilation network, and OBEFWA has better optimization effect than particle swarm optimization algorithm and enhanced fireworks algorithm.

The modern cryptographic protocol specifies that only authorized participants can gain access to the key and obtain information. However, the way to leak passwords through intrusion into the system is endless, causing serious problems for modern information security. On this issue, the advantages of PUF for information security to provide further protection. For example:Arbiter PUF，RO PUF,SRAM PUF. This project is designed to integrate the physical information into the circuit design to achieve the design of the PUF. Comparing to existing RO-PUF, PISO shift register reduce the hardware. A 4-bit challenge can produce 16-bit random response, which greatly increases the number of challenge response pair, and the internal Hamming distance is measured by the FPGA.

The widespread use of chemical herbicides has jeopardized concerns about food safety and ecological consequences. To address these issues and reduce reliance on chemical herbicides, a physical weed control device was developed for the tillering stage in paddy fields. This device features a biomimetic duckbill-like vibration chain that effectively controls weed outbreaks. The chain penetrates the soft surface soil of the paddy field under gravity and rapidly stirs the soil through vibration, leading to the detachment of the weed roots anchored in the surface layer. Simultaneously, the device avoids mechanical damage to rice seedlings rooted in deeper soil. This study aimed to investigate the effects of chain structural parameters (the number of chain rows, vibration amplitude, and length of chains) and operational parameters (vibration frequency and working velocity) on weed control efficiency and rice seedling damage. Through a central composite regression field test, the optimal device structure and operational parameters were determined. The optimization results demonstrated that a vibration amplitude of 78.8 mm, a chain length of 93.47 cm, and 3.4 rows of chains, along with a vibration frequency and working velocity ranging from 0.5 to 1.25 m/s, achieved an optimal weeding effect. Under the optimal parameter combination, field test results demonstrated that approximately 80% of the weeds in the field were effectively cleared. This indicates that the design of the biomimetic duckbill-like vibration chain weeding device exhibits a relatively superior weeding performance, offering a practical solution for the management of weeds in rice fields. [ABSTRACT FROM AUTHOR]

To realize the autonomous operation of a terraced rice sowing robot, a set of sowing robot operation path planning algorithms with universal significance for small, irregular terraced plots is proposed. According to the characteristics of terraces and the agronomic requirements of sowing seeding, the operation path mainly includes parallel operation and boundaries surrounding the operation path. The boundary pre-collision detection method is expounded, and the cyclic detection method judges the U-turn area. The Bézier curve fitting algorithm was used to smooth the boundary wrapping path. To verify the feasibility of the algorithm, four typical irregular small fields located in 666.7-hectare terraces of Sama in Hong He Prefecture, Yunnan Province, were randomly selected, and a field map was obtained through Google Earth. An existing seeding robot was used as a model, and the simulation and comparison tests were carried out with the mainstream EHNS algorithm and boundary polyline algorithm under the ROS-kinetic platform in the Cen Village Scientific Research Base of South China Agricultural University. The actual boundaries of the four fields with the same simulation test were used as the map to verify the field experiment. The simulation test results show that the area coverage of the sowing operation is greater than 93.53% and the replay rate is less than 3.46%, and the field test results show that the area coverage of the sowing operation is greater than 94.33% and the replay rate is less than 3.03%. The simulation test is in good agreement with the field test results, indicating that the algorithm has good adaptability, which meets the requirements of a sowing robot for sowing operation path planning and can provide a certain reference for the path planning of irregular field operation robots in hilly and mountainous areas. [ABSTRACT FROM AUTHOR]

The computation of the Moore–Penrose inverse is widely encountered in science and engineering. Due to the parallel‐processing nature and strong‐learning ability, the neural network has become a promising approach to solving the Moore–Penrose inverse recently. However, almost all the existing neural networks for matrix inversion are based on the gradient‐descent (GD) method, whose main drawbacks are slow convergence and sensitivity to learning parameters. Moreover, there is no unified neural network to compute the Moore–Penrose inverse for both the full‐rank matrix and rank‐deficient matrix. In this paper, an efficient second‐order neural network model with the improved Newton's method is proposed to obtain the accurate Moore–Penrose inverse of an arbitrary matrix by one epoch without any learning parameter. Compared with the GD‐based neural networks for Moore–Penrose inverse computation, the proposed model converges faster and has lower complexity. Furthermore, through in‐depth derivation, the neural network for computing the Moore–Penrose inverse is well interpretable. Numerical studies and application to the random matrix inversion in multiple‐input multiple‐output detection are provided to validate the efficiency of the proposed model for solving the Moore–Penrose inverse. [ABSTRACT FROM AUTHOR]

Linear minimum mean square error (MMSE) detection achieves a good trade‐off between performance and complexity for massive multiple‐input multiple‐output (MIMO) systems. To avoid the high‐dimensional matrix inversion involved, MMSE detection can be transformed into an unconstrained optimization problem and then solved by efficient numerical algorithms in an iterative way. Three low‐complexity Broyden‐Fletcher‐Goldfarb‐Shanno (BFGS) quasi‐Newton methods are proposed to iteratively realize massive MIMO MMSE detection without matrix inversion. The complexity can be reduced from O(K3)$\mathcal {O}(K^{3})$ to O(LK2)$\mathcal {O}(LK^{2})$, where K and L denote the number of users and iterations, respectively. Leveraging the special properties of massive MIMO, the authors first explore a simplified BFGS method (named S‐BFGS) to alleviate the computational burden in the search direction. For lower complexity, BFGS method with the unit step size (named U‐BFGS) is presented subsequently. When the base station (BS)‐to‐user‐antenna ratio (BUAR) is large enough, the two proposed BFGS methods can be integrated (named U‐S‐BFGS) to further reduce complexity. In addition, an efficient initialization strategy is devised to accelerate convergence. Simulation results verify that the proposed detection scheme can achieve near‐MMSE performance with a small number of iterations L as low as 2 or 3. [ABSTRACT FROM AUTHOR]

For massive multiple-input multiple-output (MIMO) systems, minimum mean square error (MMSE) detection is near-optimal, but requires high-complexity matrix inversion. To avoid matrix inversion, we formulate MMSE detection as a strictly convex quadratic optimization problem, which can be solved iteratively by the recognized most efficient Broyden-Fletcher-Goldfarb-Shanno (BFGS) quasi-Newton method. According to special properties of massive MIMO systems, we propose a novel limited-memory BFGS (L-BFGS) scheme for MMSE detection with one correction search, unit step length, and simplified initialization, which can greatly reduce the storage and computation cost compared to BFGS method. Simulation results finally verify the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

Expectation Propagation (EP)-based Multiple-Input Multiple-Output (MIMO) detector achieves exceptional performance in high-dimensional systems with high-order modulations and flexible antenna configurations. However, based on our studies, the EP MIMO detector cannot achieve superior performance due to the empirical parameter selection, including initial variance and damping factors. According to the influence of the moment matching and parameter selection on the performance of the EP MIMO detector, we propose a modified EP MIMO detector (MEPD). To obtain the initial variance and damping factors which lead to better performance, we adopt a deep learning scheme, the iterative process of MEPD is unfolded to establish MEPNet for parameters training. The simulation results show that MEPD with off-line trained parameters outperforms the original one in various MIMO scenarios. Besides, the proposed MEPD with deep learning parameters selection is more robust than EPD in practical scenarios. [ABSTRACT FROM AUTHOR]

Multiple-input Multiple-output (MIMO) technologies play an important role in modern and future wireless communication systems as they can improve the capacity without increasing the bandwidth. MIMO detection is one of the key technologies for MIMO system designs. MIMO detection schemes based on Message Passing (MP) algorithms have attracted extensive attention in recent years. The MIMO detection scheme based on Expectation Propagation (EP), which is also a kind of MP algorithms, has been proved to achieve the Bayes-optimal performance under the conditions of large system limit and compression rate threshold. However, there is improvement space for the detection performance of the EP algorithm when the conditions are not satisfied, which are the common cases in the practical applications. In this paper, when the conditions of the large system limit and compression rate threshold are not satisfied, we analyze the influences of two factors, the initial parameters selection and the moment matching strategy, on the performance of EP based detection scheme. As a result, we propose an improved EP detection scheme based on optimizing the two factors. Simulation results show that the proposed scheme outperforms the original EP detection scheme in different MIMO scenarios. [ABSTRACT FROM AUTHOR]

Polar codes have received recent attention due to their potential to be applied in advanced wireless communication protocols such as the fifth generation mobile communication system (5G). Among the existing decoding algorithms, Belief Propagation (BP) exhibits high-throughput, low-latency, and soft output with a high hardware cost. Stochastic computing, as a form of approximate computing, provides a potential low-cost implementation solution for the BP algorithm. However, existing stochastic BP decoders suffer from a relatively long decoding latency resulting in low hardware efficiency. In this paper, a novel bit-wise iterative stochastic decoding architecture for the BP algorithm is proposed to improve the throughput and hardware efficiency. By utilizing the frozen bits of polar codes and stochastic computing, multiple novel optimization methods are presented to further speed up convergence and increase the hardware efficiency. [ABSTRACT FROM AUTHOR]

An efficient resource sharing strategy is proposed for multimedia wireless networks. Assume the channel resource in a wireless system is partitioned into two sets: one for voice calls and one for video calls. In the proposed channel borrowing strategy, voice calls can borrow channels from those pre-allocated to video calls temporarily when all voice channels are busy. A threshold type decision policy is designed such that the channel borrowing request will be granted only if the quality of service (QoS) requirement on video call blocking will not be violated during the duration of channel lending. An analytical model is constructed for evaluating the performance of the channel borrowing strategy in a simplified wireless system and is verified by computer simulations. We found that the proposed channel borrowing scheme can significantly reduce the voice call blocking probability while the increase in video call blocking probability is insignificant. Index Terms--Channel borrowing strategy, performance analysis, QoS guarantee, resource sharing.

Triple-modular redundancy (TMR), which consists of three identical modules and a voting circuit, is a common architecture for soft-error tolerance. However, the original TMR suffers from two major drawbacks: the large area overhead and the vulnerability of the voter. In order to overcome these drawbacks, we propose a new complementary dual-modular redundancy (CDMR) scheme for mitigating the effect of soft errors. Inspired by the Markov random field (MRF) theory, a two-stage voting system is implemented in CDMR, including a first-stage optimal MRF structure and a second-stage high-performance merging unit. The CDMR scheme can reduce the voting circuit area by 20% while saving the area of one redundant module, achieving at least 26% error-rate reduction at an ultralow supply voltage of 0.25 V with 8.33% faster timing compared to previous voter designs. [ABSTRACT FROM AUTHOR]

Reliability is one of the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques have been applied to logic circuits to resist random noise when operating under ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks can be easily mapped onto simple logic circuits, it becomes difficult when the circuits are large and complex. In this paper, we present a general coding-based partial MRF (CPMRF) method for multi-logic operations in one basic unit, which is referred to as a CPMRF pair. A CPMRF pair saves circuit area by sharing a common MRF network. It also inherits noise immunity from the MRF theory while obtaining noise immunity from the coding structure as a combination of robust “1s” and “0s.” The resulting architectures become more cost effective than conventional ones. To validate the performance of our proof-of-concept design, we fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM 130-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20% improvement while occupying 37.7% less area and reducing power consumption by 93% compared with the master-and-slave MRF CLA design. [ABSTRACT FROM AUTHOR]

In conventional stochastic computation, all the input streams are Bernoulli sequences (BSs), which may result in large random error. To reduce random error and improve computational accuracy, some other sequences have been reported as alternatives to BSs. However, these sequences only apply to the specific stochastic circuits, have difficulties in hardware generation, or have length constraints. To this end, new sequences without these disadvantages should be considered. This paper proposes the random error analysis method for stochastic computation based on autocorrelation sequence (AS), which is more general than the conventional one based on BS. The analysis results show that we can use the proper ASs as input streams of stochastic circuits to reduce random error. On the basis of that conclusion, we propose the random error reduction scheme based on maximal concentrated autocorrelation sequence (MCAS) and BS, both of which are ASs. MCAS and BS are applicable to any combinational stochastic circuit, are easily generated by hardware, and have no length constraints, which avoid the disadvantages of sequences in the previous work. Moreover, we apply the proposed random error reduction scheme into several typical stochastic circuits as case studies. The simulation results confirm the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

Nonorthogonal multiple access technology has been proposed for use in 5G communications systems. In particular, the sparse code multiple access (SCMA) scheme is believed to be one of the most promising techniques among the various nonorthogonal approaches that have been investigated. In this letter, we focus on reducing the complexity of SCMA decoding and we propose a Monte Carlo Markov Chain (MCMC) based SCMA decoder. Benefiting from the linearly increasing complexity of the MCMC method, the proposed SCMA decoder has only 10% of the computational load compared to previous state-of-the-art methods when the codebook size is 64. Consequently, the MCMC SCMA decoder has great potential for use in practical system implementations. [ABSTRACT FROM AUTHOR]

In this paper, we design a hardware and energy-efficient stochastic lower–upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy with relative short length stochastic stream. We have designed and synthesized the stochastic LUD with CMOS 130-nm technology. According to the postlayout report, the hardware efficiency of the stochastic LUD is as high as $1.5\times $ compared with the exiting LUD methods, and the energy efficiency is also higher than the state-of-the-art LUD when the matrix dimension is $8\times 8$ and larger. [ABSTRACT FROM AUTHOR]

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed–area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18- \mum technology are also provided. [ABSTRACT FROM PUBLISHER]

In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties of RNS, including shorter critical path, low complexity, and low power. Moreover, JRR can achieve higher power reduction than RNS for VOS applications. Since the soft errors caused by VOS lead to significant performance degradation of RNS, we use the information from RNS and RPR to achieve a high recovering probability of the soft errors with low hardware complexity. From the case study of finite impulse response (FIR) filter design based on the 0.25-\mum 2.5-V CMOS technology, we find that JRR can save 62% more energy compared to the traditional FIR with a less than 2-dB signal noise ratio performance loss. We also find that JRR has lower complexity and better performance than the traditional soft error mitigation methods. [ABSTRACT FROM PUBLISHER]

Abstract: Achieving high speed and reliability is a key challenge in on-chip bus design. To address the challenge, in this paper we propose a fault model for on-chip communication and further develop a new joint scheme which integrates an equalization technique and special spacing rules for improving the speed and communication reliability for on-chip buses. The proposed equalizer employs a variable threshold inverter whose switching threshold is adjusted as a function of the past output of the buses to achieve high-speed and high-reliability of the buses. Special spacing rules use the sufficient spacing between the adjacent wires to mitigate the crosstalk effect from the adjacent wires. The joint scheme equalization and special spacing rules exploits their respective advantages to further improve the speed and communication reliability of the buses. The simulation results show that the joint scheme equalization and increasing spacing of the uncoded bus can reduce 50% delay and save 42% power only with 52% area overhead compared with the minimum-spaced uncoded bus. The bit error rate of the bus can be improved from 10−5 to 10−24. [Copyright &y& Elsevier]

Abstract: Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies. [Copyright &y& Elsevier]

We propose an effective scheme based on redundant residue number systems (RRNS) for radiation hardening of datapath in this paper. The proposed hardening scheme employs redundant residues to mitigate soft errors. We use the properties of RRNS, such as independence, parallel and error correction, to establish the radiation hardening architecture for datapath in radiation environments. In the architecture, all of the residues can be processed independently, and most of soft errors in datapath can be corrected with the redundant relationship of the residues at correction module, which is allocated at the end of the architecture. There is not any additional processing in the architecture but correction operation and binary to residue translation. Thus, the proposed scheme has high efficiency when the processing steps of datapath are large. In order to provide protection for the key module in the proposed scheme, correction module, some traditional protection methods, including Guard-gate register triple modular redundancy (G-RTMR), pipeline-level TMR, and module-level TMR, are used to construct the hybrid protection schemes. In the case studies, we find that the RRNS based scheme and the hybrid schemes can reduce soft error rate from 10-12 to 10-17, -18,10-25, and -25-respectively, only with 45.-46.1% area overheads and negligible latency overheads, when the pipeline stages of datapath are 104 and the moduli set with correction capability of one residue is adopted. The case studies also show that the proposed schemes can achieve less area and latency overheads than that of datapath without radiation hardening, because RRNS can reduce the complexity of operations in datapath. [ABSTRACT FROM AUTHOR]

High efficient implementation of scaling in residue number system (RNS) is one of the critical issues for the applications of RNS in digital signal processing (DSP) systems. In this paper, an efficient scaling algorithm for signed integers in RNS is proposed firstly through introducing a correction constant in negative integers scaling procedure. Based on the proposed scaling algorithm, an efficient RNS 2 n scaling implementation method is presented, in which Chinese remainder theorem (CRT) and a redundant modulus are used to perform the base extension to obtain the least significant n bits of RNS integers. With the redundant modulus, the RNS sign detection can be achieved by the parity detection. And then, an approach to update the residue digit of the redundant channel is also proposed. Meanwhile, this paper provides a method of computing the correction constant of the redundant channel in negative integers scaling. The analysis results indicate that the complexity of the proposed scaling algorithm grows linearly with the word-length of the RNS dynamic range without using Look-up Table (LUT). Furthermore, the proposed algorithm is employed for a specific moduli set 2 n scaling. The synthesis results show that the critical path of the proposed algorithm is shortened by 12%, the area and power consumption performance is improved by about 35%, compared to the existing cascading 2 n scaling method for very large scale integration (VLSI) implementation under the same restriction. Besides, the VLSI layout indicates that the parallel structure is simpler. [ABSTRACT FROM AUTHOR]

Residue number system (RNS) has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, subtraction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory (CRT) and mixed radix conversion (MRC) for the moduli set {2 n − 1, 2 n + 1, 22 n + 1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS. [ABSTRACT FROM AUTHOR]

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes. [ABSTRACT FROM AUTHOR]

The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two's Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2 n − 1 , 2 n , 2 n + 1 , which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2 n − 1 , 2 n , 2 n + 1 . Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR. [ABSTRACT FROM AUTHOR]

The past few decades have witnessed a substantial increase in terahertz (THz) research. Utilizing THz waves to transmit communication and imaging data has created a high demand for phase and amplitude modulation. However, current active THz devices, including modulators and switches, still cannot meet THz system demands. Double-channel heterostructures, an alternative semiconductor system, can support nanoscale two-dimensional electron gases (2DEGs) with high carrier concentration and mobility and provide a new way to develop active THz devices. In this Letter, we present a composite metamaterial structure that combines an equivalent collective dipolar array with a double-channel heterostructure to obtain an effective, ultrafast, and all-electronic grid-controlled THz modulator. Electrical control allows for resonant mode conversion between two different dipolar resonances in the active device, which significantly improves the modulation speed and depth. This THz modulator is the first to achieve a 1 GHz modulation speed and 85% modulation depth during real-time dynamic tests. Moreover, a 1.19 rad phase shift was realized. A wireless free-space-modulation THz communication system based on this external THz modulator was tested using 0.2 Gbps eye patterns. Therefore, this active composite metamaterial modulator provides a basis for the development of effective and ultrafast dynamic devices for THz wireless communication and imaging systems.