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We explore a novel data representation scheme for multilevel flash memory cells, in which a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The only allowed charge-placement mechanism is a "push-to-the-top" operation, which takes a single cell of the set and makes it the top-charged cell. The resulting scheme eliminates the need for discrete cell levels, as well as overshoot errors, when programming cells. We present unrestricted Gray codes spanning all possible n-cell states and using only "push-to-the-top" operations, and also construct balanced Gray codes. One important application of the Gray codes is the realization of logic multilevel cells, which is useful in conventional storage solutions. We also investigate rewriting schemes for random data modification. We present both an optimal scheme for the worst case rewrite performance and an approximation scheme for the average-case rewrite performance. Index Terms--Asymmetric channel, flash memory, Gray codes, permutations, rank modulation.

Non-volatile memories suffer from two challenges due to their physical and system-level constraints. One challenge is limited memory lifetime, also called the endurance problem. The other is the difficulty in deleting data securely, called the insecure deletion problem. This paper proposes a coding scheme that addresses both challenges jointly. It studies the secure write-efficient memory (WEM) by analyzing its rewriting-rate equivocation region and secrecy rewriting capacity. It also presents an optimal code construction for a large family of secure WEM channels. [ABSTRACT FROM AUTHOR]

We propose efficient coding schemes for two communication settings: 1) asymmetric channels and 2) channels with an informed encoder. These settings are important in non-volatile memories, as well as optical and broadcast communication. The schemes are based on non-linear polar codes, and they build on and improve recent work on these settings. In asymmetric channels, we tackle the exponential storage requirement of previously known schemes that resulted from the use of large Boolean functions. We propose an improved scheme that achieves the capacity of asymmetric channels with polynomial computational complexity and storage requirement. The proposed non-linear scheme is then generalized to the setting of channel coding with an informed encoder using a multicoding technique. We consider specific instances of the scheme for flash memories that incorporate error-correction capabilities together with rewriting. Since the considered codes are non-linear, they eliminate the requirement of previously known schemes (called polar write-once-memory codes) for shared randomness between the encoder and the decoder. Finally, we mention that the multicoding scheme is also useful for broadcast communication in Marton’s region, improving upon previous schemes for this setting. [ABSTRACT FROM PUBLISHER]

The current flash memory technology focuses on the cost minimization of its static storage capacity. However, the resulting approach supports a relatively small number of program-erase cycles. This technology is effective for consumer devices (e.g., smartphones and cameras) where the number of program-erase cycles is small. However, it is not economical for enterprise storage systems that require a large number of lifetime writes. The proposed approach in this paper for alleviating this problem consists of the efficient integration of two key ideas: 1) improving reliability and endurance by representing the information using relative values via the rank modulation scheme and 2) increasing the overall (lifetime) capacity of the flash device via rewriting codes, namely, performing multiple writes per cell before erasure. This paper presents a new coding scheme that combines rank-modulation with rewriting. The key benefits of the new scheme include: 1) the ability to store close to 2 bit per cell on each write with minimal impact on the lifetime of the memory and 2) efficient encoding and decoding algorithms that make use of capacity-achieving write-once-memory codes that were proposed recently. [ABSTRACT FROM PUBLISHER]

The rank-modulation scheme has been recently proposed for efficiently storing data in nonvolatile memories. In this paper, we explore $[n,k,d]$ systematic error-correcting codes for rank modulation. Such codes have length $n$ , $k$ information symbols, and minimum distance $d$ . Systematic codes have the benefits of enabling efficient information retrieval in conjunction with memory-scrubbing schemes. We study systematic codes for rank modulation under Kendall’s $\tau $ -metric as well as under the $\ell _\infty $ -metric. In Kendall’s $\tau $ -metric, we present $[k+2,k,3]$ systematic codes for correcting a single error, which have optimal rates, unless systematic perfect codes exist. We also study the design of multierror-correcting codes, and provide a construction of $[k+t+1,k,2t+1]$ systematic codes, for large-enough $k$ . We use nonconstructive arguments to show that for rank modulation, systematic codes achieve the same capacity as general error-correcting codes. Finally, in the $\ell _\infty $ -metric, we construct two $[n,k,d]$ systematic multierror-correcting codes, the first for the case of $d=O(1)$ and the second for $d=\Theta (n)$ . In the latter case, the codes have the same asymptotic rate as the best codes currently known in this metric. [ABSTRACT FROM PUBLISHER]

An introduction is presented in which the editor discusses various articles within the issue on topics including the design of an optimal detector for multi-level flash devices, the use of distributed storage systems for data analysis and coding methods for cloud storage systems.

This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower than recommended by a microcontroller's specifications in order to reduce energy consumption. Flash memory integrated within a microcontroller typically requires the entire chip to operate on a common supply voltage almost twice as much as what the CPU portion requires. Our software approach allows the flash memory to tolerate a lower supply voltage so that the CPU may operate in a more energy-efficient manner. Energyefficient coding algorithms then cope with flash memory writes that behave unpredictably. Our software-only coding algorithms (in-place writes, multiple-place writes, RS-Berger codes, and slow writes) enable reliable storage at low voltages on unmodified hardware by exploiting the electrically cumulative nature of half-written data in write-once bits. For a sensor monitoring application using the MSP430, coding with in-place writes reduces the overall energy consumption by 34%. In-place writes are competitive when the time spent on low-voltage operations such as computation are at least four times greater than the time spent on writes to flash memory. Our evaluation shows that tightly maintaining the digital abstraction for storage in embedded flash memory comes at a significant cost to energy consumption with minimal gain in reliability. We find our techniques most effective for embedded workloads that have significant duty cycling, rare writes, or energy harvesting. [ABSTRACT FROM AUTHOR]

Flash memories are currently the most widely used type of nonvolatile memories. A flash memory consists of floating-gate cells as its storage elements, where the charge level stored in a cell is used to represent data. Compared to magnetic recording and optical recording, flash memories have the unique property that the cells are programmed using an iterative procedure that monotonically shifts each cell's charge level upward toward its target value. In this paper, we model the cell as a monotonic storage channel, and explore its capacity and optimal programming. We present two optimal programming algorithms based on a few different noise models and optimization objectives. [ABSTRACT FROM AUTHOR]

A write-once memory (wom) is a storage medium formed by a number of “write-once” bit positions (wits), where each wit initially is in a “0” state and can be changed to a “1” state irreversibly. Examples of write-once memories include SLC flash memories and optical disks. This paper presents a low complexity coding scheme for rewriting such write-once memories, which is applicable to general problem configurations. The proposed scheme is called the position modulation code, as it uses the positions of the zero symbols to encode some information. The proposed technique can achieve code rates higher than state-of-the-art practical solutions for some configurations. For instance, there is a position modulation code that can write 56 bits 10 times on 278 wits, achieving rate 2.01. In addition, the position modulation code is shown to achieve a rate at least half of the optimal rate. [ABSTRACT FROM AUTHOR]

We investigate error-correcting codes for a the rank-modulation scheme with an application to flash memory devices. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, overcomes overshoot errors when programming cells (a serious problem that reduces the writing speed), and mitigates the problem of asymmetric errors. In this paper, we study the properties of error-correcting codes for charge-constrained errors in the rank-modulation scheme. In this error model the number of errors corresponds to the minimal number of adjacent transpositions required to change a given stored permutation to another erroneous one--a distance measure known as Kendall's τ-distance. We show bounds on the size of such codes, and use metric-embedding techniques to give constructions which translate a wealth of knowledge of codes in the Lee metric to codes over permutations in Kendall's τ-metric. Specifically, the one-error-correcting codes we construct are at least half the ball-packing upper bound. [ABSTRACT FROM AUTHOR]

This paper studies t-interleaving on two-dimensional tori. Interleaving has applications in distributed data storage and burst error correction, and is closely related to Lee metric codes. A t-interleaving of a graph is defined as a vertex coloring in which any connected subgraph of t or fewer vertices has a distinct color at every vertex. We say that a torus can be perfectly t-interleaved if its t-interleaving number (the minimum number of colors needed for a t-interleaving) meets the sphere-packing lower bound, [t²/2]. We show that a torus is perfectly t-interleavable if and only if its dimensions are both multiples of t²+1/2 (if t is odd) or t (if t is even). The next natural question is how much bigger the t-interleaving number is for those tori that are not perfectly t-interleavable, and the most important contribution of this paper is to find an optimal interleaving for all sufficiently large tori, proving that when a torus is large enough in both dimensions, its t-interleaving number is at most just one more than the sphere-packing lower bound. We also obtain bounds on t-interleaving numbers for the cases where one or both dimensions are not large, thus completing a general characterization of t-interleaving numbers for two-dimensional tori. Each of our upper bounds is accompanied by an efficient t-interleaving scheme that constructively achieves the bound. [ABSTRACT FROM AUTHOR]

Phage P1 is a temperate phage which makes the lytic or lysogenic decision upon infecting bacteria. During the lytic cycle, progeny phages are produced and the cell lyses, and in the lysogenic cycle, P1 DNA exists as a low-copy-number plasmid and replicates autonomously. Previous studies at the bulk level showed that P1 lysogenization was independent of m ultiplicity o f i nfection (MOI; the number of phages infecting a cell), whereas lysogenization probability of the paradigmatic phage λ increases with MOI. However, the mechanism underlying the P1 behavior is unclear. In this work, using a fluorescent reporter system, we demonstrated this P1 MOI-independent lysogenic response at the single-cell level. We further observed that the activity of the major repressor of lytic functions (C1) is a determining factor for the final cell fate. Specifically, the repression activity of P1, which arises from a combination of C1, the anti-repressor Coi, and the corepressor Lxc, remains constant for different MOI, which results in the MOI-independent lysogenic response. Additionally, by increasing the distance between phages that infect a single cell, we were able to engineer a λ-like, MOI-dependent lysogenization upon P1 infection. This suggests that the large separation of coinfecting phages attenuates the effective communication between them, allowing them to make decisions independently of each other. Our work establishes a highly quantitative framework to describe P1 lysogeny establishment. This system plays an important role in disseminating antibiotic resistance by P1-like plasmids and provides an alternative to the lifestyle of phage λ. IMPORTANCE Phage P1 has been shown potentially to play an important role in disseminating antibiotic resistance among bacteria during lysogenization, as evidenced by the prevalence of P1 phage-like elements in animal and human pathogens. In contrast to phage λ, a cell fate decision-making paradigm, P1 lysogenization was shown to be independent of MOI. In this work, we built a simple genetic model to elucidate this MOI independency based on the gene-regulatory circuitry of P1. We also proposed that the effective communication between coinfecting phages contributes to the lysis-lysogeny decision-making of P1 and highlighted the significance of spatial organization in the process of cell fate determination in a single-cell environment. Finally, our work provides new insights into different strategies acquired by viruses to interact with their bacterial hosts in different scenarios for their optimal survival.