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Crystallization (set) time is a key bottleneck to achieve high-speed programming in phase change memory (PCM). Overcoming this limitation requires a deeper understanding of the solidification processes within nanoscale device configuration. This study explores crystallization dynamics in Ge2Sb2Te5 by measuring the transient resistance and power during the set process in confined PCM cells with nanosecond resolution. The transient resistance probes the phase, while the power can be used to evaluate temperature, thus uncovering details of the phase change dynamics. Our findings reveal a notable trend indicating that solidification from the melt results in faster crystallization compared with annealing the glassy state. Moreover, we observed notable differences in the solidification dynamics during set (crystallization) and reset (amorphization) pulses. Our nanosecond transient measurement methodology proves valuable in revealing crucial aspects of PCM crystallization dynamics, holding the potential to enable higher-speed programming. [ABSTRACT FROM AUTHOR]

Despite their great synaptic potential, the trade-off between programming speed and energy consumption of electrochemical random-access memory (ECRAM) devices are major hindrance to their incorporation into practical applications. In this work, we experimentally study the main limiting factor for high-speed programming of ECRAMs, the ionic current in the gate stack. We use two-terminal structures composed of LiCoO2/Li3PO4/amorphous-Si to represent the ECRAM gate stack (reservoir/electrolyte/channel). We perform electrical characterization including impedance spectroscopy (small-signal) and large-signal transient measurements across nine orders of magnitude in the time domain. We find that at the sub-microseconds range, the current is governed by the energy barrier for Li+ ions at the electrolyte interfaces. After a period of ∼1 μs, ionic migration through the ∼80 nm electrolyte layer dictates the current. At ∼50 μs, the ionic double layer at the interface is fully charged and the gate current drops by several orders of magnitude, indicating that the Li3PO4/Si interface is saturated, and the measured current is dominated by the electronic leakage component. Furthermore, we evaluate ECRAM performance under various pulse parameters. Our predictions show that an aggressively scaled (atomically thin) channel having a low carrier density of ∼1011 cm−2 can be programmed at ∼nanosecond using a gate current of ∼100 A/cm2. [ABSTRACT FROM AUTHOR]

One of the key challenges of phase change memory (PCM) is its high power consumption during the reset operation, when the phase change material (typically Ge2Sb2Te5, i.e., GST) heats up to ∼900 K or more in order to melt. Here, we study the temperature-dependent behavior of PCM devices by probing the reset power at ambient temperatures from 80 to 400 K. We find that different device structures exhibit contrasting temperature-dependent behavior. The reset power in our confined-type PCM is nearly unchanged with ambient temperature, corresponding to a temperature-dependent thermal resistance, whereas results for mushroom-type PCM from the literature show a linear relation between power and temperature, suggesting a more constant thermal resistance. This discrepancy is ascribed to different temperature distributions and thermal properties of the dominant components of the PCM cell thermal resistance, as shown by electro-thermal modeling. In the confined cell, the thermal boundary resistance of the GST and the thermal conductivity of the bottom electrode dominate the thermal resistance, while for the mushroom cell, the GST thermal conductivity plays a greater role. These findings can help to design more power- and energy-efficient PCM devices by better focusing thermal management efforts on the key components of the device. [ABSTRACT FROM AUTHOR]

A key bottleneck in using phase change memory (PCM) for training artificial neural networks is the abrupt nature of the melt-quench process (amorphization), which does not allow gradual reset. Here we demonstrate analog reset (partial amorphization) in PCM by applying sub-nanosecond programming pulses. Intermediate-level reset states are enabled by reducing the pulse width below the dominant thermal time constant of the PCM, which is on the order of a few nanoseconds. We show gradual change in PCM resistance as a function of number of (sub-ns) reset pulses with 50 intermediate states. Our unique scheme allows fine-tuning the resistance with sub-ns pulses of constant amplitude, which can significantly reduce the programming complexity in training neuromorphic hardware. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is one of the leading candidates for neuromorphic hardware and has recently matured as a storage class memory. Yet, energy and power consumption remain key challenges for this technology because part of the PCM device must be self‐heated to its melting temperature during reset. Here, it is shown that this reset energy can be reduced by nearly two orders of magnitude by minimizing the pulse width. A high‐speed measurement setup is utilized to probe the energy consumption in PCM cells with varying pulse width (0.3–40 nanoseconds) and uncover the power dissipation dynamics. A key finding is that the switching power (P) remains unchanged for pulses wider than a short thermal time constant of the PCM (τth < 1 ns in 50 nm diameter device), resulting in a decrease of energy (E = P × τ) as the pulse width τ is reduced in that range. Thermal confinement during short pulses is achieved by limiting the heat diffusion time. The improved programming scheme reduces reset energy density below 0.1 nJ µm−2, over an order of magnitude lower than state‐of‐the‐art PCM, potentially changing the roadmap of future data storage technology and paving the way toward energy‐efficient neuromorphic hardware. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) devices have great potential as multilevel memory cells and artificial synapses for neuromorphic computing hardware. However, their practical use is hampered by resistance drift, a phenomenon commonly attributed to structural relaxation or electronic mechanisms primarily in the context of bulk effects. In this study, we reevaluate the electrical manifestation of resistance drift in sub-100 nm Ge 2 Sb 2 Te 5 (GST) PCM devices, focusing on the contributions of bulk vs interface effects. We employ a combination of measurement techniques to elucidate the current transport mechanism and the electrical manifestation of resistance drift. Our steady-state temperature-dependent measurements reveal that resistance in these devices is predominantly influenced by their electrical contacts, with conduction occurring through thermionic emission (Schottky) at the contacts. Additionally, temporal current-voltage characterization allows us to link the resistance drift to a time-dependent increase in the Schottky barrier height. These findings provide valuable insights, pinpointing the primary contributor to resistance drift in PCM devices: the Schottky barrier height for hole injection at the interface. This underscores the significance of contacts (interface) in the electrical manifestation of drift in PCM devices.