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This paper presents a bonding-less 5 GHz radio frequency identification (RFID) tag module using an 85% downsized RFID tag chip and a 97% downsized antenna. Inductive (or magnetic) coupling between the antenna and the chip realizes low cost bonding-less implementation. Compared with a conventional module operating in the UHF band, the proposed module operating in the 5 GHz range is downsized in terms of both the chip and the antenna sizes. The experimental results confirmed that the proposed RFID tag module successfully works at 20 cm away from a reader whose output power is 15 dBm, achieving the same figure of merit as a conventionally bonded module. Moreover, this paper confirmed that the misalignment tolerance of the inductive coupling can be up to 50 μ m. [ABSTRACT FROM AUTHOR]

A 6 Gb/s 9.8 pJ/b rotatable non-contact connector applicable to industrial robot arms is developed. The proposed non-contact connector enables a high-speed and highly reliable wireless data connection between three-dimensional (3-D) cameras and an edge computer in an autonomously controlled robot. A rotatable transmission line coupler (RTLC) is proposed to accommodate the rotational operation of the robot arm. Since the proposed doughnut-shaped RTLC has a constant overlapped area at any rotation angle, the RTLC has a constant coupling gain at all rotation angles. To remove inter-symbol interference (ISI) occurring at a specific rotation angle, a pulse-equalizing receiver is also developed. An interface bridge IC is proposed to transfer a wide range of interface signals from a slow-control signal such as the control area network (CAN) to a high-speed video interface signal. A signal protocol conversion technique applying on-off keying (OOK) modulation is also developed in order to transfer slow legacy interfaces used in the robot arms that include a dc component. Experiments with a test chip fabricated in a 40 nm CMOS process confirmed that bit error rate (BER) was lower than 10 $^{-12}$ at any rotation angle in a communication distance of 3 mm. The proposed system improves energy efficiency by a factor of 3.7, area efficiency by a factor of 1.8. [ABSTRACT FROM AUTHOR]

H2 and NH3 detection with low power consumption was demonstrated by integrated chemiresistive Pt and PtRh nanosheet sensors on glass substrates. The self-heating effects realized low power and local heating of metal nanosheet sensors, enabling the integration of sensors with different operating temperatures. Based on different resistance changes in Pt and PtRh nanosheets toward H2 and NH3, the concentration of each gas was detected from a gas mixture by consuming around 1-mW power. For decreasing the power consumption and further integration of sensors, sensor scaling and pulsed operations were numerically and experimentally studied. In addition to good connectivity of metal nanosheet sensors to large-scale integration (LSI) circuits, improvements of the power consumption by sensor scaling were proven. The pulsed operations required for integrated sensor arrays maintained a sensor response, or a resistance change, of approximately 60%, even when the power consumption was reduced by 20%. [ABSTRACT FROM AUTHOR]

QUEST is a programmable multiple instruction, multiple data (MIMD) parallel accelerator for general-purpose state-of-the-art deep neural networks (DNNs). It features die-to-die stacking with three-cycle latency, 28.8 GB/s, 96 MB, and eight SRAMs using an inductive coupling technology called the ThruChip interface (TCI). By stacking the SRAMs instead of DRAMs, lower memory access latency and simpler hardware are expected. This facilitates in balancing the memory capacity, latency, and bandwidth, all of which are in demand by cutting-edge DNNs at a high level. QUEST also introduces log-quantized programmable bit-precision processing for achieving faster (larger) DNN computation (size) in a 3-D module. It can sustain higher recognition accuracy at a lower bitwidth region compared to linear quantization. The prototype QUEST chip is integrated in the 40-nm CMOS technology, and it achieves 7.49 tera operations per second (TOPS) peak performance in binary precision, and 1.96 TOPS in 4-bit precision at 300-MHz clock. [ABSTRACT FROM AUTHOR]

A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted. [ABSTRACT FROM AUTHOR]

A non-contact interface for modular smartphones that can provide a data connection at a maximum MIPI rate of 6 Gb/s has been developed. A two-fold transmission line coupler, which is a small-size coupler that has a wide bandwidth, is proposed for modular smartphones, where the layout area is strictly limited. The coupler size is 6 mm2 for a 5 mm communication distance, which is 1/24 smaller than the conventional coupler. Since many wireless communication components, such as LTE, WiFi, and GPS transceivers, are assembled in a small module, the interference between the non-contact interface and the wireless transceivers should be suppressed. To improve noise immunity and reduce unwanted radiation from the coupler, an electromagnetic-compatibility robust pulse transceiver is proposed. A synchronous receiver using an edge counting clock recovery circuit improves noise immunity, and a bi-phase pulse transmitter reduces noise radiation in the GPS band. There is no EMS by LTE or WiFi signals on the data connection at BER < 10^-12 when the coupler is separated by a distance of 2 mm and no EMI on GPS signals at a separation of 10 mm. Compared with the state-of-the-art result, the highest energy efficiency (6 pJ/b) and space efficiency (1.2 \textmm^2/1 \textmm distance) is achieved. [ABSTRACT FROM PUBLISHER]

A highly reliable wireless solid-state drive (SSD) system for future applications of large volume storage is presented. The wireless interface in the system consists of an inductively coupled power link with fast transmission power control and high-speed data links using transmission line couplers (TLCs). The wireless power link can deliver 1 W from the host to the SSD. The full duplex wireless data interface achieves raw data rate of 1.6 Gb/s. The reliability of the wireless interface is studied though simulation analysis and experiments. The error correction block for the NAND flash memory system can also correct errors in the wireless data links, allowing the requirements for the PHY layer to be relaxed. The error correction code is discussed, including optimization by analyzing the error bits on the wireless data links. The experimental results confirmed strong tolerance to the interference from the power link on the wireless data link, and the water proof property of both the data and power links. [ABSTRACT FROM PUBLISHER]

Wireless 3-D network-on-chips (NoCs) with inductive-coupling ThruChip interfaces provide a large degree of flexibility for customizing the number of arbitrary chips in a package after chips have been fabricated. To simplify the vertical communication interfaces, static time division multiple access (TDMA) is used for the vertical broadcast buses, while arbitrary or customized topologies can be used for the intrachip network. This paper proposes two techniques to break through the simple static TDMA-based vertical buses while maintaining a simple communication interface. The first technique is headfirst sliding (HS) routing to reduce the waiting time for acquiring the communication time-slot. HS routing selects the best vertical bus based on the current time, taking advantage of static TDMA. The second technique extends carrier sense multiple access with collision detection (CSMA/CD) for vertical broadcast buses. We introduce a packet collision detection technique for inductive-coupling buses and propose two retransmission strategies to reduce the waiting time for packet retransmissions caused by collisions. Network simulation results show that HS routing reduces the communication latency by 39.1% compared with the conventional static TDMA bus-based 3-D NoC that uses the shortest path routing. The proposed CSMA/CD bus also improves the latency by 52.5% and throughput by 34.1%. The full-system simulation results show that HS routing and the proposed CSMA/CD technique reduce the application execution time accordingly while maintaining the average flit transfer energy overhead modest. [ABSTRACT FROM AUTHOR]

A blind source separation (BSS) is proposed to reject the crosstalk between inductive-coupling channels in 3-D systems. The phase and permutation ambiguities inherent to BSS are compensated for in the proposed technique. A continuous-time natural gradient BSS with integrator output swing bounding, which is amenable for high-speed implementation, is also proposed. Techniques to reduce the implementation complexity for a large channel array are presented. The proposed technique shows substantial improvement results for crosstalk rejection in a high-crosstalk-coupling environment. In addition, for a 3 \times 3 array channel with 1 Gb/s/channel, with a crosstalk-to-signal ratio of -3 dB, a bit-error rate of 10^-11 is obtained compared to 10^-4 without BSS. [ABSTRACT FROM PUBLISHER]

A 0.3–0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V. [ABSTRACT FROM PUBLISHER]

A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips. [ABSTRACT FROM PUBLISHER]

An introduction is presented in which the editor discusses various papers presented at the Institute of Electrical and Electronics Engineers (IEEE) International Solid-State Circuits Conference held in California on February 17–21, 2013 on topics such as sensors, digital circuits, and transistors.

A noncontact and housing-less thin–thick connecting method was developed for mobile industry processor interface (MIPI) applications. This paper describes the world's first 0.15-mm-thick connector using a vertical directional coupler (VDC) which enables simultaneous two-link communication with one coupler without fatal performance degradation. We have analyzed the conditions for isolating two links in a coupler, and the design method is discussed. A fully balanced pulse transmitter implemented in 90-nm CMOS technology significantly suppressed electromagnetic interference (EMI), which agrees well with MIPI requirements. An experimental liquid crystal display interface system reached a maximum data rate of 2.3 Gb/s/link at a bit error rate of less than 10^-12 and a power consumption of 1.47~pJ/b. The timing margin of single link was 320 ps (=64% U.I.) and of two links was 305 ps (=61% U.I.) at 2.0 Gb/s. [ABSTRACT FROM AUTHOR]

The authors developed a scalable heterogeneous multicore processor. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-offs between performance and energy consumption. The stacked chips interconnect through a scalable 3D network on a chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. No design change is needed, and hence, no additional nonrecurring engineering (NRE) cost is required. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. The authors developed a prototype system called Cube-1 with 65-nm CMOS test chips, and confirmed successful system operations, including 10 hours of continuous Linux OS operation. Simple filters and a streaming application were implemented on Cube-1 and performance acceleration up to about three times was achieved. [ABSTRACT FROM PUBLISHER]

This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (HVt) and low threshold voltage (LVt), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS process has successfully reduced leakage power by 98%, and it achieves 8.2-bit ENOB and while consuming only 650 pW at 0.1 kS/s from 0.5-V power supply. The power consumption is scalable up to 4 MS/s and power supply range from 0.4 to 0.7 V. The best figure of merit at 0.5 V is 5.2 fJ/conversion-step at 20 kS/s. [ABSTRACT FROM AUTHOR]

This paper presents a high data rate, non-contact interface using a coupled transmission line (CTL) composed of two differential transmission lines. The proposed CTL can achieve a measured loss of -13.4 dB and a 3-db bandwidth of 3.4–9.0 GHz as a non-contact channel for a 1-mm communication distance. This wideband characteristic makes it possible to achieve high-speed communication using a single channel. The hysteresis buffer-based receiver recovers the transmitted data from the distorted waveforms derived from the AC coupling characteristics of the channel. The interference from the power delivery coil to the CTL is also evaluated. The simulated results showed that the interference was less than -57.8 dB at 13.56 MHz. The system could achieve a communication speed of 12 Gb/s with a BER < 10^-12 at a communication distance of 1 mm both with and without a wireless power supply of 75 mArms. The timing margin with the wireless power supply was 41 ps (=0.49 UI). [ABSTRACT FROM PUBLISHER]

In this paper, we describe a noncontact inductive-coupling data transmission link employing rotary data encoding. A system using this data-transmission link is inherently insensitive to jitter introduced in the channel and consumes approximately 50% less power than previously reported solutions. The system is targeted for applications benefiting from simultaneous noncontact power and data transmission, such as wafer-level testing, memory card interfaces, and inter-strata data communication in 3-D integrated circuits. Functionality of the proposed link is verified experimentally with a test chip developed in an 0.18-\mu \m CMOS process. In the second part of this paper, we introduce a design of a high-speed data transceiver using rotary coding. We demonstrate that, because of properties of the rotary coding, a simple transceiver without a PLL-based CDR circuit can operate at data rates limited only by characteristics of the physical channel. For performance optimization, we have developed a new family of ternary logic gates including latches, D-flip-flops, and multiplexers. [ABSTRACT FROM PUBLISHER]

This paper presents SD-card-size wireless power transfer system for large-volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc–dc converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-\mum-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 \mu\s. [ABSTRACT FROM PUBLISHER]

A 0.025–0.45 W inductive-coupling power transceiver for non-contact memory applications is presented. To deal with sudden and large load variations and achieve high-efficiency, we propose a power transceiver with 5-bit feedforward control. Knowing that load patterns of a memory card have strong correlation with commands issued by a host, feedforward control is applied to minimize response times. To achieve 5-bit power levels, the proposed transceiver utilizes pulse-density modulation (PDM) and a multi-channel structure. Different operation frequencies are chosen for each channel to maximize power transfer efficiency. To further improve transceiver efficiency and enable high-speed operation, an active rectifier with a fast positive feedback is proposed. The test prototype demonstrates 40%–70% efficiency across all load conditions and 60% efficiency in average, which are over an order of magnitude improvements compared to prior arts. [ABSTRACT FROM AUTHOR]

An inductive power and data transmission link for a noncontact memory card interface is reported. Nested clover coils improve signal-to-interference ratio and enable simultaneous power and data transmission. This capability is then used in the design of a closed-loop feedback system for improving power transfer efficiency. Interference cancellation mechanism is analyzed with both 3-D EM simulations and a newly developed compact model of coupled inductors. Performance of the proposed solutions was confirmed experimentally using a scaled-down stacked-chip prototype fabricated in a 65-nm CMOS process. Maximum data transmission rate is 6 Gb/s and the total power transfer efficiency is 5.2%–10.2% over a load resistance range of 0.1–2 k\Omega. [ABSTRACT FROM AUTHOR]

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision. [ABSTRACT FROM PUBLISHER]

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160\ \mu\m \times 70\ \mu\m. [ABSTRACT FROM PUBLISHER]

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-\mum mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 \mum, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, -101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated. [ABSTRACT FROM PUBLISHER]

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated. [ABSTRACT FROM AUTHOR]

This paper presents a 30 Gb/s/link 2.2 Tb/s/mm^2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm^2, which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link. [ABSTRACT FROM PUBLISHER]

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2~V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate <10^-12, are achieved at 0.55 V and 0.7 V supply voltage, respectively. [ABSTRACT FROM AUTHOR]

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 \mu\ m \times \,100 \mu\ m). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution. [ABSTRACT FROM PUBLISHER]

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions. [ABSTRACT FROM AUTHOR]

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm²/Gbps, respectively, which are the same as those of two-chip integration. [ABSTRACT FROM AUTHOR]

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 μm CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8. [ABSTRACT FROM AUTHOR]

A high-speed inductive-coupling link is presented. It communicates at a data rate of 11 Gb/s for a communication distance of 15 μm in 180 nm CMOS. The data rate is II x higher than previous inductive-coupling links. The communication distance is 5 x longer than a capacitive-coupling link for the same data rate, bit error rate, and layout area. Burst transmission utilizing the high-speed inductive-coupling link is also presented. Multi-bit data links are multiplexed into a single burst data link. It reduces layout area by a factor of three in 180 nm CMOS and a factor of nine in 90 nm CMOS. [ABSTRACT FROM AUTHOR]

This paper presents a novel impulse radio based ultra-wideband transmitter. The transmitter is designed in 0.18 μm CMOS process realizing extremely low complexity and low power. It exploits the 6-to-10 GHz band to generate short duration bi-phase modulated UWB pulses with a center frequency of 8 GHz. No additional RF filtering circuits are required since the pulse generator circuit itself has the functionality of pulse shaping. Generated pulses comply with the FCC spectral emission mask. Measured results show that the transmitter consumes 12 pJ/b to achieve a maximum pulse repetition rate of 750 Mb/s. An optional embedded on-chip antenna and a power amplifier operating in 6-10 GHz band are also designed and investigated as a future low cost solution for very short distance IR-UWB communications. [ABSTRACT FROM AUTHOR]

A 2 Gb/s bi-directional inter-chip data transceiver is experimentally demonstrated for the first time in 180 nm CMOS technology. Two orthogonal differential inductor pairs are vertically overlapped to make a bi-directional channel. Using these channels, bi-directional communication system is established without any complex circuit techniques. The crosstalk interference problem in channel array is also considered. Differential inductors, due to their noise immunity can make shorter pitches possible in channel array. Compared with the data link with conventional inductor array, this proposed technique achieves 64% area reduction with the same speed. [ABSTRACT FROM AUTHOR]

Quadrature injection-locked LC dividers with either a Miller topology or an injection-locked LC VCO topology are coupled with transconductors to enhance their locking range. The effect of the transconductance coupling is analyzed theoretically and through circuit simulation. Both topologies were fabricated by 90-nm CMOS technology with a target input center frequency of 20 GHz and output frequency of 10 GHz. The measured locking range for the Miller topology with transconductance coupling is 25.3%, compared to 20.9% without coupling. The measured locking range for the injection-locked LC VCO topology with transconductance coupling is 18.1%, compared to 12.9% without coupling. Moreover, power consumption for both dividers is 6.4 mW with a 1.2-V supply. [ABSTRACT FROM AUTHOR]

A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the transmitter energy is 0.11 pJ/b. Due to device scaling from 180 nm CMOS to 90 nm CMOS, the receiver energy is 0.03 pJ/b. The overall energy dissipation is 20X lower than previous work, without degrading the data rate of 1 Gb/s. [ABSTRACT FROM AUTHOR]

A 0.79-mm² 29-mW real-time face detection core is fabricated in a 0.13-μm CMOS technology. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The core can detect eight faces in each frame of moving pictures at 30 frames/second. Face detection accuracy is 92%. [ABSTRACT FROM AUTHOR]

Inductive coupling among stacked chips in a package enables 1 Gb/s/channel data communications. Array arrangement of the channel increases data bandwidth, while signal may be degraded by crosstalk. In this paper, crosstalk is measured and analyzed, and crosstalk countermeasures are discussed. Received signal waveforms through the inductive coupling are measured by embedded voltage detectors on a test chip. Interference-to-signal ratio (ISR) has good agreement between the measurements and calculations. It is found that crosstalk is reduced negligibly at a certain distance. If the channels are arranged at intervals of this distance, ISR is minimized. A technique based on time interleaving is also proposed to further reduce crosstalk. A 3 × 17 channel array is implemented with the crosstalk countermeasures. The channel pitch is taken down to 50 μm. Inter-chip communication with data rate of 1 Gb/s/channel and bit error rate (BER) lower than 10-9 is demonstrated. [ABSTRACT FROM AUTHOR]

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 µm in a layout area of 1 mm². The total layout area including 16 clock transceivers is 2 mm² in 0.18 µm CMOS and the chip thickness is reduced to 10 µm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13. [ABSTRACT FROM AUTHOR]

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-µm CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of ±2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10-3. For ranging applications, the transmitter can reduce the power to 0.7 µW for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 µV/m, and thus the UWB system can be operated even under the current Japan radio regulations. [ABSTRACT FROM AUTHOR]

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2 W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-μm pitch in 0.25-μm CMOS technology. By thinning chip thickness to 10 μm, the interface communicates at distance of 15 μm at minimum and 43 μm at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk. [ABSTRACT FROM AUTHOR]

A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10-12 by laboratory measurements. [ABSTRACT FROM AUTHOR]

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-µm CMOS technology. The receiver active area is 0.8 mm² and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10-12. The areas and power consumptions are 47 µm × 85 µm and 13.2 mW for the equalizer, and 145 µm × 80 pm and 10 mW for the ISI monitor. [ABSTRACT FROM AUTHOR]

A wireless bus for stacked chips was development by utilizing inductive coupling among then inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive are designed for inductive nonreturn-to-zero where no signal is transmitted when data remains the same. At test chip was fabricated in 0.35-μm CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 42 and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 μm in 90-nm device generation,power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm2. [ABSTRACT FROM AUTHOR]

Power dissipation of CMOS integrated circuits continues to increase as a result of device scaling. In this paper circuit design techniques for high-speed low-power CMOS VLSIs for multimedia applications are reviewed. In addition to general guidelines for low-power design and a summary of recent research, we discuss in detail some of the recent research achievements including low-voltage circuits such as MTCMOS and VTCMOS, and low-capacitance circuits such as pass-transistor logic circuits. © 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(9): 67–74, 1998 [ABSTRACT FROM AUTHOR]