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A compact nonquasi-static (NQS) MOSFET model is presented that incorporates the carrier-response delay mechanisms influencing the formation of carriers in the channel. The model predicts the correct transient terminal currents and achieves a stable circuit simulation.

A completely surface-potential-based compact model for a fully depleted SOI-MOSFET, called the Hiroshima University semiconductor technology academic research center IGFET model silicon-on-insulator (HiSIM-SOI) is reported. The HiSIM-SOI is verified to reproduce measured I-V characteristics as also 1/f noise data of a 250-nm fully depleted SOI technology, while the stable convergence of HiSIM-SOI in the circuit simulation is confirmed.

The Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) is a complete MOSFET model for advanced technologies based on the surface potential concept. It is suited for accurate RF circuit simulation, enabling high accuracy and a reduced number of model parameters.

Nonplanar polyoxide electrical/thermal properties and the effects on EEPROM operations are examined.

The current status of research in the field of power semiconductor device models is reviewed. For this purpose, the basic modeling problems and research issues, which have to be overcome in this field, are discussed. Recently, some new and quite promising modeling concepts have been proposed, which are compared with more traditional ways of achieving an efficient tradeoff between the necessary accuracy, required simulation speed, and feasibility of parameter determination. From this comparison, a prediction of the future evolution of circuit simulation models for power semiconductor devices naturally emerges. Many of the different concepts are expected to survive only in an application niche, where their specific points of strength are important. However, three modeling concepts have already been proven to be successfully applicable to the complete spectrum of power semiconductor devices and have their strength for different grades of complexity of the power circuit. A revolutionary development from anticipated or long-due breakthroughs is on the other hand not expected in the foreseeable future. Index Terms - CAD, circuit simulation, modeling, parameter extraction, power semiconductor devices.

Power dissipation of on-chip cache memories contributes a large portion of a processor’s power consumption. Therefore, power management of cache memories is crucial in modern processors. On the other hand, bias temperature instability (BTI) is one of the most serious reliability concerns in SRAM-based on-chip memories. The effect of BTI on SRAM-cell transistors is manifested as their threshold-voltage shift over stress duration, which decreases the robustness of these structures. This paper presents a power consumption-reduction technique for data-cache memories, based on a storage management considering narrow-width values (NWVs), which additionally mitigates the BTI rate on the most aging susceptible SRAM cells of data-cache memory, as well. In the proposed technique, the most significant bits of data-cache memory words are stored in SRAM blocks that operate with lower $V_{\mathrm {DD}}$ , to achieve the decrease of the related power consumption and aging rate. This is shown to reduce leakage-current and dynamic current of data-cache memory by 37.6% and 22.1%, respectively, besides improving its lifetime by up to 2.25x, all with negligible performance and area overheads. [ABSTRACT FROM AUTHOR]

The additional implanted channel-dopant layer of depletion-mode (DM) MOSFETs induces, at the same time, two main currents, namely, an accumulation current at the channel surface and a neutral-region current flowing deep in the implanted buried layer. In particular, the neutral-region current causes the normally-on condition of DM MOSFETs. These two currents dominate drain–source current alternatively depending on the bias conditions. To model the measured features of a DM MOSFET, a compact model is developed by considering also the complete vertical potential distribution from the surface to the bottom of the additional implanted channel-dopant layer. The potential distribution is self-consistently obtained by solving the Poisson equation. It is further demonstrated that a major development task is the correct coupling between Vds and Vbs contributions, which is needed to describe the specific features of the DM MOSFET accurately. [ABSTRACT FROM AUTHOR]

Many computer-vision and machine-learning applications in robotics, mobile, wearable devices, and automotive domains are constrained by their real-time performance requirements. This paper reports a dual-feature-based object recognition coprocessor that exploits both histogram of oriented gradient (HOG) and Haar-like descriptors with a cell-based parallel sliding-window recognition mechanism. The feature extraction circuitry for HOG and Haar-like descriptors is implemented by a pixel-based pipelined architecture, which synchronizes to the pixel frequency from the image sensor. After extracting each cell feature vector, a cell-based sliding window scheme enables parallelized recognition for all windows, which contain this cell. The nearest neighbor search classifier is, respectively, applied to the HOG and Haar-like feature space. The complementary aspects of the two feature domains enable a hardware-friendly implementation of the binary classification for pedestrian detection with improved accuracy. A proof-of-concept prototype chip fabricated in a 65-nm SOI CMOS, having thin gate oxide and buried oxide layers (SOTB CMOS), with 3.22-mm2 core area achieves an energy efficiency of 1.52 nJ/pixel and a processing speed of 30 fps for $1024\times 1616$ -pixel image frames at 200-MHz recognition working frequency and 1-V supply voltage. Furthermore, multiple chips can implement image scaling, since the designed chip has image-size flexibility attributable to the pixel-based architecture. [ABSTRACT FROM AUTHOR]

Object recognition offers a more general implementation for vision-based applications. This paper reports a resource-efficient recognition coprocessor with embedded cell-based simplified speeded up robust feature descriptor extraction unit and parallel scan-window (SW) recognition engine, applicable for various mobile scenarios and image sensor types. The feature extraction circuitry with pixel-based pipelined architecture describes the target objects among complex backgrounds, only relying on the pixel frequency from the image sensor. A cell-based SW algorithm enables parallelized recognition in multiple SWs and compatibility to different image sizes. The proposed hardware-friendly object-recognition coprocessor was implemented in 65-nm Silicon on thin BOX CMOS technology with 1.26 mm2 core area and can operate down to low supply voltage of 0.5 V. For video graphics array image sizes, the energy efficiency is determined as 910~\mu \textJ per frame at 200 MHz and 1-V supply voltage. The coprocessor’s classification performance is demonstrated for pedestrian and car detection. [ABSTRACT FROM AUTHOR]

An investigation of the carrier trapping influence on device characteristics in poly-Si thin-film transistors (TFTs) is reported. Particular focus is laid on the transient characteristics, which is influenced by the carrier trapping during the device operation. On the basis of these features, a compact model for TFT-circuit simulation has been developed, which considers the dynamically changing time constant of the carrier trapping in the framework of a complete surface-potential description, thus enabling modeling the dynamically varying trapped carrier density. The compact model is verified against measured characteristics of repeated switching. [ABSTRACT FROM AUTHOR]

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (Vth) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (Eox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted. [ABSTRACT FROM PUBLISHER]

The reported compact SOI-MOSFET model hiroshima university starc igfet model-silicon on thin buried oxide (HiSIM-SOTB) has been developed for devices with ultrathin silicon on insulator (SOI) and buried oxide (BOX) layers. The potential distribution determined by the Poisson equation is accurately solved with the Newton iteration method across the SOI layer and in the substrate on the backside of the BOX for source and drain side of the device. All charges including accumulation and inversion charges on both side of the BOX are explicitly considered in the Poisson equation. It is found that different from the double-gate MOSFET, the influence of the impurity concentration of the bulk substrate below the BOX must be also explicitly considered to capture all measured properties of the silicon on thin buried oxide (SOTB) MOSFET. A further modeling challenge of the thin SOI and BOX layers, which had to be overcome, is that charge neutrality is not independently preserved at the front-gate oxide or at BOX side, but only totally within the whole device. Additionally it is found that, due to the consistent potential- and charge-based model formulation, the developed HiSIM-SOTB model can reproduce not only TCAD and measured SOTB device data but is even capable to predict the effects of structural variations, including the limiting case of the double-gate MOSFET structure. [ABSTRACT FROM PUBLISHER]

Examines the electrical passivation of leakage currents through thermally grown oxides on polycrystalline silicon. Importance of electrical passivation in integrated circuits; Effect of electrons trapped at neutral oxide trapping sites on passivation; Determination of the thermal activation energies for passivation removal.