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AlGaN channel (Eg>3.4 eV) is the most effective method for enhancing the breakdown field of the group IIInitride based HEMTs. This work demonstrates the potential of AlGaN double channel HEMTs on Silicon carbide substrate. The device DC characteristics are investigated using numerical simulator by using drift-diffusion transport model. The AlGaN double channel HEMTs enhances the total 2DEG density due to double potential well and shows better current driving capability (IDS) of 0.714 A/mm, transconductance (gm) of 116 mS/mm, and low specific ON-resistance (Ron) of 3.262 Ω.mm. The AlGaN double channel HEMT on Silicon carbide substrate exhibited 680 V blocking voltage (VBR) and gate field plate HEMT shows 532 V. The effective reduction in electric field at the gate edge is the major source for elevated breakdown voltage in field plate HEMTs. The superior DC characteristics indicates the proposed wide bandgap channel HEMT is suitable device for future portable power converters. [ABSTRACT FROM AUTHOR]

The Huang-Pair is a novel hybrid diode concept based on the integration of a low forward voltage drop, low voltage rating diode with a high voltage majority carrier switch, such as a silicon carbide (SiC) Junction gate field-effect transistor (JFET). A 1200 V Huang-Pair is developed to demonstrate the concept in which a low voltage Si diode is paired with a 1200 V SiC JEFT, resulting in a low-forward voltage, low reverse recovery high voltage diode. The Huang-Pair is a two terminal device and its performance tradeoff between forward voltage drop, leakage current, and reverse recovery can be conducted between two discrete devices, which is more flexible. The Huang-Pair concept can also be realized by SiC MOSFET and gallium nitride MOSFET, and it can be applied to different voltage classes. [ABSTRACT FROM AUTHOR]

In this paper, a dual-gate laterally double-diffused metal–oxide–semiconductor (DG-LDMOS) device with shallow trench isolation (STI) and sinker at the source side has been proposed. STI and sinker help to provide isolation and reduce the leakage current, respectively, in the device. This is an improvement over a single-gate (SG) LDMOS device when only one gate is used and no STI and sinker are there. The study of both the devices has been carried out using the ATLAS SILVACO simulator. In the simulation studies, all the dimensions and doping parameters of both devices have been kept the same except gate length and channel doping. The distance between two gates of DG-LDMOS device has been kept smaller. This has been done to overcome the island and overlapping issues. The simulation studies have shown a significant improvement in DG-LDMOS device parameters in comparison to the SG-LDMOS device. The DG-LDMOS device provides high breakdown voltage, low ON-resistance, high $f_{\sf {T}}$ and $f_{\sf {max}}$ , low drain-induced barrier lowering, and better output conductance as compared to conventional SG-LDMOS device. These features make the DG-LDMOS device an excellent candidate for RF applications. [ABSTRACT FROM AUTHOR]

Very fast transients of V {\text {TH}} shift and their impact on R\mathrm{\scriptscriptstyle ON} under dynamic AC (1 k–1 MHz) positive gate stress in depletion-mode (D-mode) metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) are revealed. We achieve data acquisition within 120 ns right after each stress pulse throughout the entire stress time range from 10^ -7 up to 10^ 3 s, by virtue of a short stress-to-sense delay of \sim 100 ns and high sampling rate up to 50 MSa/s. Despite the considerable V_{\mathrm {\mathbf {TH}}} shift, its impact on R\mathrm{\scriptscriptstyle ON} in D-mode MIS-HEMT is modest, if the device is under sufficient gate overdrive. Furthermore, V_{\mathrm {\mathbf {TH}}}$ shift and the consequent R\mathrm{\scriptscriptstyle ON} increase under dynamic stress, which are more relevant to high-frequency switching operation, exhibits frequency dependence within 1 k–1 MHz and is always smaller than that under conventionally used static (constant) stress. [ABSTRACT FROM PUBLISHER]

The operation of traditional rectifiers such as half-wave and bridge rectifiers in wireless power transfer applications may be inefficient and can reduce the amount of power that is delivered to a load. An alternative is to use Class E resonant rectifiers that are known to operate efficiently at high resonant frequencies and at large input voltages. Class E rectifiers have a near sinusoidal input current which leads to an improved overall system performance and increased efficiency, especially that of the transmitting coil driver. This paper is the first to investigate the use of Class E resonant rectifiers in wireless power transfer systems based on resonant inductive coupling. A piecewise linear state-space representation is used to model the Class E rectifier including the rectifying diode's forward voltage drop, its ON resistance, and the equivalent series resistance of the resonant inductor. Power quality parameters, such as power factor and total harmonic distortion, are calculated for different loading conditions. Extensive experimental results based on a 10-W prototype are presented to confirm the performed analysis and the efficient operation of the rectifier. An impressive operating efficiency of 94.43% has been achieved at a resonant frequency of 800 kHz. [ABSTRACT FROM AUTHOR]

ABSTRACT In this work, we analyzed the efficiency of a switching-mode RF CMOS power amplifier with the following design parameters: the on resistance and the parasitic capacitance of the power transistor. The power amplifier is composed of a class-D type driver stage and a class-E type power stage. The power consumption of the driver stage, the load impedance of the power stage, and the loss of the output matching networks are considered for a numerical analysis. We investigated the normalized drain efficiency according to the variable supply voltage of the power stage for polar transmitter applications. From the simulated results of the power amplifier, we successfully proved the feasibility of using the numerical analysis. The designed power amplifier is implemented using 0.13 μm RF CMOS process to verify the numerical results by means of an experiment. A distributed active transformer is used for an output matching network. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:110-117, 2014 [ABSTRACT FROM AUTHOR]

A silicon-on-insulator (SOI) CMOS technology on high-resistivity silicon substrates is presented for the design of high-power switches for cellular and wireless local area network handset applications. A design methodology is introduced to design high-order switches for optimal insertion loss and isolation performance. Sources of nonlinearities in SOI switches are discussed. To the best of our knowledge, this work is the first demonstration of high-power switches on a high-resistivity SOI CMOS technology for high-volume cellular handset applications with adequate intermodulation and harmonic distortion performance. The design details and measurement results for a variety of RF switches with general-purpose input/output and mobile industry processor interface control interfaces, flip-chip/wire-bond packaging, and for various standards are discussed. [ABSTRACT FROM PUBLISHER]

In this paper, the effects of limited drain current and transistor's on resistancee on the performance of an LDMOS inverse class-E power amplifier (PA) are analyzed using a simplified transistor model of piecewise linear dc I-V curves. The minimal magnitude of driving signal, the maximal voltage gain, and the maximal output power of an inverse class-E PA can be defined with the maximal drain kept. The theoretical and simulated results of amplifier performance, such as drain efficiency and output voltage, are compared to verify the analysis, and the nonlinear relation among the drain dc supply voltage, input/output voltage, and phase of an inverse class-E PA caused by limited drain current are presented. The effects on the amplifier performance are further verified by the measured results of a 945-MHz transmission-line inverse class-E amplifier in comparison with the corresponding theoretical and simulated results. [ABSTRACT FROM AUTHOR]

Designing and fabrication of 4H-SiC (0001) lateral MOSFETs with a double reduced surface field (RESURF) structure have been investigated to reduce ON resistance. In order to achieve high breakdown voltage, a two-zone RESURF structure was also employed in addition to the double RESURF structure. The simulated double RESURF MOSFETs with optimum doses exhibit slightly higher breakdown voltage and lower drift resistance than the simulated single RESURF MOSFETs. The double RESURF structure is attractive to suppress oxide breakdown at gate edge. After the device simulation for dose optimization, the 4H-SiC two-zone double RESURF MOSFETs have been fabricated by using a self-aligned process. The fabricated MOSFET has demonstrated a high breakdown voltage of 1380 V and a low ON resistance of 66 mΩ · cm² (including a drift resistance of 24 mΩ · cm²). The drift resistance of the fabricated double RESURF MOSFETs is only 50% or even lower than that of the single RESURF MOSFETs. [ABSTRACT FROM AUTHOR]

Abstract: The nm-range abrupt doping profiles in SiC epitaxial layers are stable even after the high temperature process because SiC crystal exhibits little diffusion of impurities. Growth of the SiC delta-doped layers have been reported by our group and the others. We believe that the well-designed delta-doped epitaxial layers for the FET channels extend possibility of the power SiC FET. We proposed the SiC Delta-doped Accumulation Channel MOSFET (DACFET) consisting of the delta-doped layers for MOS channel and reported its high MOS-channel mobility. The vertical hot-wall-type CVD system was used to grow SiC epitaxial layers. The pulse valve, which supplied short (100cm2/Vs. The vertical DACFET, whose blocking voltage was >600V, was fabricated with the double-implantation MOS process. R on of the normally-off 2μm-gate DACFET was measured to be 13mΩcm2. Current density was observed to be >140Acm−2 larger than Si-IGBT. Shortening of gate length and unit cell size of the SiC-DACFET using high-resolution lithography will result in R on <7mΩcm2. [Copyright &y& Elsevier]

The differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF (reduced surface field) LDMOSFETs (lateral double‐diffused metal‐oxide‐semiconductor field‐effect transistors) are discussed in this paper. Two concise RESURF criteria for LDMOS with a low‐doped fully depleted N‐ buried layer (NBL) and a highly doped nondepleted N+ floating layer (NFL) are developed by optimizing the lateral and vertical electric fields. The analytical solution quantitatively demonstrates the variation of the drift charge concentration and its dependence on the key NBL and NFL parameters. It also indicates that the NBL LDMOS achieves a superior tradeoff between specific on‐resistance (Rs,on)and breakdown voltage (BV) to the NFL LDMOS. The BV2/Rs,on for NBL LDMOS is 3.1 MW/cm2, which is increased respectively by 93.8% and 40.9% compared with the single RESURF and NFL‐LDMOS. [ABSTRACT FROM AUTHOR]