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Datapath synthesis is a crucial step in synthesis flow and aims at globally minimizing an area by identifying shareable logic structures. This paper introduces a novel Directed Acyclic Graph (DAG)-based datapath synthesis method based on graph isomorphism and gate reconfiguration. Unlike algorithms that identify common specification logic, our approach simplifies the problem by focusing on searching for common topology. Leveraging the concept of gate reconfiguration, our algorithm extends the applicability of DAG-based datapath synthesis by transforming a topology-equivalent network into a specification-equivalent network. Experimental results demonstrate up to 23.6% improvement when optimizing the adder–subtractor circuit, a scenario not addressed by existing DAG-based datapath synthesis algorithms. [ABSTRACT FROM AUTHOR]

With the rapid development of the communication industry in the fifth generation and the advance towards the intelligent society of the sixth generation wireless networks, traditional methods are unable to meet the ever‐growing demands for higher data rates and improved quality of service. Deep learning (DL) has achieved unprecedented success in various fields such as computer vision, large language model processing, and speech recognition due to its powerful representation capabilities and computational convenience. It has also made significant progress in the communication field in meeting stringent demands and overcoming deficiencies in existing technologies. The main purpose of this article is to uncover the latest advancements in the field of DL‐based algorithm methods in the physical layer of wireless communication, introduce their potential applications in the next generation of communication mechanisms, and finally summarize the open research questions. [ABSTRACT FROM AUTHOR]

The objective of this work was to design a versatile readout circuit for patch-type wearable devices consisting of a Transimpedance Amplifier (TIA). The TIA performs Current to Voltage (I–V) conversion, the most widely used technique for amperometry and impedance measurement for various types of electrochemical sensors. The proposed readout circuit employs a digitally controllable feedback resistor ( R f ) technique in the TIA to improve accuracy, which can be utilized in a variety of electrochemical sensors within a current range of 0.1 µA–100 µA. It is designed to accommodate multiple sensors simultaneously to track multiple target analytes for high accuracy and versatile usage. The readout circuit consists of low power operational amplifier (op–amp) and digital circuit blocks, is designed and fabricated with Magna 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology, which provides low power consumption and a high degree of integration. The design has a small size of 0.282 mm 2 and low power consumption of 0.38 mW with a 3.3 V power supply, which are desirable factors in wearable device applications. [ABSTRACT FROM AUTHOR]

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of material-level characteristics to replace conventional Cu counterparts are quantified, such as the channel density, mean free path (MFP), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints. Results demonstrate that the optimal design scheme strongly depends on the power constraint, driving devices as well as material parameters, including the contact resistance. It is shown that up to 45% of the throughput improvement can be achieved by replacing both local and intermediate Cu interconnects at an ultralow-power budget. [ABSTRACT FROM AUTHOR]

As the traditional CMOS technology encounters significant scaling challenges, many emerging beyond-CMOS devices have been proposed and developed to augment or even replace CMOS devices. Spintronic devices have received extensive attention due to several unique attributes, including a low operation voltage and nonvolatility. However, spintronic devices are intrinsically slow because of the long switching delay of the magnet. To overcome the drawback, in this article, we propose and develop a deep pipeline method for generic spintronic majority-gate-based circuits. A fast and efficient pipeline buffer insertion methodology is integrated into the industry-standard placement and routing design flow to ensure the correct functionality. The proposed framework can accurately capture 1) the timing of a multiphase clock-gated spintronic circuit and 2) the energy overhead associated with the supply clocking, which is one major overhead of spintronic circuits. Based on the proposed framework, we demonstrate that a spintronic circuit implemented with a deep pipeline can provide over $10\times $ reduction in energy-delay products compared to their traditional CMOS-based counterparts. In the case study, the proposed deep pipeline method is applied to three emerging spintronic devices. Results show that device-level parameters have significant impacts on circuit-level performance and optimal logic depth. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

In this letter, we present a comprehensive performance analysis of ferroelectric (FE)-based logic gates and repeaters. In addition, we highlight the key aspects of negative capacitance FET (NCFET) characteristics, including the proper circuit initialization, the negative capacitance (NC) effect on leakage currents, and the impacts of the FE viscosity coefficient. The threshold voltage adjustment is proposed to optimize the NCFET-based devices according to the activity factor. Furthermore, we study the interconnect repeater insertions and optimize the numbers and sizes of repeaters to minimize the overall energy-delay product. The NCFET is implemented in SPICE, with FE dynamics described by the Landau-Khalatnikov equation. Our analyses with the SPICE circuit model can provide useful insights into future studies of low-power devices. [ABSTRACT FROM AUTHOR]

The advent of multigate transistor technology for 20-nm technology node and beyond, has increased the importance of wire parasitics, in particular, wire resistance in determining the circuit delay computation. Variability in wire dimensions directly impacts the wire parasitics, hence, the overall system performance. For the first time, in this paper, we study circuit variability for 11- and 7-nm technology nodes based on GDSII-level layouts. We propose novel hybrid multipatterning flows, which combine the litho-etch-litho-etch and self-aligned-spacer technologies, to reduce circuit variability induced by the lithography process. We engineer the hybrid solutions to have reduced variability in wire resistance, and circuit performance, and develop variability models for each patterning proposal. We also find the increasing need of these hybrid solutions at the 7-nm technology node. For Extreme Ultraviolet (EUV) lithography to enable higher circuit performance than the proposed patterning regimes, it requires a high precision in core variation of less than 1 nm. [ABSTRACT FROM AUTHOR]

Due to the massive parallel computing capability and outstanding image and signal processing performance, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology. The CNN was originally implemented by VLSI analog technologies with operational amplifiers and operational transconductance amplifiers as neurons and synapses, respectively, which are power and area consuming. In this paper, we propose a hybrid structure to implement the CNN with magnetic components and CMOS peripherals with a complete driving and sensing circuitry. In addition, we propose a digitally programmable magnetic synapse that can achieve both positive and negative values of the templates. After rigorous performance analyses and comparisons, optimal energy is achieved based on various design parameters, including the driving voltage and the CMOS driving size. At a comparable footprint area and operation speed, a spintronic CNN is projected to achieve about one order of magnitude energy reduction per operation compared to its CMOS counterpart. [ABSTRACT FROM PUBLISHER]

This letter presents a uniform interconnect-centric benchmark methodology for various emerging charge-based device technologies, including ferroelectric FETs, tunneling FETs, piezoelectric FET, graphene pn junction, and 2D material-based FET. Multiple key metrics are proposed and implemented to quantify the circuit/system limitations imposed by repeaters and interconnects. The results in this letter give device technologists an insightful perspective to better balance and manage the trade-offs of intrinsic device properties for the optimum interconnect performance. [ABSTRACT FROM AUTHOR]

Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance. [ABSTRACT FROM PUBLISHER]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

This paper analyzes the impact of the interconnect variation at the system level in terms of clock frequency based on a fast and efficient system-level variation-aware design methodology. Various types of interconnect variations are compared, such as the critical dimension for line/core and spacer, etch, chemical mechanical polishing (CMP), and overlay variations. The $3 \sigma $ values for these independent variation values are extracted from various fabrication processes, including the litho-etch-litho-etch (LELE) double patterning, self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP). The results indicate that the impact of the interconnect variation on the clock frequency increases for a processor at a smaller technology node, especially for the CMP variation. For the impact of the combination of five sources of interconnect variations, the processor using the SADP performs the best. The overlay variation and the spacer variation have a larger impact on the LELE double patterning and the SAQP patterning techniques. Up to 8% and 16% of the frequency drops are observed based on $1\times $ and $2\times $ of the default $3 \sigma $ values, respectively. [ABSTRACT FROM PUBLISHER]

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness. [ABSTRACT FROM AUTHOR]

Optimal operation of energy storage systems plays an important role in enhancing their lifetime and efficiency. This paper combines the concepts of the cyber–physical system (CPS) and multi-objective optimization into the control structure of the hybrid energy storage system (HESS). Owing to the time-varying characteristics of HESS, combining real-time data with physical models via CPS can significantly promote the performance of HESS. The multi-objective optimization model designed in this paper can improve the utilization of supercapacitors, reduce energy consumption, and prevent the state of charge (SOC) of HESS from exceeding the limitation. The new control scheme takes the characteristics of the components of HESS into account and is beneficial in reducing battery short-term power cycling and high discharge currents. The rain-flow counting algorithm is applied for battery life prediction to quantify the benefits of the HESS under the control scheme proposed. A much better power-sharing relationship between the supercapacitor and the lithium–ion battery (LiB) can be observed from the SIMULINK results and the case study with our new control scheme. Moreover, compared to the traditional low-pass filter control method, the battery lifetime is quantifiably increased from 3.51 years to 10.20 years while the energy efficiency is improved by 1.56%. [ABSTRACT FROM AUTHOR]

As the technology scales down to the sub-10 nm nodes, the interconnect performance becomes primarily dominated by the resistance rather than the capacitance due to the ever-increasing size effects of copper and a higher input capacitance of the devices. The implications of this paradigm shift are discussed in this letter, and it is shown that the local interconnect technology needs to be reoptimized to rebalance the interconnect resistance and capacitance. One approach is to increase the interconnect width beyond half pitch without changing the interconnect pitch. For the 5-nm technology node with an aspect ratio of 3, the energy-delay product of vertical field-effect transistor circuits at the optimal relative width improve up 55%, compared with the circuits using an aspect ratio of 2 and an interconnect width of half pitch. [ABSTRACT FROM AUTHOR]

To suppress the impact of size effects on sub-20 nm wide wires, a novel aluminum-copper hybrid interconnect architecture is proposed and its potential performance has been quantified. Al wires offer lower resistivities at nanoscale dimensions because they do not need diffusion barriers, and size effects are less prominent in them due to their smaller bulk mean free path. However, their current conduction capacity is substantially lower than that of Cu wires. To get around this limitation, this letter proposes a hybrid interconnect technology to replace only short narrow local signal wires by Al wires. This scheme takes advantage of the fact that signal wires conduct bi-directional currents and are therefore virtually immune to electromigration. The improvement in chip clock frequency is predicted to be between 50% and 100% for the 7 nm technology node. [ABSTRACT FROM PUBLISHER]

Despite the rapid development of photovoltaic (PV) industry, direct current (DC) fault arc remains a major threat to the safety of PV system and personnel. While extensive research on DC fault arc has been conducted, little attention has been paid to the long-time interactions between the PV system and DC arc. In this paper, a simulation system with an arc model and PV system model is built to overcome the inconvenience of the fault-arc experiments and understand the mechanism of these interactions. For this purpose, the characteristics of the series DC arc in a small grid-connected PV system are first investigated under uniform irradiance. Then, by comparing with different arc models, the Habedank model is selected to simulate the fault arc and a method to determine its parameters under DC arc condition is proposed. The trends of simulated arc waveforms are consistent with the measured data, whose fitting degree in adjusted R-squared is between 0.946 and 0.956. Finally, a phenomenon observed during the experiment, that the negative perturbation of the maximum power point tracking (MPPT) algorithm can reduce the arc current, is explained by the proposed model. [ABSTRACT FROM AUTHOR]

In the above-named paper [ibid., vol. 37, no. 4, pp. 508?511, Apr. 2016], a typo was found in equation 3. The corrected equation is provided. [ABSTRACT FROM AUTHOR]