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Advancements in electronic technology have led to the emergence of portable devices like smartphones and smartwatches. For these devices, low-power supply management systems are crucial. In this study, the LDO (low-drop) regulator is implemented with TSMC 0.18 um CMOS high-voltage process. This chip is designed based on multi-current mirror circuits to implement a level-shifting circuit for controlling the error amplifier. The new architecture is achieved using the structure of three low-voltage operational amplifiers. The gate voltage of the power transistor is precisely driven by the level-shifting circuit, eliminating the need for a voltage limiting circuit on the power MOS's Vgs, thus enhancing the response time. This chip incorporates a temperature protection circuit that controls the feedback circuit for high-voltage MOS components. When the temperature exceeds a predefined threshold, the output shuts down immediately. Experimental results demonstrate that this chip can output voltages ranging from 3 to 19 V when the input voltage ranges from 3.5 to 20 V. The chip achieves a maximum output current of 1A and a peak conversion efficiency of 89.94%. [ABSTRACT FROM AUTHOR]

This paper presents a channel-wise average pooling and one dimension pixel-shuffle architecture for a denoising autoencoder (CPDAE) design that can be applied to efficiently remove electrode motion (EM) artifacts in an electrocardiogram (ECG) signal. The three advantages of the proposed design are as follows: (1) In the skip connection layer, less memory is needed to transfer the features extracted by the neural network; (2) Pixel shuffle and pixel unshuffle techniques with point-wise convolution are used to effectively reserve the key features generated from each layer in both the encoder and decoder; (3) Overall, fewer parameters are required to reconstruct the ECG signal. This paper describes three deep neural network models, namely CPDAELite, CPDAERegular, and CPDAEFull, which support various computational capacity and hardware arrangements. The three proposed structures involve an encoder and decoder with six, seven, and eight layers, respectively. Furthermore, the CPDAELite, CPDAERegular, and CPDAEFull structures require fewer multiply-accumulate operations—355.01, 56.96, and 14.69 million, respectively—and less parameter usage—2.69 million, 149.7 thousand, and 55.5 thousand, respectively. To evaluate the denoising performance, the MIT–BIH noise stress test database containing six signal-to-noise ratios (SNRs) of noisy ECGs was employed. The results demonstrated that the proposed models had a higher improvement of SNR and lower percentage root-mean-square difference than other state-of-the-art methods under various conditions of SNR. [ABSTRACT FROM AUTHOR]

The diminished-one modulo [2.sup.n] + 1 addition is an important arithmetic operation for a high-performance residue number system. In this paper, we propose a new circular-carry-selection (CCS) technique for modulo [2.sup.n] + 1 addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. For actual VLSI implementation, the proposed modular adder can demonstrate its superiority of savings up to 39.5% in AreaxTime and 46.3% in TimexPower performances over those of the previous existing solutions under 180-nm CMOS technology. Finally, the chip area and the clock rate of CCS diminished-one modulo [2.sup.16] + ladder are 26746 [micro][m.sup.2] and 476 MHz, respectively. Index Terms--Circular carry selection (CCS), modulo [2.sup.n] + 1 adder, residue number system (RNS), VLSI design.

In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered XOR/XNOR designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-[micro]m process models, indicate that the proposed design has the lowest working [V.sub.dd] and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases. Index Terms--Energy efficient, full adder design, low-voltage operation, pass transistor logic.

In this paper, we present a new four.moduli set ([2.sup.n] - 3, [2.sup.n] + 1, [2.sup.n] - 1, [2.sup.n] + 3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n = 3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work [8]. Index Terms--Balanced bit-width, dynamic range, moduli set, residue to binary (R/B) converter, very large scale integrated circuits (VLSI) design.

This paper presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image. 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6) adaptability for N*N morphologic operations.

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch. [ABSTRACT FROM AUTHOR]

In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual $V_{{\mathrm{DD}}}$ design technique, which facilitates a faster state transition in the slave latch, is devised to enhance time performance. In circuit implementation, transistor sizes are optimized with respect to the power-delay product (PDP). A TSMC 90-nm CMOS process was selected as the implementation technology. In this paper, the performance levels of seven FF designs were compared. The timing parameters of each FF were first characterized. Post-layout simulation results indicated that the proposed design excelled in various performance indices such as PDP, clock-to-Q delay, average power consumption, and leakage power consumption. Moreover, the design was determined to have the smallest layout area. Compared with the conventional transmission-gate-based FF design, the PDP improvement in the proposed design was up to 63.5% (at 12.5% switching activity) and the area saving was approximately 10%. Further simulations on process corners, supply voltage settings, and working frequencies were conducted to study the design reliability. [ABSTRACT FROM AUTHOR]

Stereo vision has become a popular topic in recent years, especially in-depth images from stereo vision. Depth information can be extracted either from a dual camera or RGB-D camera. In image processing, the realization of object detection is only based on the color information or depth images separately; however, both have advantages and disadvantages. Therefore, many researchers have combined them together to achieve better results. A new fast motion object-detection algorithm is presented based on the complementary depth images and color information, which is able to detect motion objects without background noise. The experiment results show that the proposed fast object detection algorithm can achieve 84.4% of the segmentation accuracy rate on average with a 45 FPS computation speed on an embedded platform. [ABSTRACT FROM PUBLISHER]

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node. [ABSTRACT FROM PUBLISHER]

When a band is performing at a public occasion, certain sound effects are expected to be added to enliven the atmosphere. To achieve this effect, microphones and instruments are all connected to an audio mixer, then the expected audio output will be played through the speakers. However, sound engineers always spend plenty of time tuning the mixer until the satisfied results are obtained. This paper presents a smart digital mixer system that integrates touch control, speech control, and commonly used functions on an Android mobile platform to improve the mobility of audio mixer while tuning. The proposed system adopts a digital signal processor (DSP) as the core of the hardware architecture. The application provides a UI interface on an Android mobile phone in order to achieve the functions of speech recognition and touch control. The control commands will be transmitted to DSP via Bluetooth 5.0, self-defined Bluetooth packet format (SBPF), and data transfer controller (DTC). The main contribution of this work is to propose multiple functions of a mixer system with a convenient and interactive user interface. The experimental results show the average accuracy of all respondents reached 92.3%. Moreover, the proposed system has the advantage of having a low-cost hardware circuit design, and provides high flexibility of setting for the audio mixer system according to the user's preference. [ABSTRACT FROM AUTHOR]

The aim of this paper is to distinguish the vehicle detection and count the class number in each classification from the inputs. We proposed the use of Fuzzy Guided Scale Choice (FGSC)-based SSD deep neural network architecture for vehicle detection and class counting with parameter optimization. The 'FGSC' blocks are integrated into the convolutional layers of the model, which emphasize essential features while ignoring less important ones that are not significant for the operation. We created the passing detection lines and class counting windows and connected them with the proposed FGSC-SSD deep neural network model. The 'FGSC' blocks in the convolution layer emphasize essential features and find out unnecessary features by using the scale choice method at the training stage and eliminate that significant speedup of the model. In addition, FGSC blocks avoided many unusable parameters in the saturation interval and improved the performance efficiency. In addition, the Fuzzy Sigmoid Function (FSF) increases the activation interval through fuzzy logic. While performing operations, the FGSC-SSD model reduces the computational complexity of convolutional layers and their parameters. As a result, the model tested Frames Per Second (FPS) on edge artificial intelligence (AI) and reached a real-time processing speed of 38.4 and an accuracy rate of more than 94%. Therefore, this work might be considered an improvement to the traffic monitoring approach by using edge AI applications. [ABSTRACT FROM AUTHOR]

The local-dimming backlight has recently been presented for use in LCD TVs. However, the image resolution is low, particularly at weak edges. In this work, a local-dimming backlight is developed to improve the image contrast and reduce power dissipation. The algorithm enhances low-level edge information to improve the perceived image resolution. Based on the algorithm, a 42-in backlight module with white light-emitting diode (LED) devices was driven by a local dimming control core. The block-wise register approach substantially reduced the number of required line-buffers and shortened the latency time. The measurements made in the laboratory indicate that the backlight system reduces power dissipation by an average of 48% and exhibits no visible distortion compared relative to the fixed backlighting system. The system was successfully demonstrated in a 42-in LCD TV, and the contrast ratio was greatly improved by a factor of 100. [ABSTRACT FROM PUBLISHER]

Background modeling and foreground object detection are crucial techniques for embedded image surveillance systems. The most popular and accurate methods are mostly pixel based, taking up more memory and requiring longer execution times. Thus, these techniques are not suitable for embedded platforms. This paper presents a block-based major color background modeling and a foreground detection algorithm that possesses efficient processing and low memory requirement in a complex scene, making them feasible for embedded platforms. Our proposed approach consumes 37% less memory and increases accuracy by at least 2% compared to existing methods. Last, implementing the object detection algorithm on the VIA VB8001 platform, we can achieve 22 frames per second for the benchmark video with image size 768\,\times\,576. [ABSTRACT FROM PUBLISHER]

In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52. [ABSTRACT FROM PUBLISHER]

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ. [ABSTRACT FROM AUTHOR]

The discriminative object tracking system for unmanned aerial vehicles (UAVs) is widely used in numerous applications. While an ample amount of research has been carried out in this domain, implementing a low computational cost algorithm on a UAV onboard embedded system is still challenging. To address this issue, we propose a low computational complexity discriminative object tracking system for UAVs approach using the patch color group feature (PCGF) framework in this work. The tracking object is separated into several non-overlapping local image patches then the features are extracted into the PCGFs, which consist of the Gaussian mixture model (GMM). The object location is calculated by the similar PCGFs comparison from the previous frame and current frame. The background PCGFs of the object are removed by four directions feature scanning and dynamic threshold comparison, which improve the performance accuracy. In the terms of speed execution, the proposed algorithm accomplished 32.5 frames per second (FPS) on the x64 CPU platform without a GPU accelerator and 17 FPS in Raspberry Pi 4. Therefore, this work could be considered as a good solution for achieving a low computational complexity PCGF algorithm on a UAV onboard embedded system to improve flight times. [ABSTRACT FROM AUTHOR]

To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology. [ABSTRACT FROM AUTHOR]

A novel low‐power sense‐amplifier‐based flip‐flop (FF) is presented. Using a simplified single‐ended pass transistor‐based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense‐amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive post‐layout simulations. [ABSTRACT FROM AUTHOR]