123 results on '"Masera, G."'
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2. Odd type DCT/DST for video coding: Relationships and low-complexity implementations
3. Area efficient DST architectures for HEVC
4. Molecular transistor circuits
5. Molecular transistor circuits: From device model to circuit simulation
6. A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic
7. A Network-on-Chip-based turbo/LDPC decoder architecture
8. Bit-width optimization of extrinsic information in turbo decoder
9. Reconfigurable Architecture for LDPC and Turbo Decoding: A NoC Case Study
10. Mixed hardware-software testbed for IEEE-802.11n
11. A new approach to compress the configuration information of programmable devices
12. Error correcting arithmetic coding for JPEG 2000
13. Interconnection framework for high-throughput, flexible LDPC decoders
14. Low-complexity, efficient 9/7 wavelet filters implementation
15. Optimized CORDIC core for frequency-domain motion estimation
16. A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder.
17. Thermal Control for Crossbar-Based Input-Queued Switches.
18. Iterative MIMO detection: Flexibility and convergence analysis of Soft-Input Soft-Output List Sphere Decoding and Linear MMSE detection.
19. ALOE-Based Flexible LDPC Decoder.
20. A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder.
21. A feasible VLSI engine for soft-input-soft-output for joint source channel codes.
22. Look-Ahead Sphere Decoding: Algorithm and performance evaluation.
23. Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm.
24. Low Complexity Motion Detection with Background Modeling.
25. Error resilient JPEG2000 decoding for wireless applications.
26. VLSI implementation of SISO arithmetic decoders for joint source channel coding.
27. Low resources algorithm for video surveillance.
28. Error correcting arithmetic coding for JPEG 2000.
29. Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information.
30. Accelerating channel codes simulations with a mixed hardware-software system architecture.
31. A VLSI Decoder for the Golden code.
32. Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding.
33. Testing Logic Cores using a BIST P1500 Compliant Approach.
34. Design and implementation of phase correlation based motion estimator.
35. DSP implmentation of a low complexity motion detection algorithm.
36. dynDCT: a dynamically adaptable integer DCT.
37. Mumford and Shah functional: finite precision analysis and software implementation.
38. Design and implementation of a scalable multimedia processor.
39. Hierarchical power supply noise evaluation for early power grid design prediction
40. FPGA power efficient inverse lifting wavelet IP
41. Power bus optimal sizing in presence of power supply noise
42. VLSI Reed Solomon decoder architecture for networked multimedia applications.
43. Automated power supply noise reduction via optimized distributed capacitors insertion.
44. Switching noise analysis framework for high speed logic families.
45. Low-cost IP-blocks for UMTS turbo decoders.
46. Speed and behaviour improvement for semidynamic flip-flop logic family.
47. A 50 Mbit/s iterative turbo-decoder.
48. Transistors optimization of CMOS logic structures for high performance IC.
49. A noise test structure for CMOS logic families.
50. Cell library development using multi-objective function optimization.
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