Search

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies $220\times 630\,\,\mu \text{m}^{2}$ and has no power consumption. [ABSTRACT FROM AUTHOR]

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed. [ABSTRACT FROM AUTHOR]

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from $460 \,\mathrm {k\Omega }$ to $300 \,\mathrm {G\Omega }$ allowing the TIA to process dc currents with a dynamic range of more than $100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between $0.3 \,\mathrm {M\Omega }$ and $100 \,\mathrm {M\Omega }$ , resulting in an overall ac transimpedance between $3 \,\mathrm {M\Omega }$ and $1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of $10 \,\mathrm {MHz}$ is achieved. The TIA provides a minimum input-referred current noise density of $1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of $1.5\,\mathrm {V_{pp}}$ with a THD below $1 \mathrm {\%}$ on a $1.8-\mathrm {V}$ supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account. [ABSTRACT FROM AUTHOR]

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author’s knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board. [ABSTRACT FROM AUTHOR]

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate $< 1\text{E}$ -10 with a power efficiency of 4.75 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper investigates the secure consensus tracking problem for continuous-time nonlinear multiagent systems with sensor attacks. By designing a secure data selector, the unattacked output data is extracted from a group of output measurements under sparse sensor attacks. Then, by virtue of the obtained data and neural networks, a state observer is constructed to estimate the unavailable system states, where the convex combination theory is introduced to reduce the difficulty of solving observation gains. To utilize the limited communication resources reasonably, a novel saturated threshold event-triggered control strategy is proposed to reduce control updates, and then each update is encoded into a binary signal (0 or 1) to further reduce the occupation of communication bandwidth. The designed control scheme ensures that all closed-loop signals are semi-globally uniformly ultimately bounded, and its effectiveness is verified via a simulation of attitude control of unmanned aerial vehicles. [ABSTRACT FROM AUTHOR]

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm2 and a power dissipation of 0.85W. [ABSTRACT FROM AUTHOR]

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of $1.75\times $. In image training tasks, the proposed hardware architecture helps to achieve up to $1.67\times $ speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by $1.30\times $ and $1.04\times $ respectively. [ABSTRACT FROM AUTHOR]

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling. [ABSTRACT FROM AUTHOR]

This paper presents direct sequence spread spectrum (DS/SS) datalinks operating at 92-100 GHz with spreading factors up to 100K. Unlike traditional DS/SS datalinks which rely on preamble and cyclic dispreading for synchronization, the reported datalink uses a self-synchronous demodulation scheme, avoiding the large hardware complexity associated with exceptionally large spreading factors, and avoiding the difficulties of synchronizing the long de-spreading codes that are applicable to mm-wave systems. A demonstration link chipset is presented operating at 92-100 GHz with a spreading factor of 104K and a spread bandwidth of 6.0 GHz (baseband bandwidth of 56Kb/s) while consuming a total of 425mW. [ABSTRACT FROM AUTHOR]

This paper proposes a technique which allows quadband impedance matching and impedance level shifting Doherty power amplifier (DPA) design. By using novel coupler networks with reactance and choosing appropriate complex load impedances, the quadband DPA can reach a power back-off range (OBO) of over 9 dB. In addition, the peak PA branch and the carrier PA branch use different coupler network parameters in order to satisfy different impedance requirements. To illustrate the design procedure a quadband DPA with 9 dB OBO operating in 0.5-0.7 GHz, 1.5-1.7 GHz, 2.5-2.7 GHz, and 3.5-3.7 GHz frequency ranges is designed, fabricated and tested. Measurements demonstrate that the DPA can deliver saturated output power between 43.1 dBm and 43.8 dBm in all four bands, with a drain efficiency ranging from 63.3% to 66.5%. Also, drain efficiency of from 42.2% to 52.3 % can be obtained at an OBO of 9 dB level. The DPA implemented here shows state-of-the-art performance for OBO under quad-band operation. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper addresses the problem of simultaneous fault detection and control (SFDC) for Markov jump systems (MJSs) over sensor networks. In order to save the bandwidth of the network, round-Robin protocol is adopted for the communication between the sensors and fault detection filter. First, to fully utilize the data of sensor networks, a new distributed system is developed especially for SFDC, and a residual system, which integrates the MJSs with the distributed SFDC system, is also established. Then, by constructing a mode-dependent Lyapunov functional, the conditions for distributed SFDC are derived, which can make the residual system asymptotically mean-square stable and meanwhile satisfy the prescribed H∞ performance requirements. Finally, comparison analyses are made by examples to illustrate the effectiveness and superiority of the proposed new design approach. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

A wideband CMOS low-noise amplifier (LNA) with multiple resonant frequencies is demonstrated in this article. A common source (CS) with inductive degeneration topology is widely employed in LNA circuit design to decouple the input impedance from the noise figure (NF). Since CS with inductive degeneration topology only achieves a single resonant frequency, it generally has narrow bandwidth performance. Through impedance transformation analysis of the matching circuit, a shunt resonator combined with inductive degeneration topology employed for input impedance transformation is carefully constructed to form multiple resonant frequencies. By placing resonant frequencies further apart from each other, impedance fluctuations within a wideband frequency range can be alleviated. In addition, the noise performance of this topology is the same as that of a conventional CS source-degenerated structure. The proposed LNA for the whole K/Ka Band is implemented in a commercial 65-nm CMOS process. It occupies 0.28 mm2. Under a 1.0 V voltage supply, the LNA achieves 3-dB gain bandwidth of 28 GHz from 16.5 GHz to 44.5 GHz. Within the whole 3-dB bandwidth, the gain is larger than 15.5 dB, the NF is less than 4.8 dB with a minimal value of 2.72 dB, and the input 1-dB gain compression point (IP1dB) varies from −24 dBm to −12 dBm. [ABSTRACT FROM AUTHOR]

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at $f_{s}\,{=}\,800$ MHz, while the back-end samples at $f_{s}/2$. [ABSTRACT FROM AUTHOR]

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18- $\mu \text{m}$ standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs. [ABSTRACT FROM AUTHOR]

This article is to present a complete method to design transmission-line reflectionless filters. Our approach can be used to accord a transmission-line filter to feature an infinite frequency range of reflectionless response. It can be applied to reflectionless filter prototypes consisting of filtering and matching sections that comply the Cauer topology. Hence, it does not limit by the filter order and/or the filter response type. Design equations supporting our approach are provided, and their applications to actual filter designs will be elaborated via various filter examples with distinct features. The measurements authenticate our design approach. [ABSTRACT FROM AUTHOR]

A novel algorithm is presented that can resolve frequency ambiguity that arises from sampling a set of signals spanning more than a single Nyquist zone. The method uses two samplers, each sampling the same input signal with different (non-integer multiple) sampling rates. The algorithm is able to resolve frequency ambiguity and reconstruct signals with an orthogonal frequency basis spanning multiple Nyquist zones, provided that the aggregate information-bearing bandwidth of the signals is less than half the cumulative data converter sampling rates. This manuscript describes the theoretical background for the algorithm and validates it through measurements performed on a test-board comprising of two 10 bit analog-to-digital converters clocked at two different (non-integer multiple) sample rates. Measurements show that even in the presence of aliasing, an orthogonal signal spanning multiple Nyquist zones can be fully reconstructed. [ABSTRACT FROM AUTHOR]

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s. [ABSTRACT FROM AUTHOR]

The increasing demand for data-intensive computing applications, such as artificial intelligence (AI) and more specifically machine learning (ML), raises the need for novel computing hardware architectures capable of massive parallelism in performing core algebraic operations. Among the new paradigms, in-memory computing (IMC) with analogue devices is attracting significant interest for its large-scale integration potential, together with unrivaled speed and energy performance. Here, we present a fully-analogue, universal primitive capable of executing linear algebra operations such as regression, generalized least-square minimization and linear system solution with and without preconditioning. We study the impact of the main circuit parameters on accuracy and bandwidth with analytical closed-form expressions and SPICE simulations. Scaling challenges due to parasitic resistance/capacitance and their impact on key parameters such as bandwidth and accuracy are discussed. Finally, a comparison with existing solvers belonging to the same IMC framework is made to assess advantages and disadvantages of the proposed circuit. [ABSTRACT FROM AUTHOR]

The presence of RLC line parasitics in a flexible hybrid electronic assembly can lead to signal integrity issues, and their progression over time can lead to catastrophic failures. A technique for extracting the RLC line parasitics from a flexible hybrid electronics assembly is presented. The proposed extraction method exploits the on-chip ESD protection circuits of an IC chip to extract the parasitics of the printed conductors bonded to the chip. This is performed through a single test access port, i.e., two test points. While the parasitics LC are extractable through one-port reflection-based techniques such as time domain reflectometry; the parasitic R requires a two-port measurement such as Kelvin test, which is extremely difficult to perform for printed conductors bonded to small surface-mount IC package devices. The accuracy of the extracted RLC parameters with the proposed method are verified with a prototype developed on a rigid FR4 substrate. Subsequently, the proposed technique is utilized to track the variation of the RLC parasitics for prototypes developed on Kapton Polyimide substrate subjected to different forms of bending. [ABSTRACT FROM AUTHOR]

Centralized Massive Multiple Input Multiple Output (MIMO) uplink detection techniques for baseband processing possess severe bottleneck in terms of interconnect bandwidth and computational complexity. This problem has been addressed in the current work by adapting the centralized Newton method for decentralized MIMO uplink detection leveraging several Base Station antenna clusters. The proposed decentralized Newton (DN) method achieves error-rate performance close to centralized Zero Forcing detector as compared to other decentralized techniques. Two hardware topologies, namely the ring and the star topologies, are proposed to assess and discuss the trade-off among interconnect bandwidth and throughput, in comparison with contemporary decentralized MIMO uplink detection techniques. As such the following findings are elaborated. On BS antenna cluster scaling for different MIMO system configurations, the ring topology provides high throughput at constant interconnect bandwidth, while the star topology provides lower latency with a deterministic variation in the hardware resource consumption. Due to strategic optimizations on the hardware implementation, additional user equipment can be allotted at a fractional increase in Field Programmable Gate Array resource consumption, improved energy efficiency, and increased transaction of bits per Joule. The ring topology can process additional subcarrier at a fractional increase in latency and improved system throughput. [ABSTRACT FROM AUTHOR]

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between −7 and −30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205 × and 140 ×, respectively. [ABSTRACT FROM AUTHOR]