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This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a $50\times 50$ array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy. [ABSTRACT FROM AUTHOR]

Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

Diffusion-driven instabilities with pattern formation may occur in a network of identical, regularly-spaced, and resistively-coupled cells if and only if the uncoupled cell is poised on a locally-active and stable operating point in the Edge of Chaos domain. This manuscript presents the simplest ever-reported two-cell neural network, combining together only 7 two-terminal components, namely 2 batteries, 3 resistors, and 2 volatile NbOx memristive threshold switches from NaMLab, and subject to diffusion-driven instabilities with the concurrent emergence of Turing patterns. Very remarkably, this is the first time an homogeneous cellular medium, with no other dynamic element than 2 locally-active memristors, hence the attribute all-memristor coined to address it in this paper, is found to support complex phenomena. The destabilization of the homogeneous solution occurs in this second-order two-cell array if and only if the uncoupled cell circuit parameters are chosen from the Edge of Chaos domain. A deep circuit- and system-theoretic investigation, including linearization analysis and phase portrait investigation, provides a comprehensive picture for the local and global dynamics of the bio-inspired network, revealing how a theory-assisted approach may guide circuit design with inherently non-linear memristive devices. [ABSTRACT FROM AUTHOR]

Most memristor-based associative memory neural networks are focused on classical conditioning and ignored operant conditioning. In this paper, a memristor-based neural network of operant conditioning accorded with biological feature is designed. The designed circuit includes a voltage control module, an operant module and synapse modules. It realizes learning, forgetting, long-term memory, reinforcement and punishment functions based on variable synapse structure and double self-protection measure. Meanwhile, the four factors that affect operant conditioning such as contingency, immediacy, magnitude and deprivation are discussed and implemented. The simulation results in PSPICE show that the circuit can be used to simulate actual conditioned reflex and complicated applications. The memristor-based neural network circuit of operant conditioning provides more references for further development of neural networks. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid-integrated optical transceiver front-end for beyond-400G short-reach optical links. A pair of the monolithic 8-channel laser drivers and the trans-impedance amplifier (TIA) is developed in 180nm SiGe BiCMOS, incorporating arrayed Vertical-Cavity-Surface- Emitting Lasers and photo-detectors. The driver uses a $2^{\mathrm {nd}}$ -order continuous-time linear equalizer (CTLE) to compensate for the channel loss with a nonlinear frequency response. Both the inductive peaking and RC-degeneration are embedded at the output stage to extend the optical modulation bandwidth (BW). The series-peaking and multi-stage distributed CTLE are combined in a resistive feedback TIA topology for improved BW and linearity. Measurement results show up to 100-Gb/s PAM-4 electrical eyes of the driver and TIA. The optical transmitter front-end operates 56 Gb/s, 4.1-dB extinction ratio, and 6.6-pJ/bit power efficiency, while the optical receiver front-end achieves 56-Gb/s, $10^{-6}$ bit error rate, and 5.9-pJ/bit power efficiency. [ABSTRACT FROM AUTHOR]

Inhomogeneous linear ordinary differential equations (ODEs) and systems of ODEs can be solved in a variety of ways. However, hardware circuits that can perform the efficient analog computation to solve them are rarely in the literature. To address such problems, this paper proposes a general method of using a memristor-capacitor (M-C) circuit to solve inhomogeneous linear ODEs and systems of ODEs of any order in initial value problems. The M-C circuit can match the coefficients of the equations sought by adjusting the memristor resistance value according to the coefficient formula proposed in the paper, which has higher programmability. Then, some ODEs and systems of ODEs are given in the paper as examples to evaluate the proposed method. According to the comparison results based on MATLAB software simulation and the simulation based on OrCAD software, the designed M-C circuit has an effective improvement in speed and the accuracy exceeds 99.95% in software simulation. Based on practical verification, this paper gives the actual M-C circuit experiment based on PCB. Moreover, the proposed method can be used to quickly solve the object motion state in the spring mass damping system in actual engineering, and the accuracy can reach 99.98%. [ABSTRACT FROM AUTHOR]

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed. [ABSTRACT FROM AUTHOR]

An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis ANN, two analysis ANNs and a proposed self-inspection machine (SIM). For a given design request, the SAM synthesizes a layout first, followed by analyzing the performance of the layout automatically, and finally improves the layout confidence through self-inspection. Compared to the modeling functions of analysis ANN, the synthesis ANN behaves as an inverse model, of which the inputs are desired inductor performances while the outputs are geometrical parameters of the layout. However, multi-value problems might occur in obtaining geometries of inductors, suggesting with evidence from mathematic relationships between geometrical and electrical parameters of an inductor. A multi-valued training dataset will mislead the synthesis ANN, resulting in unqualified layouts. To deal with this issue, a solution space contraction technique (SSCM) is also proposed. Furthermore, the SIM suspends most of the failures by comparing the output of analysis ANN back to the input of synthesis ANN. An electromagnetic simulation tool is used for experiments, and the effectiveness of the proposed SAM is proven by 6,500 inductor samples. [ABSTRACT FROM AUTHOR]

This paper is concerned with the secure estimation problem for the state of charge of Lithium-ion batteries subject to malicious attacks during the data transmission from sensors to cloud-based battery management system terminal. First, the second-order resistance-capacitance equivalent circuit model, whose parameters are identified by Kalman filter in an off-line manner, is introduced to describe the internal dynamics of lithium-ion batteries. Then, by applying the $\chi ^{2}$ detection mechanism, real-time malicious attacks are first detected and then a secure estimator is designed to suppress the influence of attacks on the estimation performance. An upper bound of the filtering error covariance is determined by solving certain coupled Riccati-like equations, and the filter parameter is obtained by minimizing such an upper bound at each time step. Finally, the validity of the proposed attack detection approach and the effectiveness of the developed estimation scheme are verified by experiment results under Federal Urban Driving Schedule condition. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed. [ABSTRACT FROM AUTHOR]

Stacked MOS power amplifiers (PA) are commonly used in SOI nodes but also have the potential to be realized in bulk CMOS nodes. In this paper they are analyzed in millimeter wave regimes. The study focuses on the key limiting factors and in particular the optimum number of transistors from which the key performance parameters such as maximum possible operating frequency, output power, and efficiency are achieved. Based on the analysis, design trade-offs of stacked MOS PAs are presented. The frequency dependency of the optimum load presented to each stack is analyzed to express the overall performance of the mentioned PA topologies as a new optimization method. Additionally, it is shown how the optimal load variations translate into amplitude-to-amplitude/phase (AM-AM/PM) conversion distortions. The validity of the analysis is examined against simulations. The simulations are performed based on 8M1P CMOS 28nm technology and electromagnetic simulations in ADS Momentum. [ABSTRACT FROM AUTHOR]

Efficient simulation of switched-mode power conversion circuits is necessary for the analysis and optimization of power electronics. This paper introduces the extended impedance method (EIM) to the simulation and analysis of general switched-mode power converter circuits. By using the EIM method, the conventional impedance concept can be extended to involve more linear time-variant (LTV) and nonlinear devices, such as MOSFET switches and diodes, which are commonly used in switched-mode power conversion circuits. EIM models a circuit network from the component level in the frequency domain, rather than from the system-level constitutive differential equation in the time domain. Compared with the conventional averaging method, EIM can reveal more high-frequency features of a switched-mode converter circuit, in particular, those around the switching instants. A buck converter is taken as a representative example to validate the EIM based analysis. Both the simulation and experimental results prove that EIM provides precise numerical results, which match the real waveform, as the commercial simulators, e.g. PSpice and ADS, do. Moreover, it largely reduces the computational complexity towards more efficient and more flexible steady-state analysis of switched-mode power electronics. [ABSTRACT FROM AUTHOR]

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

A well-performed capacitive power transfer (CPT) system highly depends on its compensation to achieve load-independent (LI) output and zero phase angle (ZPA) operation. It is particularly meaningful to maintain these objectives under various misalignments. This paper is devoted to a general and comprehensive method to study and explore all the potential high-order compensations. The coupler parameter variation is evaluated under different types of misalignment, and misalignment-insensitive (MI) parameters are properly designed for MI resonance. A general and straightforward decomposition and synthesis method is then proposed to generate the high-order resonant tanks. With the help of inverse ABCD parameters, all tank candidates are further judged by their capability for LI output and ZPA operation. Finally, two example CPT systems are built to verify the LI output and ZPA operation under misalignment. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on the high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation) without needing a detailed electrical simulation. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, MDM Laboratory. The parameters extraction procedure is also discussed. The obtained results clearly show that the model proposed in this paper is able to capture the influence of the programming pulse parameters (i.e. pulse duration and height) changes. This is accomplished by the introduction of a parameter, which is related to the specific device technology. [ABSTRACT FROM AUTHOR]

Tree-based machine learning models, like random forests and decision trees, are low-complexity solutions that provide an efficient prediction for a wide range of applications. These models are particularly interesting for energy-constrained platforms since they can be implemented with simple logical operations. Tree-based accelerators are also intrinsically resilient to errors, and this can be leveraged to boost energy efficiency with approximate computing techniques. The key operations in these models are comparisons to constants, making comparators excellent candidates for approximation. This paper presents a technique to approximate comparisons to constants called C2PAx, which is capable of reducing the area and energy of tree-based accelerators. The method consists in finding alternative constants that reduce circuit area while keeping an efficient prediction performance. It is also shown that the selection of the constant parameters directly influences both hardware complexity and model performance, demanding cross-layer optimization. For that, we extend an existing framework that generates VLSI tree-based accelerators, inserting our approximation proposal that allows selecting the constant parameters that maximize energy efficiency at the cost of minor accuracy drops. Simulation results demonstrate that C2PAx outperforms the Don’t Care logic approximation technique when accuracy and energy are jointly considered. C2PAx trades accuracy for significant reductions in the VLSI area, power, delay, and energy consumption compared to precise models. [ABSTRACT FROM AUTHOR]

Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) with large scales of artificial neurons are increasingly used in recognition and classification tasks. In power-constrained scenarios, the tradeoff between performance and hardware consumptions must be carefully evaluated before silicon tape-out. In this paper, we proposed a systematic approach to design ultra-low power NN system. This work is motivated by the facts that NNs are resilient to approximation in many of the computations and NNs are outputting statistical tensors which are acceptable to less-than-perfect results. We resort to the front-back end approach with a twofold aim: (1) a fast and accurate design approach is proposed by estimating the computing quality of low-power approximate adder arrays, and it is adopted to evaluate the neural network system; (2) a quality configurable engine with different approximation degrees while processing NNs is implemented. The proposed work is demonstrated with a comprehensive keyword spotting (KWS) system as an ultra-low power NN engine. The experimental environment is setup with ten keywords from the google speech command dataset (GSCD) using an industrial 22-nm ultra-low-leakage (ULL) process. Comparing to the state-of-the-art KWS processors, the proposed approximate NN engine can demonstrate over 60% improvement in power efficiency and $1.1\times $ area efficiency while achieving similar recognition accuracy. [ABSTRACT FROM AUTHOR]

In this paper, a miniature dual-band absorptive bandstop filter (ABSF) design with improved lower passband performance is proposed. Specifically, a stepped-impedance short-circuited stub is introduced to a bridged-T coil-based dual-band ABSF design, such that the insertion loss around the desired passband center frequency can be largely reduced while the absorptive stopband performance remains intact. This also helps equalize the lower passband insertion loss response and achieve a flatter passband, which is especially advantageous when cascading multiple ABSFs for improving the stopband rejection or increasing the number of stopbands. Closed-form design formulas are established to facilitate the synthesis of proposed dual-band ABSF. As an example, a 4.8/9.6-GHz dual-band ABSF in GaAs is realized with a measured insertion loss within 0.85± 0.12 dB from dc to 2.6 GHz. The circuit size is only 1.6 mm $\times $ 1.84 mm, and the corresponding electrical size is $0.013\lambda _{0} \times 0.015\lambda _{0}$ at the designated passband center frequency of 2.4 GHz. Application of the proposed dual-band ABSF for the passband performance improvement of cascaded ABSF designs is also demonstrated, and good performance is obtained. [ABSTRACT FROM AUTHOR]

This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a smart pulsing strategy is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision. [ABSTRACT FROM AUTHOR]

The dynamics of modern hybrid power systems are characterized by behaviors at different timescales, typically separated by several orders of magnitude. In this paper we apply the envelope-following method to hybrid power systems simulations, in which single-phase and three-phase representations of a power system co-occur. This simulation method is well suited for handling coexisting behaviors occurring at different timescales. Compared to the simulation approaches present in the literature, the envelope-following method does not need to continuously switch between two separate simulation engines, but rather automatically handles instantaneous variations in the dynamics of the system, such as faults or topology changes. Additionally, given the vast penetration of power electronic components in modern electricity networks, employing the envelope-following method allows using a vast array of numerical algorithms that have been developed over the years to simulate electrical and electronic circuits. The proposed approach is validated by means of power systems case studies of increasing complexity. [ABSTRACT FROM AUTHOR]

Computing-in-memory (CIM) is a new architecture which is more energy-efficient than the Von Neumann architecture due to the fact that it performs calculation in the memory units which can reduce a large amount of data movement. Nowadays, CIM with non-volatile memory (nvCIM), such as resistive random access memory (RRAM), has become a research frontier to further improve computing performance. Recent works mainly explored how to improve the computing performance of nvCIM, but seldom paid attention to the problem of accuracy loss. In this paper, we propose the nvCIM framework, which can systematically analyze the relationship between the classification accuracy of network models and main analog factors. Based on the nvCIM framework, we further provide detailed optimization methods, including RRAM features, array properties, and ADC parameters. The adaptive voltage-controlled SET and pulse-controlled RESET (VSPR) program-verify scheme is proposed to achieve high-resolution RRAM. And the margin enhancement based current-mode sense amplifier (MECSA) and offset reduction based analog-to-digital converter (ORADC) are proposed to improve the accuracy of analog part computing. Experimental results show that the macro-level and system-level energy efficiency is 112.1 TOPS/W and 9.86 TOPS/W respectively with less than 3.51% loss in contrast to the ideal accuracy, which is $2.9\times $ - $25.9\times $ compared to the energy efficiency of existing RRAM based nvCIM accelerators. [ABSTRACT FROM AUTHOR]

In this paper, a unified framework is proposed to address the synchronization problem of memristor chaotic systems (MCSs) via the sliding-mode control method. By employing the presented unified framework, the finite-time and fixed-time synchronization of MCSs can be realized simultaneously. On the one hand, based on the Lyapunov stability and sliding-mode control theories, the finite-/fixed-time synchronization results are obtained. It is proved that the trajectories of error states come near and get to the designed sliding-mode surface, stay on it accordingly and approach the origin in a finite/fixed time. On the other hand, we develop an image encryption algorithm as well as its implementation process to show the application of the synchronization. Finally, the theoretical results and the corresponding image encryption application are carried out by numerical simulations and statistical performances. [ABSTRACT FROM AUTHOR]

Memristors are widely used to construct multi-scroll/wing chaotic systems with complex dynamics. However, the generation of a multi-scroll/wing attractor is typically not induced by the memristor but depends on other nonlinear functions in the system, which does not take advantage of the unique features of the memristor for chaos-based applications. To address this issue, the present paper introduces a memristor coupling (MC) method to construct a novel memristive Sprott A system (MSAS) through coupling a flux-controlled memristor with multi-piecewise linear memductance into the chaotic Sprott A system. From theoretical analysis and numerical simulations, the MSAS is shown to be able to generate any number of multi-type hidden attractors, including multi-one-scroll, multi-double-scroll and multi-double-wing hidden attractors. In addition, it has two kinds of multistabilities, that is, heterogeneous multistability and homogeneous multistability. Based on these unique properties, different numbers of coexisting heterogeneous hidden attractors and coexisting homogeneous hidden attractors are derived respectively by switching the memristor initial states. These interesting dynamical properties are comprehensively investigated using nonlinear analysis tools. Furthermore, hardware experiments are implemented to demonstrate the feasibility of the MSAS and the effectiveness of the MC method. Finally, a new pseudo-random number generator (PRNG) is proposed to explore the practical applications of the MSAS. Performance evaluation results verify the high-quality randomness of the designed PRNG. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical method for effectively evaluating the performances of zero-bias diode-based RF power harvesters. The method allows the accurate calculation of both the diode power conversion efficiency (PCE) and matching efficiency, while showing the wide adaptability to frequency and input power. To calculate the diode PCE accurately, the junction voltage is built based on modeling the diode junction capacitance and turn-on voltage. Using the accurate diode PCE, the equivalent nonlinear resistance of the diode is calculated, and thus the diode impedance is obtained. This helps to design a matching network with required bandwidths and evaluate the corresponding matching efficiency. The total PCE of the RF power harvester is finally obtained by multiplying the diode PCE and matching efficiency. For verification, dual-band RF power harvesters based on diodes of SMS7630 and HSMS-2850 are developed to cover the two 5G frequency bands for three telecom operators in China (2.515-2.675, 3.4-3.5 & 3.5-3.6 GHz). They are designed to operate in the low power range of −25-−5 dBm for low power harvesting scenarios. Compared with the simulated results, the calculation discrepancy of less than 3.12% can be achieved in evaluating the total PCEs of the RF power harvesters. Prototypes of the designed RF power harvesters were fabricated and measured for validation. It shows that the proposed analytical method can provide design guidelines for developing a multi-band RF power harvester. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

On the emerging development of SiC MOSFET, the switching frequency of power converters has been pushed to the order of hundreds of kilohertz or even megahertz to improve power density. However, the state-of-the-art simulations for such high-frequency power electronics circuits are usually time-consuming, blocking the studies of long dynamics such as several seconds. What’s worse, adopting physical models to simulate the turn-on and turn-off transients leads to high stiffness and therefore convergence problems. In this paper, an event-driven approach is proposed to improve the solving speed and simulation stability of SiC based high-frequency converters. A time-scale hierarchical automaton is proposed to model the system, where piecewise analytical transient model for SiC MOSFET is established as the second layer in the automaton to simulate the switching transients with improved numerical stability. Simulation of the system is driven by discrete events in the automaton. A 3.3 kW 79.1 kHz wireless power transfer system for the wireless charging of electric vehicle is studied. Compared with ideal switch model in Simulink and physical switch model in LTspice, 60-fold and 400-fold increases in terms of simulation speed with same level of accuracy are achieved respectively. The simulated results are also attested to by experimental verifications. [ABSTRACT FROM AUTHOR]

Regarding as a basic circuit component with special nonlinearity, memristor has been widely applied in chaotic circuits and neuromorphic circuits. However, discrete memristor (DM) has not been received much attention, yet. To this end, this paper reports a general DM model and its unified mapping model. Using the general DM model, four representations of DMs are given and their pinched hysteresis loops are exhibited. Based on the unified DM mapping model, four two-dimensional (2D) DM maps are generated and their parameter-relied and initials-relied behaviors are explored using multiple numerical measures. The results demonstrate that all the four 2D DM maps can generate hyperchaos with coexisting bi-stable or memristor initial-boosted behavior, and their sequences have excellent performance indictors. A hardware device is constructed to implement these maps and the analog voltage signals are experimentally acquired. Moreover, pseudo-random number generators (PRNGs) are designed using these DM maps and the test results show that the generated pseudo-random numbers (PRNs) have high randomness. [ABSTRACT FROM AUTHOR]

In this paper, the sensitivity of the neural network (NN) outputs to device parameter uncertainties (non-idealities) in inverter-based memristor (IM) crossbar neuromorphic circuits is mathematically modeled and verified using exhaustive circuit and system-level simulations. The NN sensitivity is obtained by modeling the sensitivity of the IM neuron output to the non-idealities of its circuit elements. The analysis reveals a higher sensitivity of the output voltage of the IM neuron to the non-idealities of the inverters compared to the conductance variation of the memristors. Among the inverter non-idealities, horizontal shift of the inverters voltage transfer characteristic (VTC) shows the highest impact on the output voltage of the neuron. To reduce the accuracy loss due to the variations, a training approach which includes a sensitivity term in the cost function of the training phase, is suggested. The achievable improvements through the said NN training approach are evaluated. In the evaluation, the California Housing, MNIST, and Fashion MNIST datasets are employed. The results show up to 50% reduction in the NN output variations in the presence of circuit elements’ non-idealities. [ABSTRACT FROM AUTHOR]

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty. [ABSTRACT FROM AUTHOR]

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems. [ABSTRACT FROM AUTHOR]

In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems. [ABSTRACT FROM AUTHOR]

In this paper, a method for offline training of inverter-based memristive neural networks (IM-NNs), called ERIM, is presented. In this method, the output voltage of the inverter is modeled very accurately by considering the loading effect of the memristive crossbar. To properly choose the size of each inverter, its output load and the required slope of its voltage transfer characteristic (VTC) for an acceptable level of resiliency to the circuit element non-idealities are taken into account. The efficacy of ERIM is investigated by comparing its accuracy to those of two recently proposed offline training methods for IM-NNs (RIM and PHAX). The study is performed using IRIS, BCW, MNIST, and Fashion MNIST datasets. Simulation results show that 72% (56%) reduction in average energy consumption of the trained networks is achieved compared to RIM (PHAX) thanks to proper sizing of the inverters. In addition, due to the higher accuracy of the NN mathematical model, ERIM results in significant improvements in the match between the results of high-level modeling and HSPICE simulations while exhibiting lower sensitivity to circuit element variations. [ABSTRACT FROM AUTHOR]

Nowadays, research, modeling, simulation and realization of brain-like systems to reproduce brain behaviors have become urgent requirements. In this paper, neural bursting and synchronization are imitated by modeling two neural network models based on the Hopfield neural network (HNN). The first neural network model consists of four neurons, which correspond to realizing neural bursting firings. Theoretical analysis and numerical simulation show that the simple neural network can generate abundant bursting dynamics including multiple periodic bursting firings with different spikes per burst, multiple coexisting bursting firings, as well as multiple chaotic bursting firings with different amplitudes. The second neural network model simulates neural synchronization using a coupling neural network composed of two above small neural networks. The synchronization dynamics of the coupling neural network is theoretically proved based on the Lyapunov stability theory. Extensive simulation results show that the coupling neural network can produce different types of synchronous behaviors dependent on synaptic coupling strength, such as anti-phase bursting synchronization, anti-phase spiking synchronization, and complete bursting synchronization. Finally, two neural network circuits are designed and implemented to show the effectiveness and potential of the constructed neural networks. [ABSTRACT FROM AUTHOR]

Ring oscillators, with capacitive load intended for frequency tuning, can fail to sustain stable oscillations. Failure depends on the size of the load capacitors and their equivalent series resistance. This paper first describes the failing mechanism from an intuitive perspective. It then develops an analytical model and provides the equations for the minimum load capacitance and the range of equivalent series resistance at which the ring oscillator fails. The dependency on the number of stages of the ring oscillator as well as the trans-conductance and impedance of its gain stages are also examined. Confirmed by simulations, the model shows that the failing region reduces significantly for ring oscillators with 7 or more stages but that it can be a serious concern for 5 and especially 3-stage ring oscillators. [ABSTRACT FROM AUTHOR]

This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ($\mathrm {P}_{\mathrm {DC}}$), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs $\ge80$ GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ($\mathrm {P}_{\mathrm {DC}}$) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per $\mathrm {P}_{\mathrm {DC}}$ (${\mathrm {GBP}} \mathord {\left /{ {\vphantom {{\mathrm {GBP}} \mathrm {P}_{\mathrm {DC}}}} }\right. } \mathrm {P}_{\mathrm {DC}}$) of 6.01 GHz/mW while being power-efficient. [ABSTRACT FROM AUTHOR]

Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities. [ABSTRACT FROM AUTHOR]

Synchronization transition in neuromorphic networks has attracted much attention recently as a fundamental property of biological neural networks, which relies on network connectivity along with different synaptic features. In this work, an area-optimized FPGA implementation of an Asynchronous Cellular Automata Neuron model that exhibits discrete-state neuron dynamics is introduced. The proposed neuron model is capable of reproducing various neuromorphic oscillations observed in biological neurons using less hardware resources than previous implementations. We investigate synchronization transitions with a focus on the emergence of chimera states in a ring-based network consisting of hardware-based neurons with electrical synaptic coupling. In particular, we study the effects on the network’s phase synchronization through changing two control parameters: the coupling range and the coupling strength. We indicate that via proper configuration of the coupling parameters, we influence the synchronization transition and reveal chimera states which have been associated with neurological disorders. [ABSTRACT FROM AUTHOR]

In this work, a stable and accurate model order reduction method for large-scale partial element equivalent circuit (PEEC) models with many delays is proposed. The method reduces the dimension of the original model by interpolating the original transfer function. The interpolation points are iteratively selected using a greedy algorithm. An efficient error estimator for the reduced transfer function makes the greedy algorithm very successful in both, properly selecting the interpolation points and tightly measuring the error of the reduced transfer function. The resulting reduced-order model is accurate both in the frequency and in the time domain. Numerical tests have shown that the reduced-order model successfully filters the instability behavior of the original model and exhibits stability over a large time interval. [ABSTRACT FROM AUTHOR]

Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively. [ABSTRACT FROM AUTHOR]

A model-based strategy for an efficient power supply control used in a wireless sensor network is presented. The strategy, based on Pulse-Skipping Modulation, regulates the current charging a battery, delivered by a photovoltaic source, resulting in an accurate current regulation and highly efficient power management. The strategy is implemented on a microcontroller unit and compensates for the microcontroller self-absorbed current. The modulation signal is generated through a full software interface, reducing the requirement for external components. Experimental validations, performed on a charger prototype by using a laboratory photovoltaic device simulator, proved that both regulation accuracy, regulation resolution and converter efficiency achieved are superior to the classic Pulse-Width Modulation. The approach results in a simple practical implementation, carries over the advantages of an up-to-date model for the photovoltaic device, and serves the auxiliary purpose of using the photovoltaic source as an instantaneous solar irradiance sensor. [ABSTRACT FROM AUTHOR]

No isolated system may ever support complexity. Emergent phenomena may however appear in an open system, if, as established by the Edge of Chaos theory, some of its constitutive elements feature the capability to amplify infinitesimal fluctuations in energy, provided an external source supplies them with a sufficient amount of DC power, which is known to be a signature for locally-active behaviour. In particular, complex behaviours, including static and dynamic pattern formation, may emerge in arrays of identical diffusively-coupled cells, if and only if the basic unit is poised on a particular sub-domain of the Local Activity regime, referred to as Edge of Chaos, within which a quiet state hides in fact a high degree of excitability. Here we show, for the first time, that these counterintuitive phenomena may emerge in a basic memristor cellular neural network, consisting of two identical diffusively-coupled second-order cells. The proposed bio-inspired array represents the simplest ever-reported open system, which reproduces the shocking phenomenon, reported by Smale in 1974, when, while studying a model from cellular biology, he observed two identical reaction cells, “mathematically dead” on their own, pulsating together upon diffusive coupling. Impressively, the bio-inspired two-cell reaction-diffusion network contains only nine circuit elements, specifically two DC voltage sources, three linear resistors, two linear capacitors, and two functional niobium oxide (NbO) memristors from NaMLab. Applying the theory of Local Activity to an accurate model of the memristor oscillator, a comprehensive picture for its local and global dynamics may be drawn, providing a systematic method to tune the design parameters of the two-cell array to enable diffusion-driven instabilities therein. [ABSTRACT FROM AUTHOR]

We present a compact, continuous, and numerically stable version of a tantalum oxide (TaOx) memristor model which can be employed for robust and reliable simulations of large scale memristor based circuits. The original model contains a piecewise differentiable function in the memductance expression and discontinuous step functions in the state equation. Additionally, the original model does not set a proper upper bound for the state variable and may admit blowing up solutions due to an exponential power term, preventing the use of it for numerically reliable simulations. Considering these drawbacks, we modify the original model so as to i) simplify the memductance function while removing its piecewise differentiable nonlinearity, ii) include a proper window function for the ON state dynamics, which is missing in the original model, iii) modify and bound the exponential power term to prevent an uncontrollable blow-up of the solutions, and iv) apply a process called unification, allowing us to remove the step functions inherent in the model, which is a novelty in state-limited memristor models. We validate the accuracy of the proposed model via DC and transient simulations, dynamic route map analysis and a Spice implementation of an anti-series configuration, showing the applicability of the model. [ABSTRACT FROM AUTHOR]

Schmitt-Triggers (S/Ts) are often utilized to clean noisy analog signals at intermediate voltage values in digital circuits. However, they are vulnerable to metastability, which may cause the same undesired non-digital output behavior that was supposed to be removed in the first place. To enable an efficient characterization of static and dynamic metastability properties of S/Ts (e.g., the metastable voltages, the resolution time constants and the overall total resolution times), this work introduces multiple simulation approaches based on control theory, AC, DC and transient analyses. The accuracy and runtime of all methods are compared and discussed by applying them to an analytically describable idealized circuit model as well as three common circuit implementations. Altogether, this work represents a comprehensive resource for investigating the metastable behavior in S/Ts. Even more, the proposed methods are applicable beyond the S/T, enabling an efficient characterization of static and dynamic metastable behavior in general circuits as well. [ABSTRACT FROM AUTHOR]

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design. [ABSTRACT FROM AUTHOR]

We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes. [ABSTRACT FROM AUTHOR]