Search

In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610 $\mu \text{W}$ and $850~\mu \text{W}$ across the measured deadtime ranges while $\text{C}_{\mathrm {L}} =12$ pF, $\text{V}_{\mathrm {dd}} =3.3$ V, and $\text{f}_{\mathrm {s}}=200$ kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of $150\mu $ m $\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum $\text{T}_{\mathrm {DLH}}$ and optimal $\text{T}_{\mathrm {DHL}}$ at $\text{I}_{\mathrm {Load}} =25$ mA is improved by 12% compared to a converter with a fixed deadtime of $\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ ns. [ABSTRACT FROM AUTHOR]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nVrms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

In this paper, we revisit Boole’s expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole’s expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed. [ABSTRACT FROM AUTHOR]

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using a common-mode feedback (CMFB) circuit. The proposed amplifier employs two P-type and N-type current mirrors to form two self-biasing positive feedback loops resulting in a double transconductance. The bulk terminals of the P-type current mirrors are used as the input nodes to provide a high input dynamic range. The diode-connected topologies of the current mirrors adaptively bias other transistors to cover the lack of the CMFB circuit. To ensure stability, additional current sources are paralleled with the positive feedback structures. A high output voltage swing and a high DC gain are achieved by adding an adaptively biased common-source amplifier as the output stage leading to a class-AB operation. A large signal analysis, in weak inversion, is also done to mathematically describe both small- and large-signal characteristics. The proposed circuit was fabricated using TSMC $0.18 \mu \text{m}$ CMOS technology occupying a silicon area of $113\,\,\mu \text{m}\,\,\times 70\,\,\mu \text{m}$. Experimental results at a supply voltage of 0.4 V show a gain bandwidth of 7 kHz, a DC gain of 60 dB, and a slew rate of 79 V/ms with just 24 nW power dissipation while driving a capacitive load of $2\times 15$ pF. [ABSTRACT FROM AUTHOR]

Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively. [ABSTRACT FROM AUTHOR]

We demonstrate SONOS (silicon-oxide-nitride-oxide-silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a $> 10\times $ gain in energy efficiency over state-of-the-art digital and analog inference accelerators. [ABSTRACT FROM AUTHOR]

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the $1/f$ noise upconversion. A complete $1/f^{3}$ PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shift range is introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm2 and achieves $1/f^{3}$ PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset. [ABSTRACT FROM AUTHOR]

Transistor aging phenomena manifest themselves as degradations in the main electrical characteristics of transistors. Over time, they result in a significant increase of cell propagation delay, leading to errors due to timing violations, since the operating frequency becomes unsustainable as the circuit ages. Conventional techniques employ timing guardbands to mitigate aging-induced delay increase, which leads to considerable performance losses from the beginning of the circuit’s lifetime. Leveraging the inherent error resilience of a vast number of application domains, approximate computing was recently introduced as an aging mitigation mechanism. In this work, we present the first automated framework for generating aging-aware approximate circuits. Our framework, by applying directed gate-level netlist approximation, induces a small functional error and recovers the delay degradation due to aging. As a result, our optimized circuits eliminate aging-induced timing errors. Experimental evaluation over a variety of arithmetic circuits and image processing benchmarks demonstrates that for an average error of merely $5\times 10^{-3}$ , our framework completely eliminates aging-induced timing guardbands. Compared to the respective baseline circuits without timing guardbands (i.e., iso-performance evaluation), the error of the circuits generated by our framework is $1208\times $ smaller. [ABSTRACT FROM AUTHOR]