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This paper proposes a novel all-digital background calibration of timing mismatch for a time-interleaved analog-to-digital converter (TIADC). For two different calibration strategies, the absolute calibration and the relative calibration, the inductive expressions of modulation matrices are derived from the coefficient matrices provided by different estimation methods. Based on the modulation matrix, we develop a digital calibration architecture, which enables the output of TIADC to be modulated firstly before being corrected, so the costly matrix multiplication processing can be avoided. This calibration architecture also enables the estimation process of each channel to be independent and can be executed simultaneously, which accelerates the convergence speed of the timing mismatch. We show the efficiency of the calibration structure by simulations, including examples from the literature. Numerical simulation demonstrates that the convergence speed of the timing mismatch has been improved by at least 27%, compared with the estimation method depending on the specified reference channel. The result of FPGA-based hardware implementation shows that the spurious-free dynamic range (SFDR) is improved by 37.63dB. [ABSTRACT FROM AUTHOR]

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within $77~\mu \text{s}$ , which translates to a 37% reduction in processing cycles from state-of-art. [ABSTRACT FROM AUTHOR]

The paper describes the FPGA implementation of a novel position evaluation algorithm based on the time difference of arrival (TDOA) principle that combines the characteristics of an Orthogonal Frequency Division Modulation (OFDM) symbol with the properties of the Zadoff-Chu mathematical sequences. The resulting system is highly scalable and its characteristics are easily adaptable to different operating scenarios. The algorithm has been implemented using the Stratix IV-E EP4SGX70HF35C3 FPGA, requiring about 112k bit of memory and less than 44k logic elements of which about 16k are registers. The paper describes the algorithm and its FPGA implementation along with experimental results validating the system performance even in the presence of multipath interferences and showing precision in target position estimation that is better than 2 cm. [ABSTRACT FROM AUTHOR]

With the quick expansion of signal bandwidth in communication systems, time-interleaved Analog-to-Digital Converters (TI-ADC) provide quick pathway to very high sampling speed. Nonetheless, mismatches among the sub-ADC channels are major performance limiting factors for TI-ADCs. With the scaling of CMOS processes, all-digital background calibration techniques with blind estimation have been actively pursued in recent years to compensate for the mismatches from TI-ADCs. In this paper, a new all-digital background calibration technique is introduced. The technique achieves blind estimation by exploiting the correlation difference between the signal component and the mismatch spurs. This method can process wideband signals and can be implemented with low calibration overhead. The technique is verified with extensive simulations over a 2GS/s 12bit 16-channel ADC. Simulation shows that, with ADC mismatch spurs over −40dBc, the new technique can reliably suppress the spurs to be lower than −80dBc within the duration of about $1.2\times 10^{6}$ samples with a typical wideband OFDM (orthogonal frequency-division multiplexing) signal. [ABSTRACT FROM AUTHOR]

In order to gain substantial circuit performance improvement in terms of power, speed and area cost, approximate computing is ideally applied in many error-resilient DSP and multimedia applications by relaxing the requirements of exact computation. Fixed-width multipliers are intensively used in those applications, which makes them a good demonstration for approximation through dynamic range reduction. In this paper, a probabilistic prediction based fixed-width Booth multiplier has been proposed. The error compensation function is derived from the probabilistic analysis on the partial products obtained from Booth encoding. By slightly modifying the partial product array with dedicated partitioning, a simple compensation circuit is thus formulated. Compared with the previous works, the proposed design exhibits the best performance-accuracy tradeoff. It achieves at least 27% reduction on the area-energy-delay-error product compared with the other multipliers among various operand lengths. Additionally, the evaluation on 2-Dimensional discrete cosine transform (DCT) circuits indicates that our proposed fixed-width Booth multiplier is applicable for lossy applications with a considerable reduction on hardware expenses and power dissipation while maintaining decent output quality. [ABSTRACT FROM AUTHOR]

Time-interleaving (TI) is a major trend for high-speed ADC designs. The major limitation of TI-ADC is the mismatches among ADC channels. Calibration techniques have been actively pursued to compensate the mismatches. In this paper, we present a new spectral calibration technique for TI-ADC. Although the technique does not run in the background, it does not need external calibration signals and has no constraint on the input signal, which is similar to blind estimation. Compared to benchmark designs, the new technique involves much less calibration hardware overhead, and calibrates all mismatches with much less time. In practice, this efficient technique can run repetitively to track the environment changes. It addresses the needs from practical TI-ADCs well. The technique is verified with extensive simulations on a 2GS/s 12-bit 16-channel ADC. With mismatch spurs over −40dBc, the technique can reliably suppress the spurs to be lower than −80dBc within about 4000 samples without the need of iteration. [ABSTRACT FROM AUTHOR]

This paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error. A new method for recursive estimation of the additive noise variance is also proposed for reliable bias compensation. The mean and mean-square asymptotic behaviors of the algorithm are analyzed and a self-calibration scheme is further proposed to improve the steady-state mean squares error (MSE) due to finite sample effect. Simulations show that the proposed VFF approach offers improved tracking and steady-state MSE performance over the conventional recursive least squares method and its fixed FF counterpart. A linear array architecture is proposed for the realization of this algorithm and several hardware efficient techniques are introduced to avoid the expensive cubic root and division operations required. The proposed algorithm is validated on Xilinx Zynq®-7000 AP SoC ZC702 Field Programmable Gate Array (FPGA). For a 10-tap finite impulse response (FIR) system, the implementation requires only about 11.5k slice look-up table (LUT)s, 4.5k slice registers and 50 DSP48s and it can work up to about 0.58 MHz sample rate with a 200 MHz system clock. The hardware resources are considerably lower than traditional techniques using divider and cubic root realization. The linear array architecture also serves as an attractive alternative to the systolic array in medium to low rate applications due to its reduced hardware usages. [ABSTRACT FROM AUTHOR]

Multiple-clock-cycle, signal adaptive, and fully pipelined hardware design of the optimal (Wiener) space/spatial-frequency (S/SF) filter is developed in this paper. All implementation and verification details, as well as the extensive comparative analysis, are provided. The developed solution optimizes critical design performances related to the hardware complexity, in line with multiple-clock-cycle nature. Variable (signal adaptive) number of clock cycles, taken within the execution in different S/SF points, provides this solution to retain the optimized time requirements, as well as high resolution, selectivity, and estimation quality of the corresponding recently proposed signal adaptive filtering solution. However, as the major contribution, the fully pipelined implementation enables the developed design to additionally improve the time required for execution. The achieved improvement corresponds to a clock cycle per each S/SF point performed within the estimation that results in the significant comparative improvement in execution time of up to 50% in terms of S/SF points lying outside the local frequency of the estimated 2D frequency-modulated signal. The implementation is tested on a highly nonstationary multicomponent signal and is verified by a field programmable gate array circuit design. [ABSTRACT FROM AUTHOR]

Compressed sensing (CS) analog to information converters (AICs) offer key benefits for signal reception or detection when the input signal is sparse. So far AICs have been demonstrated in environments with controlled input signal conditions and with fixed sparsity levels. This paper investigates how to make AICs effectively operate in dynamic environments with changing signal conditions and thus changing sparsity levels. We focus on RF spectrum scanning, where signals or interferers need to be detected across a wide dynamic RF spectrum, but the presented concepts are widely applicable for low-pass and band-pass CS AICs. The number of measurements and hence the number of branches required in a CS RF front end scales with the sparsity level, i.e. the number of signals that need to be detected. In practice this leads to excessively large silicon area for more than a few signals (e.g., six). We introduce the time-segmented quadrature analog-to-information converter (TS-QAIC), a scalable architecture for signal detection in dynamically changing spectrum environments. While our TS-QAIC prototype implements a fixed number of hardware branches, we experimentally demonstrate adaptive thresholding and adaptive time segmentation to adjust its signal detection capability to the sparsity level of the input signal. [ABSTRACT FROM PUBLISHER]

Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper, we introduce a discrete wavelet transform (DWT)-based methodology for a state-of-the-art disparity estimation algorithm that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input images, reducing the number of samples to be processed in subsequent stages by 50%, thereby decreasing computational complexity and improving processing speed. Subsequently, the architecture has been designed based on this proposed methodology and prototyped on a Xilinx Virtex-7 FPGA. The performance of the proposed methodology has been evaluated against four standard Middlebury Benchmark image pairs viz. Tsukuba, Venus, Teddy, and Cones. The proposed methodology results in the improvement of about 44.4% cycles per frame, 52% frames/s, and 61.5% and 59.6% LUT and register utilization, respectively, compared with state-of-the-art designs. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new approach to use a residue number system (RNS) to design an arithmetic unit to parallelize execution of addition and multiplication. The chosen RNS is defined by a moduli set composed of one larger even modulus 2^k and all remaining moduli of the type 2^n-1 , selected to fit into the word size of a typical general-purpose processor, e.g., 32 or 64 b. The RNS operations are implemented in hardware, except for the reverse conversion, which is implemented in software, allowing not only to save hardware area but also offering the ease of run-time changing of the dynamic range, which in turn can result in reducing both power consumption and execution time. Simulation experiments were performed on synthesized seven-operation arithmetic units with varying dynamic range for three applications: constant-coefficient filtering, matrix multiplication, and large Montgomery multiplication. The results show that thanks to smaller modular multipliers, RNS arithmetic units have smaller both area and delay, and, consequently, they allow to achieve up to over 20% energy saving for a constant-coefficient filter application, up to over 28% for the matrix multiplication, and up to 27% for Montgomery multiplication, compared with executions using a positional arithmetic unit. [ABSTRACT FROM AUTHOR]

We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach of deriving physical unclonable functions (PUF) from correction circuits measuring and digitizing nonlinearities of data converters. The often digitally available correction data can then be used to generate a fingerprint of the chip. The general concept is presented and then specifically evaluated on an existing Delta-Sigma $(\Delta\Sigma)$ modulator whose outermost feedback DAC mismatches are greatly influencing the overall performance and thus need correction. The applied mixed-signal correction scheme reveals the intrinsic mismatches which are firstly used to linearize the $\Delta\Sigma$ modulator, but which can also be further analyzed. The intra-Hamming distance is initially determined to values less than 6% at nominal conditions and could be further reduced to less than 2% by applying different encodings. Regarding the distinctness of devices, the inter-Hamming distance is highly stable under all circumstances with a value very close to 50%. Though the influence of varying environmental conditions on the stability of repeated PUF readouts is negligible, inevitable deviations in the correction coefficients increase the intra-Hamming distance with respect to nominal conditions. As a result, 80 highly stable identification bits are obtained from the exemplarily used $\Delta\Sigma$ modulator. [ABSTRACT FROM PUBLISHER]

In this paper, a detection and estimation scheme and its architecture design for synchronization in 60 GHz indoor wireless transmission are presented. With the complementary Golay sequence based preamble structure, the proposed synchronization scheme is designed to detect the preamble and symbol boundary, estimate the frequency offset within a unified architecture. For the very high sampling speed at 60 GHz transmission, the architecture is designed as 8\times-parallelism with feed-forward data path. This architecture supports the single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) transmissions of both IEEE 802.15.3c and IEEE 802.11ad standards. The synchronization module is implemented as a part of a digital baseband receiver for IEEE 802.15.3c. The tolerance of maximum frequency offset is about 114.58 ppm and 171.87 ppm for SC and OFDM mode, respectively. The implementation result shows that it takes about 0.84 mm^2 of area (equivalent to 307 k gate counts). The power consumption is about 59 mW in SC mode and 96 mW in OFDM (HSI) mode when operating at 1.76 GHz and 2.64 GHz chip rate, respectively. [ABSTRACT FROM AUTHOR]

A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 mm^2 and 16.10 mm^2 after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order. [ABSTRACT FROM AUTHOR]

Stereo vision is widely deployed on robots and drones to enable depth estimation at a low cost. The combination of lightweight deep neural network (DNN) and cost volumes algorithm is proved to possess the advantages of both high depth estimation accuracy and speed. However, currently there is no accelerator architecture compatible with both efficient DNN inference and cost generation algorithms such as stereo matching. This work proposes a stereo vision accelerator called Dadu-eye, dedicated to real-time processing of high-resolution image streams. The proposed architecture adopts a pipelined hardware design with the techniques of operation approximation and scheduling-level optimization. First, a cost estimation block is designed to generate cost volumes from both luminance and color information. Second, a super pipelined multiplication and accumulation array with a row scan-based fused-layer convolution scheduling is proposed to perform the encoding and decoding neural network efficiently. Finally, an optical flow block is designed and cooperates with the array to approximately predict half of the frames’ depth to achieve real-time (30fps) processing on 1080p view. Based on the SMIC 40 nm CMOS process, this stereo vision accelerator achieves 5.3 TOPS/W power efficiency and significantly reduces 81% off-chip memory access. [ABSTRACT FROM AUTHOR]

Millimeter-wave (mmWave) communication in combination with massive multiuser multiple-input multiple-output (MU-MIMO) enables high-bandwidth data transmission to multiple users in the same time-frequency resource. The strong path loss of wave propagation at such high frequencies necessitates accurate channel state information to ensure reliable data transmission. We propose a novel channel estimation algorithm called BEAmspace CHannel EStimation (BEACHES), which leverages the fact that wave propagation at mmWave frequencies is predominantly directional. BEACHES adaptively denoises the channel vectors in the beamspace domain using an adaptive shrinkage procedure that relies on Stein’s unbiased risk estimator (SURE). Simulation results for line-of-sight (LoS) and non-LoS mmWave channels reveal that BEACHES performs on par with state-of-the-art channel estimation methods while requiring orders-of-magnitude lower complexity. To demonstrate the effectiveness of BEACHES in practice, we develop a very large-scale integration (VLSI) architecture and provide field-programmable gate array (FPGA) implementation results. Our results show that adaptive channel denoising can be performed at high throughput and in a hardware-friendly manner for massive MU-MIMO mmWave systems with hundreds of antennas. [ABSTRACT FROM AUTHOR]

We propose a progressive radiance estimation engine (PREE) hardware architecture to accelerate the processing of the progressive photon mapping with satisfactory graphic quality. The presented PREE architecture consists of four progressive radiance estimation units (PREUs), approximate full task schedule-oriented hit-point update operation controller (AFTSO-HpUOC) and approximate data-independent schedule-oriented radiance evaluation controller (ADISO-REC). The PREUs accelerate the radiance estimation computation by a pipeline technique and share and configure the hardware resource for hit-point update operation and radiance evaluation. Through AFTSO-HpUOC and ADISO-REC, the data can be efficiently dispatched to achieve better parallelism and the data dependence can be alleviated within the four PREUs, respectively. The core area of the proposed PREE architecture implemented in TSMC 90-nm CMOS process is 1.78 mm2. According to the post-layout simulation results, the implementation achieves 496.79 million hit-point update operations per second (MHpUO/s) and consumes 184 mW at 125 MHz for Cornell box with three balls. [ABSTRACT FROM AUTHOR]

In wireless sensor nodes with a tight power budget, minimizing both the amount of transmitted data and the complexity of the algorithms used for data compression are fundamental in achieving long battery life-time. Compressed Sensing (CS) has been proposed to process incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. We show that the architecture implementing parallel projection-based CS can be reused to realize a linear estimator able to minimize the transmitted data when the primary interest is the acquisition of a scalar feature of the signal rather than its entire profile. Further, we increase the energy-efficiency of the architecture by puncturing the sample stream which allows the duty-cycle of both the analog front-end and the analog-to-digital converter to be reduced. We found that conventional CS acquisition can be made more energy-efficient as it tolerates a certain amount of random puncturing, and also that more substantial power savings can be achieved when estimation is the target and undersampling is optimized by a suitable algorithm. In the latter case, the power consumption of all circuit blocks in the signal chain can be reduced by more than one order of magnitude with respect to the standard solution that samples and transmits raw data for off-board processing. The effectiveness of optimized undersampling is demonstrated in two case studies; first, the estimation of the amplitude of an electrical signal, and second, the estimation of the maximum solar radiation measured by a real-world sensor. [ABSTRACT FROM AUTHOR]