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This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CS value, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2 in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta ($\Delta$) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also digital switching energy for the ADC reset. The $\Delta$ -readout process with the proposed MSB-rounding technique shifts the location of the resolvable range using the previous digital code to increase the hit-rate. Finally, the tri-level split monotonic switching scheme minimizes the CDAC switching activity in predictive residue generation for the $\Delta$ -readout process. A prototype ADC was fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies an active area of 0.17 mm2. At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW. [ABSTRACT FROM AUTHOR]

An integrated, power-saving SAR analog-to-digital converter suitable for image sensor applications is presented in this paper. In comparison with previous works, the proposed, build-in passive correlated double sampling (CDS) and programmable gain amplifying (PGA) technique is superior in power, as it achieves correlated noise cancellation and signal amplification without additional OTAs. Furthermore, inspite of a single-ended signal from the image sensor array, single-ended-to-differential sampling is used to enable symmetrical DAC switching. The adopted LSB-first algorithm, utilizing the strong correlation between neighboring pixels, significantly reduces the energy and number of bitcycles per conversion. Additionally, a comparator with four inputs is adopted to keep the DAC array unchanged, avoiding power consumption from the operation of the initial guess for next quantization. Fabricated using a 65-nm process, the 10-bit ADC occupies a die area of 0.19 mm2. The measured DNL and INL are less than +0.68/−0.45 LSB and +1.07/−1.15 LSB, respectively. Operating at 40 MS/s, the ADC provides an SNDR of 55.7 dB and SFDR of 70.9 dB for signal bandwidths of 17.2876 MHz and consumes $415.2~\mu \text{W}$ from a 1.2-V power supply, resulting in a figure of merit of 21.7 fJ/conversion-step. Additionally, the CDS and PGA functionality are verified to be effective in removing reset level influence and providing gains of −6 dB, 0 dB, and 6 dB. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – \mu \textm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage. [ABSTRACT FROM PUBLISHER]

This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model. [ABSTRACT FROM PUBLISHER]

This paper proposes a fully differential 10-bit energy efficient successive approximation register (SAR) analog-to-digital converter (ADC) by using incremental converting method. The voltage difference of the input between two successive samples is acquired and resolved. A judge window is properly designed, and several conversion steps of significant bits could be skipped when the voltage difference is within the preset window. Thus, the power consumptions of the digital-to-analog converter (DAC), logic circuit, and comparator are greatly saved. Moreover, the differential structure also helps to suppress common mode noise and even harmonic noise. The design is implemented with a standard 0.18- \mu\textm CMOS technology. Test results show that the power consumption of the ADC with the proposed algorithm is reduced by at least 42.8% comparing to the conventional structure. The measured DNL and INL are within 0.29 LSB and 0.80 LSB, respectively. At a 0.6-V supply and a 200-kS/s sampling rate, the ADC achieves an ENOB of 9.34 and a figure-of-merit of 8.87 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the 3\times\sigma offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 \mum 1P6M CMOS technology, which occupies an active area of only 380\times 430\ \mum^2. At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 \mum CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 \muW from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB (ENOB=8.8) at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking, which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13-\mum CMOS technology, the ADC achieved a maximum differential nonlinearity (DNL) of -0.33/+0.56 LSB, maximum integral nonlinearity (INL) of -0.61/+0.55 LSB, effective number-of-bits (ENOB) of 8.8, and a power consumption of 9-\muW. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage (Vcm) and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 mm^2. With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The small capacitor size results in low power consumption. In addition, an on-the-fly programmable dynamic comparator is used for quick comparisons with low noise contributions within the limited power budget. The ADC is fabricated using a 110-nm CMOS process. It consumes 16.47 \muW from a 0.9-V supply at a conversion-rate of 1 MS/s. The measured DNL and INL are within 0.3 LSB and 0.56 LSB, respectively. The measured SNDR and SFDR are at 67.3 dB and 87 dB, respectively. The ENOB performance is 10.92 b, which is equivalent to a figure-of-merit of 8.47 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490\mum\times 7.4\mum and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18\mum technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit. [ABSTRACT FROM PUBLISHER]

A 12-bit successive approximation register (SAR) ADC based on dynamic tracking algorithm and a real-time QRS-detection algorithm are proposed. The dynamic tracking algorithm features two tracking windows which are adjacent to prediction interval. This algorithm is able to track down the input signal’s variation range and automatically adjust the subrange interval and update prediction code. QRS-complex detection algorithm integrates synchronous time sequential ADC and real-time QRS-detector. The chip is fabricated in a standard 0.13 $\mu \text{m}$ CMOS process with a 0.6 V supply. Measurement results show that proposed ADC exhibits 10.72 effective number of bit (ENOB) and 79.63 dB spur-free dynamic range (SFDR) at 10k Hz sample rate given 41.5 Hz sinusoid input. The DNL and INL are bounded at −0.6/0.62 LSB and −0.67/1.43 LSBs. The ADC achieves FoM of 48 fJ/conversion-step at the best case. Also, the prototype is experimented with ECG signal input and extracts the heart beat signal successfully. [ABSTRACT FROM AUTHOR]

An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration technique. The bulk-biasing technique is used in the sampling switch to reduce the influence of the charge injection caused by the top-plate sampling. In addition, the configurable asynchronous processing is employed to extend the flexibility of speed and resolution tradeoff. Moreover, the two-step digital-to-analog converter (DAC) switching method is proposed to reduce the switching energy of the DAC. Prototyped in 180-nm CMOS process, the ADC achieves the 56.7-/61.2-/64.6-dB signal-to-noise and distortion ratio (SNDR) and 72.3-/74.8-/75.5-dB spurious-free dynamic range (SFDR) at 80-/40-/20-MHz sampling frequency with the power consumption of 2.61/2.05/1.77 mW. [ABSTRACT FROM PUBLISHER]

An 8 b 700 MS/s 1 b/cycle asynchronous successive approximation register (SAR) analog to digital converter (ADC) which skips comparator metastability is presented. A delay-shift technique is proposed to shift the delay of comparator to generate a 1.5 b redundancy range and to accelerate comparison speed. This reduces the settling requirement and compensates for the dynamic offset by redundancy. The prototype ADC in 40 nm CMOS technology achieves an SNDR of 43.9 dB at Nyquist rate and consumes 5 mW with a 1.2 V supply. This results in an FoM of 56 fJ/conversion-step. Due to no extra calibration circuit, the core circuit occupies an area of only 0.006 \textmm^2. [ABSTRACT FROM AUTHOR]

An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 \mum CMOS process covers 6–10 bit resolution and 0.5 V–0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300\times 700~ \mum^2. [ABSTRACT FROM AUTHOR]