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This paper proposes an LCCC and CCL compensated wireless servo motor control circuitry utilizing the merits of fundamental and third harmonic. With this circuitry, the motor side needs no additional power supply and controller, which significantly reduces the difficulty of maintenance. Besides, benefiting from the proposing of CCL compensating topology and utilizing of the self-driven circuitry, the secondary operates in fully resonant state and the motor direction control H-bridge is self-driven by the LC frequency selecting circuitry (FSC). Moreover, compared with the conventional motor control circuitry, because of the use of fundamental and third harmonic, the power equalization becomes significantly easier, and zero voltage switch (ZVS) can be realized at the same time; Besides, motion direction control of the motor is simpler with only a single pole double throw (SPDT) at the transmitter side. In addition, system resource consumption is reduced compared with conventional motor drive topologies. In this paper, an 180W prototype is built for experimental verification, and the result shows a good power equalization capability and a transfer efficiency reaching up to 90% at the distance of 10cm. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a novel flexible capacitive power transfer (CPT) system, which has stable output capability when the coupler is deformed. To obtain the flexible coupler structure, the copper foil with the features of light, thin, and cost-efficiency is employed to form the flexible capacitive coupling. To achieve stable output capability, the frequency band selection method and the frequency splitting characteristic are deduced, which indicates that if the system works on optimized natural resonant frequency, moderate deformation of the copper foil coupler could have negligible effects on output power and efficiency. Furthermore, the finite-element analysis (FEA) is employed to simulate the variation of electric field distribution in the flexible coupler. Finally, a prototype is constructed in the laboratory. The copper foil coupler with 60 $\mu \text{m}$ thickness and the dimension of $30\times 16$ cm is adopted, which can achieve more than 147 W power transfer for a 100 mm air gap with the efficiency over 86%. When the bending displacement is within 40 mm, the fluctuations of received power and efficiency are less than 3.6% and 3.1%, respectively. The measured results validate the feasibility of the proposed CPT system for being applied in flexible scenarios. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations. [ABSTRACT FROM AUTHOR]

Eight-switch three-phase post-fault inverter (ESTPI) is widely used as the reconfigured topology of three-phase three-level neutral point clamped DC/AC inverter when open-circuit fault occurs. A key technical challenge for the ESTPI is the post-fault controller design. The existing post-fault control approaches for the ESTPI suffer from the difficulty in trading off the current tracking performance, neutral point voltage (NPV) balancing and common mode voltage (CMV) levels. To solve this problem, this paper proposes an improved predictive current control algorithm. The proposed algorithm contributes to achieve accurate output current tracking while greatly reducing the CMV with a balanced NPV. Simulation and experimental results are presented to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

This paper proposes a distributed cooperative control strategy for cyber-physical microgrids in a distributed sparse network with communication delays by using predictive control theory, which enables each distributed generator (DG) unit to achieve voltage restoration. In the proposed control strategy, we first design a primary droop-free model predictive controller to make the output voltage track its nominal set points timely, with the neighbor-based error information a secondary distributed coordinated predictive controller is then proposed to actively compensate the general communication delays for cyber-physical microgrids caused by low-bandwidth communication networks. Sufficient conditions, in terms of communication network connectivity and control gains for the system stability are derived by using the tools of special matrix theory and algebraic graph theory. The proposed control protocols are fully distributed and can be implemented through a sparse communication network and thus, satisfy the plug-and-play feature of the future smart grid. The effectiveness of the control strategy in compensating communication delays is also verified by real-time simulation experiments in OPAL-RT on a test microgrid. [ABSTRACT FROM AUTHOR]

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell. [ABSTRACT FROM AUTHOR]

This paper presents a 46 nF/10 $\text{M}\Omega $ -range, digital-intensive, reconfigurable RC-to-digital converter (R2CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R2CDC results in 114 aFrms/ $0.37 \Omega _{\text {rms}}$ resolutions and a worst-case temperature-drift of 64.2 ppm/°C over −40 to 125°C. Femto-farad capacitances can be sensed with a relative code-deviation less than 0.16 % even when parasitics vary 30 times the baseline. Implemented in a $0.18 ~\mu \text{m}$ standard CMOS process, the R2CDC consumes 140 $\mu \text{A}$ from a 1 V supply, occupying an active area of $0.175 ~\mu \text{m} ^{\mathrm{ 2}}$. [ABSTRACT FROM AUTHOR]

To improve the voltage and power sharing of distributed generations, the hierarchical controls are widely used in microgrids while the dependent communication network makes it difficult to ensure the performance under limited bandwidth. In this paper, a predictive voltage hierarchical controller is designed. With the delayed secondary PI compensation signals, an inner-loop robust control is designed in the primary controller, ensuring stable voltage tracking. Then, a predictive controller is designed to provide neighbor and local predictions, such that the data integrity is improved by an accurate predictive compensation under bidirectional data-loss. Final case study results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed approach allows a minimum power supply equal to the one of a MCML inverter and we show analytically the advantages in terms of speed and power consumption against the conventional implementation. The approach has been validated with post-layout simulations considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. In particular, OR/NOR gates with 3, 4, and 5 inputs implemented both with the conventional 2-inputs MCML gates implementation (Fin2) and the proposed MF MCML have been compared. Results show a reduction in the power consumption of the MF MCML equal to 3/4, 2/3 and 5/8 for the OR3, OR4 and OR5 logic functions respectively. Moreover, in terms of speed the Fin2 implementation has a delay at least 1.4 worst than the MF MCML, but is generally 1.7 worst than the proposed MF MCML gate. In this paper we have presented a novel approach which allows to implement MCML gates with a fan-in higher than 2 while keeping the minimum supply voltage as low as the one of a conventional MCML inverter. The proposed methodology, named Multi Folded MCML, born out by a generalization of the Folded MCML previously proposed by authors. The approach has been compared against the conventional Fin2 implementation (suited to implement arbitrarily logic function with a low power supply) both in terms of power consumption and propagation delay. The results have clearly demonstrated the advantages provided by the MF MCML. In particular, OR/NOR gates with 3-, 4-, and 5-inputs have been compared considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. Post layout simulation results have shown that the MF gates outperform the conventional implementations in terms of propagation delay for all the considered logic functions. In particular, the propagation delay of the Fin2 implementation has been shown to be at least 1.4 times higher than the one of the MF MCML implementation and even 2 times higher for other logic functions. The power consumption of the MF gates has been shown to be 3/4, 2/3 and 5/8 than the one of the Fin2 implementations for the OR3, OR4 and OR5 logic functions respectively. Hence, the only drawback of the propose techniques seems due to a more complex design procedure. [ABSTRACT FROM AUTHOR]

In this paper, the robust $H_{\infty }$ control problem is studied for the inductively coupled power transfer (ICPT) process with coil misalignment, energy bounded interference and time-varying delay. The problem of coil misalignment between the primary and secondary coils are considered, and the time varying coupling coefficient are described in a sojourn-probability-based switch model. A set of random variables are utilized to describe the sojourn probabilities of the finite modes of the coil misalignment. It should be pointed out that the sojourn probability of the $i$ th subsystem is obtained by the off-line statistical test instead of prescribed by hand, which is of more closer physical significance due to its engineering practice. Corresponding to the proposed switching systems, a set of controllers with time-varying delays are constructed. By resorting to the Lyapunov stability theory, the matrix analysis, and the stochastic analysis tools, the delay-dependent sufficient criteria with less conservatism are derived to guarantee the mean square stability of the ICPT system and the given interference attenuation level $\gamma $. The feedback gains of the desired controller can be readily obtained by using the control toolbox in Matlab software. Three cases of the illustrative examples without exception verify the effectiveness of the suggested modeling method and control scheme. [ABSTRACT FROM AUTHOR]

In this paper, the sensitivity of the neural network (NN) outputs to device parameter uncertainties (non-idealities) in inverter-based memristor (IM) crossbar neuromorphic circuits is mathematically modeled and verified using exhaustive circuit and system-level simulations. The NN sensitivity is obtained by modeling the sensitivity of the IM neuron output to the non-idealities of its circuit elements. The analysis reveals a higher sensitivity of the output voltage of the IM neuron to the non-idealities of the inverters compared to the conductance variation of the memristors. Among the inverter non-idealities, horizontal shift of the inverters voltage transfer characteristic (VTC) shows the highest impact on the output voltage of the neuron. To reduce the accuracy loss due to the variations, a training approach which includes a sensitivity term in the cost function of the training phase, is suggested. The achievable improvements through the said NN training approach are evaluated. In the evaluation, the California Housing, MNIST, and Fashion MNIST datasets are employed. The results show up to 50% reduction in the NN output variations in the presence of circuit elements’ non-idealities. [ABSTRACT FROM AUTHOR]

In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems. [ABSTRACT FROM AUTHOR]

In this paper, a method for offline training of inverter-based memristive neural networks (IM-NNs), called ERIM, is presented. In this method, the output voltage of the inverter is modeled very accurately by considering the loading effect of the memristive crossbar. To properly choose the size of each inverter, its output load and the required slope of its voltage transfer characteristic (VTC) for an acceptable level of resiliency to the circuit element non-idealities are taken into account. The efficacy of ERIM is investigated by comparing its accuracy to those of two recently proposed offline training methods for IM-NNs (RIM and PHAX). The study is performed using IRIS, BCW, MNIST, and Fashion MNIST datasets. Simulation results show that 72% (56%) reduction in average energy consumption of the trained networks is achieved compared to RIM (PHAX) thanks to proper sizing of the inverters. In addition, due to the higher accuracy of the NN mathematical model, ERIM results in significant improvements in the match between the results of high-level modeling and HSPICE simulations while exhibiting lower sensitivity to circuit element variations. [ABSTRACT FROM AUTHOR]

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06 ×/1.08 ×/1.36 × shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03 ×/1.09 ×/1.12 ×/1.15 ×/1.17 × shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33 ×/1.6 ×/2.4 × higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13 ×/1.32 ×/1.37 ×/1.42 ×/1.5 × higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31 ×/2.42 ×/2.55 ×/3.04 × lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead. [ABSTRACT FROM AUTHOR]

In wireless charging devices, different wireless charging standards have caused charging incompatibility, and the utilization rate of the DC voltage at the transmitter is not high, which brings challenges to the application of wireless charging. To solve these two problems, this paper proposes a multi-frequency multi-amplitude (MFMA) superimposition modulation method. This method superimposes multiple frequency signals, and then compares the synthesized signal with a high-frequency triangular carrier to output a square wave voltage signal containing information such as the frequency and amplitude of the pre-output signal. Furthermore, a phase-shifting optimization algorithm is proposed, i.e., based on the proposed MFMA superimposition modulation method, the utilization rate of the DC voltage of the system is improved by reasonably adjusting the initial phase of each frequency. Simulation and experimental results show that the proposed method can output at least four frequencies simultaneously by using a single inverter, effectively reducing the volume of the transmitter, and being compatible with the frequency range of several charging standards. The proposed phase-shifting optimization has a significant effect on improving the utilization of DC voltage with an increase of 44.88%. [ABSTRACT FROM AUTHOR]

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 – 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 – 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training. [ABSTRACT FROM AUTHOR]

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance. [ABSTRACT FROM AUTHOR]

This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip reference clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip reference clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the reference clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a reference clock with nearly temperature-independent pulse width and period. In addition, a $2^{{\text {nd}}}$ -order hybrid time-voltage delta-sigma ($\Delta \Sigma $) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18- $\mu \text{m}$ CMOS, measurement results show that the best (worst)-case temperature accuracy of the clock’s reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/−0.73 °C from −20 °C to −80 °C. The prototype occupies 0.45-mm2 chip area and consumes 1.99- $\mu \text{W}$ from a 1.8-V supply at room temperature. [ABSTRACT FROM AUTHOR]

Ring amplifiers are an advantageous new amplifier architecture, but designing them needs to be done in a time consuming process using manual transient simulations. AC based design criteria are of limit usability, because of their large signal operation. This paper presents an alternative design approach for ring amplifiers. A set of cost functions and parameters is developed and the parameters’ effect on the amplifier’s stability, accuracy and power consumption is explained in detail. The optimization process is derived from a simple ring-amplifier model and a stability criterion. This criterion is analyzed in the context of circuit parameters, design constraints and other ring-amplifier designs. A new battery-based self-biased ring-amplifier architecture is introduced and the first stage integrator of a switched-capacitor Delta-Sigma modulator is realized using the described ring-amplifier architecture. The proposed optimization process is successfully performed using 180 nm and 40 nm technology nodes (second node with two supply voltages) and the three designs are analyzed and compared. The optimization process is derived from a basic ring-amplifier model and can be applied to other ring-amplifier structures. [ABSTRACT FROM AUTHOR]

This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-trigger inverter write assist technique that controls the trip voltage of the Schmitt-trigger inverter. The proposed Schmitt-trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang’s 10T, the Schmitt-trigger-based 10T, and MH’s 9T static random access memory cells, respectively, based on 22-nm FinFET technology. [ABSTRACT FROM AUTHOR]

A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is $9\times $ improvement on the state-of-the-art. [ABSTRACT FROM AUTHOR]

In this paper, we propose two ferroelectric FET (FEFET)-based non-volatile flip-flops (NVFFs). The proposed NVFFs can handle both controlled and automatic per-cycle backup to address sudden power failure. FE layer can be either positively polarized or negatively polarized. Depending on these polarization states, the FE layer can save either “1” or “0.” To depolarize (i.e., negatively polarize) the ferroelectric layer of an n-type FEFET, a negative gate-to-source voltage is needed, which introduces a challenge. We exploit data-dependent source voltage control to achieve both polarization and depolarization. The proposed NVFFs (NVFF-1 and NVFF-2) can store data every cycle, which is necessary for energy-harvesting applications and devices with an unreliable power source. We also present a modified version of NVFF-2 (NVFF-2a) that can backup data in a controlled fashion and facilitate low-voltage normal mode operation. The proposed circuits introduce only three-to-four additional transistors in the design, which offer a lower area-overhead than contemporary standard FEFET-based NVFFs. Moreover, the FEFET-based NVFFs offer low energy (in the order of fJ) and delay (in the order of tens of ps) behavior, which is advantageous in energy-harvesting non-volatile processors. [ABSTRACT FROM AUTHOR]

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing and benefits which follow from its technological attributes, such as nanoscale dimensions, low-power operation, and multi-state programming. At the same time, the design with CMOS is quickly reaching its physical and functional limitations, and further research toward novel logic families, such as threshold logic gates (TLGs), is scoped. In this paper, we introduce a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate two-input, three-input, and four-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing a promise as an alternative hardware-friendly implementation of artificial neural networks. Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used toward an in silico classifier. [ABSTRACT FROM AUTHOR]

To reduce conservative timing margin in digital circuit designs, adaptive techniques based on timing-error detection were proposed to monitor the timing of selected critical paths. However, most of them can respond only to the detected error signals in the next, or a few, clock cycles. Then too, they usually have a large area overhead. In this paper, a low-overhead, 9-transistor transition-detector (TD) is proposed for use at a wide voltage range down to near-threshold voltage. These TDs are inserted at the half-path points of the critical paths as opposed to the conventional endpoints, so that the timing errors in the current clock cycle can be detected in advance to prevent actual timing errors at the endpoints. A half-path insertion point selection method is proposed here, with the middle points merging to reduce the number of inserted TDs. Test chips employing the proposed design approach are fabricated in a 40-nm CMOS process. Silicon measurements demonstrate that the whole design has achieved a 41.2% to 50.5% energy saving at near-threshold voltage as compared to conventional margined design at 0.56 V, and with a small area overhead. Thus, it is an effective method for a low-power and energy-efficient circuit design. [ABSTRACT FROM AUTHOR]

In this paper, tools to study forward invariance properties with robustness to disturbances, referred to as robust forward invariance, are proposed for hybrid dynamical systems modeled as hybrid inclusions. Hybrid inclusions are given in terms of differential and difference inclusions with state and disturbance constraints, for whose definition only four objects are required. The proposed robust forward invariance notions allow for the diverse type of solutions to such systems (with and without disturbances), including solutions that have persistent flows and jumps, that are Zeno, and that stop to exist after finite amount of (hybrid) time. Sufficient conditions for sets to enjoy such properties are presented. These conditions are given in terms of the objects defining the hybrid inclusions and the set to be rendered robust forward invariant. In addition, as special cases, these conditions are exploited to state results on nominal forward invariance for hybrid systems without disturbances. Furthermore, results that provide conditions to render the sublevel sets of Lyapunov-like functions forward invariant are established. Analysis of a controlled inverter system is presented as an application of our results. Academic examples are given throughout this paper to illustrate the main ideas. [ABSTRACT FROM AUTHOR]

Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present a novel synthesis technique to implement ternary logic circuits using 2:1 multiplexers. Initially a methodology, which transforms a ternary logic function into a ternary-transformed binary decision diagram, is presented. This methodology is the basis for the synthesis algorithm that is used to synthesize various ternary functions using 2:1 multiplexers. Results for various ternary benchmark functions indicate that the proposed algorithm results in circuits that have, on an average 79%, and up to 99% fewer transistors when compared with the most recent 3:1 multiplexer-based algorithm available in the literature. Synthesized circuits have been implemented using carbon-nanotube field-effect transistors and simulated in HSPICE. [ABSTRACT FROM AUTHOR]

To mitigate the excess timing margin in conventional digital integrated circuit design, resilient circuits were proposed. The current techniques however either have a large error-detecting register or have difficulty in wide-voltage-range (down to near-threshold) operation. In this paper, we propose a light-weight holosymmetrical transition detector (HTD) that can work reliably at near-threshold to normal VDD with fast response time. Combined with a conventional latch, the HTD-latch is used to replace the end point flip-flop for timing error prediction with an area overhead of only 9.5% over a conventional flip-flop. Besides, we optimize the speculation window and design an adaptive duty-cycle control mechanism to reduce the short-path padding overhead in a resilient circuit. In addition, with voltage scaling, we keep the system working at the point before the first failure by using local detection and global clock gating, which needs neither architectural circuit change nor complicated error recovery mechanism. We apply the above-mentioned three techniques on an eighth-order filter test chip in a 40-nm CMOS process. The measurement results demonstrate that the proposed HTD can work robustly at 0.474–1.1 V. With 4.37% area overhead in total, the proposed resilient technique improves performance by 179.31%/28.2% and energy efficiency by 45.6%/28.1% in a near- $V_{\mathrm {TH}}$ (0.474 V)/super- $V_{\mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins. [ABSTRACT FROM AUTHOR]

Strong physical unclonable function (PUF) transcends the limitations of legacy secure key storage methods as emerging security primitive for cryptography and device identification/authentication. In this paper, a new low power and reliable mono-stable strong PUF is proposed. Its primary entropy is derived from the process variations of the parallel diode-clamped single inverter ring working in the subthreshold region. Due to manufacturing process variations, the mono-stable state of the output voltage of single inverter ring is Gaussian distributed around the half $V_{\text {dd}}$ point. The spread of the Gaussian is broadened by mixing it with another Gaussian distributed trip point obtained from a diode-clamped parallel inverter stage. As the main entropy of the raw response bits is derived from a mono-stable circuit, it has greater immunity to perturbances introduced by operating environments. In addition, as the mono-stable state for the output voltage is a non-linear combination of individual inverter rings, the resilience against machine learning attacks can be improved. The prototype chip was fabricated using a commercial 40-nm CMOS technology. The measurement results show that the power consumption of the 64-bit mono-stable PUF is merely $3.85~\mu \text{W}$. The native bit error rate is <8% at 0.9 ~ 1.3 V and −40~ 90°C, which can be further reduced to <1% using the proposed thresholding technique. The proposed PUF reduces the accuracy of support vector machine and reliability-based covariance matrix adaptation evolution strategy attacks by $36{\times}$ and $75{\times}$ , respectively, over that of arbiter PUF. [ABSTRACT FROM AUTHOR]

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra-low-power level detector, and a boost converter. The energy harvesting system can generate an output voltage of 1 V and delivers a maximum power of $4.5~\mu \text{W}$ from a 60 mV supply. This system has been implemented in a standard $0.18~\mu \text{m}$ CMOS technology, uses neither zero-threshold voltage (normally-on) negative-channel metal-oxide semiconductor nor microelectromechanical systems switches and occupies 3.3 mm2. [ABSTRACT FROM AUTHOR]

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

A CMOS $4\times $ subharmonic mixer (SHM) with an internal phase error correction mechanism operating at mm-wave frequencies is proposed in this paper. The SHM operates with a 81-GHz RF input signal and a 20-GHz local oscillator (LO) signal to produce a 1-GHz output. The single ended input is converted into octet-phase, through an active input balun, an active polyphase filter, and certain phase adders. A phase calibration technique is employed, to compensate the phase deviations due to the circuit mismatches, offering a ±5° phase adjustment between the generated phase shifts. By this technique, a close to optimal performance can be obtained, especially in terms of conversion gain and LO-IF isolation, which can be improved by 1.5 to 7.5 dB and by 5 to 17 dB, respectively. Fabricated in a 65-nm CMOS low-power technology, the prototype exhibits a conversion gain of −8 dB (without using an IF amplifier), a 1 dB compression point ( $\text{P}_{\mathrm {1dB}}$ ) of −10 dBm, a third-order intercept point (IIP3) of 1 dBm, and a noise figure of 15 dB. The power consumption is 213 mW, and port-to-port isolation is >70 dB. The achieved performance compares well with the state of the art at these high frequencies despite the use of a slower CMOS process. [ABSTRACT FROM AUTHOR]

In this paper, a combined analytical-numerical methodology is developed for detecting subharmonic oscillation in H-bridge inverters with an LC filter and under double edge modulation. The prediction of this phenomenon is accomplished accurately by combining analytical expressions and computational procedures to determine the switching instants and the corresponding periodic orbits. Different approximate closed-form expressions for the stability boundary are derived revealing the effect of the parameters of the system on its dynamical behavior and showing that the stability boundary is different from the ones corresponding to single edge modulation strategies such as trailing edge and leading edge modulations. The theoretical results are validated by numerical simulations using a system-level switched model. Also, a prototype is implemented to validate he theoretical derivations and the numerical simulations getting a good matching. [ABSTRACT FROM AUTHOR]

Considering the coupling relationships between transfer power and efficiency in continuous-mode inductive power transfer (IPT) systems, this paper presents a pulse energy injection inverter for IPT systems. With a new topology and parameters tuning, the pulse energy injection IPT system with the proposed inverter can work in switch-mode to decouple transfer power with efficiency. Moreover, the transfer power is only decided by the duty ratio of the semiconductor switch, rather than affected by the transmitting resonator, receiving (Rx) resonator, and load. In this way, the pulse energy injection IPT system holds an operating frequency much lower than the resonant frequency to reduce switch loss and improve transfer efficiency. Experiments verify that the IPT system with proposed inverter maintains a high level efficiency within the middle range and realizes nearly 80% supply to load transfer efficiency even in a weak coupling coefficient ( $k=0.044$ ). Finally, experimental analysis implies that the pulse energy injection inverter is suitable for full-range transmission, and high-Q IPT systems with uncertainty in Rx circuits or load. [ABSTRACT FROM AUTHOR]

An inductive power converter for thermoelectric generator (TEG) is presented in this paper. A novel redundant inverter ring oscillator is proposed to self-oscillate in a very low supply voltage down to 45 mV. An additional self-start assist circuit with a differential clock booster and an exponential charge pump is implemented in the power converter to achieve lower self-start voltage. Boundary continuous-conduction mode, zero current switch (ZCS), and maximum power point tracking (MPPT) features have been incorporated into the power converter. Selective turn-ON dynamical-comparators have been used in ZCS and MPPT circuits to save power and achieve minimum operating supply voltage. Fabricated in 65-nm CMOS process, the chip can self-start at 210 mV. After self-start, only 7-mV input voltage is needed to sustain the power converter operation. With a TEG open circuit voltage of 80 mV and internal resistance of $5~\Omega $ , the chip can provide a maximum output power of 229~\mu \text{W} with end-to-end efficiency of 71.5%. [ABSTRACT FROM PUBLISHER]

Fifth-order T-type resonant converter (RC) topologies for constant current applications are introduced in this paper. Immittance property in passive resonant tanks (PRTs) of the RCs is the key feature for realizing this purpose. In comparison with the lower order PRTs, the fifth-order topologies have more inherent current robustness against load variation, less sensitivity to the parameters variation and current gain tuning ability. At first, resonant networks qualifying the PRT conditions are specified with their topological superiorities description. Without loss of generality, 28 immittance PRTs (IPRTs) are detected as possible candidates that can be used as a voltage source to current source converter. In addition, their immittance operating conditions are analyzed mathematically. For prototyping, a topology has been selected and designed using a method based on minimization of the IPRT elements size. Moreover, closed-form expressions of the output current and voltage/current stresses on the reactive elements are derived and verified for selecting the elements value. The designed prototype is a 150-W constant current RC with tight load regulation ability. Experimental results show that the ZVS operation with low reactive power on the switches as well as minimum losses on the rectifier diodes are achieved in a wide range of load variations. [ABSTRACT FROM PUBLISHER]

Common harmonic oscillator topologies, such as class-B and class-C, are typically unable to meet ultra stringent phase noise requirements, due to the exceedingly large capacitance (and, symmetrically, low inductance) that would be required in the parallel resonator. In this paper, we show that an oscillator making use of series resonators is ideally able to overcome this limitation, with the additional, surprising benefit that the phase noise contribution from the active oscillator core can be made negligible, provided that very good MOS switches are available. [ABSTRACT FROM PUBLISHER]

Reducing circuit design cost and eliminating over-design margin are the two challenges for advancing the Internet of Things (IoT). An RF-dc rectifier and storage capacitors consume 25% or more of the chip area for cost-sensitive power-harvesting-enabled IoT applications. In this paper, we explore a new circuit structure called RF-only logic that permits logic circuits to operate directly from an un-rectified RF source. By eliminating the need for RF-dc rectifier and storage capacitors, RF-only logic helps to reduce cost and design complexity for power-harvesting-enabled applications. The structure and operations of RF-only logic are presented. Its performance, power consumption, and robustness are analyzed through simulation and validated with measurement results. A standard cell library was developed for RF-only logic, and an algorithm was implemented to further improve area efficiency. A ring oscillator and two $4\times 4$ multipliers were fabricated in 0.13- \mu \text{m} CMOS as test structures. The ring oscillator was functionally measured with an RF supply voltage down to 100-mVrms at 1 GHz. The multipliers demonstrate performance improvement and overall area overhead of 16% by implementing the power-supply transistor sharing algorithm. [ABSTRACT FROM AUTHOR]

Ring oscillator (RO)-based physical unclonable function (PUF) is an emerging hardware security primitive but its response reproducibility is susceptible to changes in operating conditions and device aging. Present solutions to increase RO PUF reliability either incur large hardware overhead or require sophisticated RO selection algorithm. This paper exploits the optimal biasing of current starved (CS) inverter for the design of RO PUF with very high reliability against both temperature and voltage variations. With two additional transistors, the CS inverter can be adaptively biased at idle time and in active mode to significantly reduce the overall stress, making the proposed CS RO PUF robust against both environmental condition variations and aging. Without using error correction code, the reliability is further improved by a low-cost proximity detector circuit with a small sacrifice on challenge-response pair space. The correlation between successive RO pairs of different input challenges is also broken by an irregular clocking of the linear feedback shift register used to encipher the input challenges. Based on Monte Carlo simulation in TSMC 40-nm CMOS process, the reliability of native PUF responses has been raised substantially from 89.78% for the regular RO PUF to 95.88% for the proposed CS RO PUF over a broad temperature range of −40°C to 120 °C and ± 20% supply variation. With the proximity detector, the proposed Aging-resistant Current-starved RO (ACRO) PUF can attain 100% reliability statistically by discarding 34.47% fewer challenge-response pairs than the regular RO PUF. It is also ~3.7x more aging resilient than existing aging-resilient RO PUFs with ~2.38x lower power dissipation. [ABSTRACT FROM AUTHOR]

In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologies. [ABSTRACT FROM AUTHOR]

This paper introduces a transregional energy model to estimate the energy consumption of digital designs for voltages widely ranging from nominal down to deep sub-threshold. The model also predicts the optimal voltage at which the minimum energy point (MEP) occurs, and the resulting minimum energy achievable under aggressive voltage scaling. The model provides the energy profile versus voltage based on a few technology-dependent parameters that are extracted through simple circuit simulations, and other few design-dependent parameters extracted from synthesis or Place&Route reports at nominal voltage only. The model captures the effect of input-dependent (e.g., switching activity), technology-dependent (e.g., corner, transistor flavor), and micro-architectural parameters (e.g., logic depth). The model exhibits a typical error below 10%, and is well suited for design exploration under wide voltage scaling, as it avoids detailed and time-consuming multi-corner and multi-voltage iterations. Also, the model provides a quick estimate of the achievable MEP for a given design. Accordingly, the proposed model is a useful tool that supports early selection of the most energy-efficient design options to meet a targeted energy profile at low voltages. [ABSTRACT FROM AUTHOR]

Supply-voltage reduction in digital circuits beyond the minimum energy per operation point is advantageous for supply-voltage-constrained applications and can help to considerably reduce standby power consumption. Schmitt trigger (ST) logic allows for ultra-low voltage (ULV) operation; hardware implementations with supply voltages as low as 62mV have been demonstrated. In this paper, a systematic in-depth analysis of ST logic is presented. First, it is shown that ST logic allows for operation at supply voltages below the ultimate limit of standard digital CMOS circuits, making it—to the best of our knowledge—the only approach proposed to date for operation of digital circuits in this voltage region. The factors critical to the ultimate limit of supply voltage reduction are the ON-to-OFF current ratio of the transistors and the susceptibility to global variability. It is shown that ST logic provides improvements over standard CMOS logic in both of these aspects. The hysteresis that occurs in ST circuits at nominal supply voltage could potentially limit the applicability for ULV operation and is therefore carefully investigated. Furthermore, a systematic approach to optimum sizing of ST gates is presented for the first time. ST gates exhibit inherent overheads with respect to gate area, delay, and leakage, which are carefully evaluated. Compared with standard CMOS gates designed for the same minimum supply voltage, it is shown that ST gates, nevertheless, are the most efficient solution if the target minimum supply voltage is sufficiently low: with respect to area, this limit is at VDD\approx 110\,mV and with respect to power/delay at VDD\approx 75\,mV . [ABSTRACT FROM AUTHOR]

This paper describes a 2.4-GHz digitally-modulated class-D polar power amplifier (PA) with novel circuit techniques to enhance the average power-added efficiency (PAEave) that becomes increasingly crucial to prolong the battery lifetime. The PA features 5+5-b interactive AM-AM modulation between the class-D unit amplifiers and a novel high resolution dynamic matching network (DMN) to improve the back-off PAE. A novel power-gating technique tailored for class-D PAs is also proposed and embedded into each unit amplifier and its driver (tapped inverter chain), alleviating leakage-current suppression, area reduction of the DMN, and direct-powering by a standard 1.5-V AA battery. An high back-off power efficiency is made possible by introducing a multi-bit capacitively-tuned DMN, which adds low loss while improving the PAE of the unit amplifiers using the load-pull optimization. The DMN also can correct the antenna impedance mismatch for better average Pout (Pout,ave) and PAEave under a practical VSWR (2.5:1), and aids to reconfigure the PA between the Pout-optimized and the PAE-optimized modes. For a 20-MHz 64-QAM OFDM output at a typical EVM (< −25 dB), the 65-nm CMOS PA exhibits 40.7% PAEave at a 16.3-dBm Pout. The mode switching is demonstrated as a prospective function for battery lifetime extension. [ABSTRACT FROM AUTHOR]

In energy-constrained applications, SRAM systems operating in the subthreshold region are often deployed to reduce power consumption. Subthreshold SRAM designs, however, confront numerous challenges, such as susceptibility to process variation and reduced ON–OFF current ratio. Statistical modeling of the variation in cell stability is critical in SRAM design, especially, for designs operating in the subthreshold region, where the process and temperature variations are the most pronounced. In this paper, statistical models for estimating the static noise margins (SNMs) of SRAM cells are built from the perspective of a shifted voltage transfer characteristic. Read (hold) SNM of a subthreshold 8T cell is analyzed. It is shown that the distribution of a single-sided read SNM is a weighted sum of several normal distributions instead of a regular Gaussian distribution. The proposed statistical model is verified with simulation results in 65-nm technology. Furthermore, to mitigate performance and yield degradation, an adaptive body biasing circuit is developed. It is demonstrated through simulation that, with a negligible area and power overhead, the proposed circuit achieves a 15% improvement in the worst case read SNM. [ABSTRACT FROM PUBLISHER]

Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a fully-integrated ultra-low-power temperature sensor applicable for use in wearable, environmental monitoring, and Internet-of-Things applications. Temperature is transduced in the proposed design by charging a pair of capacitors with proportional to or complementary to (proportional to absolute temperature or complementary to absolute temperature) current sources, and converting temperature-varying charging times to digital via a time-to-digital converter clocked by an on-chip temperature- and supply-stabilized 30-kHz relaxation oscillator. A low-voltage pseudo-differential dual-loop current reference generator is employed alongside inverter-based comparators to impart supply- and temperature-stable performance at low power. Fabricated in 0.18\mu \textm CMOS, the design operates at 0.6 V and consumes 75 nW at room temperature. Across a temperature range of 0 °C–100 °C, the sensor achieves a best-case (worst-case) temperature accuracy of +0.47 °C/−0.22 °C (+0.62 °C/−1.33 °C) and a resolution of 0.093 °C (0.1 °C). Across a supply range of 0.55–−0.85 V, the sensor achieves an inaccuracy of +0.19 °C/−0.28 °C. [ABSTRACT FROM PUBLISHER]

This paper proposes a 5-b 5-GS/s time-based flash ADC in 65-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantization. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time comparators. The ADC has a low input capacitance and the calibration circuit is included on-chip for suppressing various mismatches. The prototype running at 5 GS/s consumes 7.8 mW from a 1-V supply and achieves a signal-to-noise and distortion ratio of 26.19 dB at Nyquist. The resulting figure of merit is 94.6 fJ/conversion-step and the core area is only 0.004 mm2. [ABSTRACT FROM PUBLISHER]

In this paper, we explore a new approach to synchronization of coupled oscillators. In contrast to the celebrated Kuramoto model, we do not work in polar coordinates and do not consider oscillations of fixed magnitude. We propose a synchronizing feedback based on relative state information and local measurements that induces consensus-like dynamics. We show that, under a mild stability condition, the combination of the synchronizing feedback with a decentralized magnitude control law renders the oscillators’ almost globally asymptotically stable with respect to set points for the phase shift, frequency, and magnitude. We apply these result to rigorously solve an open problem in control of inverter-based ac power systems. In this context, the proposed control strategy can be implemented using purely local information, induces a grid-forming behavior, and ensures that a network of ac power inverters is almost globally asymptotically stable with respect to a prespecified solution of the ac power-flow equations. Moreover, we show that the controller exhibits a droop-like behavior around the standard operating point, thus, making it backward compatible with the existing power system operation. [ABSTRACT FROM AUTHOR]