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This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a novel adaptive second-order sliding mode (SOSM) control method is proposed by combining a new adaptive strategy with the backstepping-like technique. The new adaptive strategy is first constructed by means of the equivalent control for which a sliding-mode-based filter is employed rather than the widely-used low-pass filter such that the parameter restriction under the usage of low-pass filter can be relaxed. Then, by applying the proposed adaptive strategy and the idea of adding a power integrator, an adaptive SOSM method is established to finite-time stabilize the sliding variables. The feature of the proposed SOSM method lies in that the gain will vary with the size of the lumped uncertainty so as to avoid the overestimation of the gain. The stability analysis is given based on the finite-time Lyapunov theory. The theoretical results are finally applied to the voltage regulation problem of a Buck converter. [ABSTRACT FROM AUTHOR]

To overcome the energy and bandwidth limitations of traditional IoT systems, “edge computing” or information extraction at the sensor node has become popular. However, now it is important to create very low energy information extraction or pattern recognition systems. In this paper, we present an approximate computing method to reduce the computation energy of a specific type of IoT system used for anomaly detection (e.g. in predictive maintenance, epileptic seizure detection, etc). Termed as Anomaly Detection Based Power Savings (ADEPOS), our proposed method uses low precision computing and low complexity neural networks at the beginning when it is easy to distinguish healthy data. However, on the detection of anomalies, the complexity of the network and computing precision are adaptively increased for accurate predictions. We show that ensemble approaches are well suited for adaptively changing network size. To validate our proposed scheme, a chip has been fabricated in UMC 65nm process that includes an MSP430 microprocessor along with an on-chip switching mode DC-DC converter for dynamic voltage and frequency scaling. Using NASA bearing dataset for machine health monitoring, we show that using ADEPOS we can achieve 8.95X saving of energy along the lifetime without losing any detection accuracy. The energy savings are obtained by reducing the execution time of the neural network on the microprocessor. [ABSTRACT FROM AUTHOR]

This paper studies the high-order sliding mode (HOSM) control for a general class of uncertain nonlinear systems. Firstly, the standard sliding mode system is extended to a new sliding mode system subject to mismatched terms. The use of the new sliding mode system can reduce the system uncertainties in the control channel and relax the well defined relative degree assumption. Secondly, the conventional constant upper bounds assumption is relaxed to time-varying positive functions, which enables us to obtain a global result. For the new sliding mode system under the new global assumption, a novel HOSM controller, that has a simple relay polynomial form, is then proposed. By introducing a new continuous component in the controller, the discontinuous component of the controller only needs to be selected to suppress the uncertainties and thus a controller with minimal discontinuous component magnitude can be implemented. Finally, strict Lyapunov analysis is provided to show the globally finite-time stability of the closed-loop sliding mode system and an application to Buck converter is presented. [ABSTRACT FROM AUTHOR]

This paper presents a turning-point output voltage (TPOV) prediction method to enhance the reference tracking speed of buck converters for dynamic voltage and frequency scaling (DVFS) application. The optimal reference tracking is modeled, and the TPOV is formulated. The parasitic effects are compensated with the proposed calibration scheme. Reference tracking considering load current changes is evaluated with the proposed end-point determination method. Additionally, this work optimizes the feedback network for smooth loop transition, and incorporates the frequency-locking circuit and the error correction path to address the shortcomings of the hysteretic control. The prototype is fabricated in a 0.13- $\mu \text{m}$ CMOS process with a 1.2-V supply voltage. The converter achieves a near-optimum reference tracking over a wide range of output voltages, from 0.5 to 1 V. Various output voltage steps are measured for different load cases. For a 0.5–1-V output voltage step, with a 90-nH inductor and a 1- $\mu \text{F}$ output capacitor, the up- and down-tracking take 558 and 542 ns, respectively, matching the theoretical result of 533 ns. The prototype achieves a peak efficiency of 93.5%, and over 85% efficiency is measured with $\mathrm {V}_{\mathrm {O}}$ from 0.5 to 1 V and $\mathrm {I}_{\mathrm {O}}$ from 130 to 550 mA. [ABSTRACT FROM AUTHOR]

This paper deals with the $H_{\infty }$ fault detection (FD) problem for a class of buck converter with the transmission-induced multiplicative noises and the event-triggered scheme under the network environment. The model of buck converter is approximated by a nonlinear model, and it is further analyzed based on the electricity knowledge. Due to the dynamic characteristics of network transmission, multiplicative noises need to be considered, which are described as a product of some uncorrelated standardized normal distribution and the transmitted signal. Meanwhile, an event-triggered mechanism is utilized for the purpose of reducing the energy consumption, and an FD observer is designed to detect the fault presented in buck converter. Some novel sufficient conditions are given in terms of linear matrix inequalities to guarantee the robust stability of the FD system, and the $H_{\infty }$ optimal fault tracking performance index is also achieved. Finally, an illustrative example is provided to show the validity and merit of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

This paper describes a method for analyzing the bifurcation phenomena in switched dynamical systems whose switching borders are varying periodically with time. The type of systems under study coven most of power electronics circuits where two or more dynamical systems are cyclically switched according to the interaction of the state variables and some periodically moving borders. In particular, the complex bifurcation behavior of a voltage feedback buck converter is studied in detail. The analytical method developed in this paper allows bifurcation scenarios to be clearly revealed in any chosen parameter space. [ABSTRACT FROM AUTHOR]

Conventionally, inductor current is sensed and quantized before it can be used by digitally controlled DC-DC converters. These are intuitively done by using two separated functional blocks—an analog current sensor and an ADC. A few research works have investigated other ways of obtaining the inductor current information in the digital domain. This paper proposes an on-chip digital inductor current sensor that combines both the inductor current-sensing and quantization into a single functional block. In this way, the redundancies found in the conventional approach can be reduced and optimizations can be made to save chip area and power consumption. An 8-bit digital inductor current sensor has been designed and fabricated with a UMC 0.13~\mum CMOS process. The measurement results show that the digital sensor can provide digital inductor current information with a conversion time of 225 ns. This can be used by a buck converter with a switching frequency up to 4 MHz. The digital sensor has linear and monotonic input-output transfer curve properties with an LSB of 6.79 mA. It consumes current of 700~\muA at 1.2 V supply voltage. [ABSTRACT FROM PUBLISHER]

Digital current-mode control is a dual-loop control which potentially results in a better transient response and thus is more favorable than voltage-mode control. There are only a few publications on how to design and implement a fully integrated digital controller as the on-chip implementation is very challenging, especially for current-mode control. This paper addresses those design challenges and considerations. One of the main challenges is to efficiently sample and quantize both the output voltage and inductor current of the buck converter for control purposes. A time-multiplex scheme is used for the control-loop which enables the converter to work with a single ADC. A modified delay-lock-loop DPWM has been developed for minimizing the mismatch of the delay-cells. This enhances the accuracy at high frequency to prevent limit-cycle. A new algorithm has also been proposed for implementing look-up-table digital compensators with 20% less chip area. A converter with the fully integrated digitally controlled loop, including the single ADC, digital compensators and DPWM, has been fabricated in a CMOS 0.35 \mum process with a chip area of 1049 \mum \times\,1533 \mum. Measurement results show that the buck converter has a load transient response of 20 \mus, which is one of the fastest compared to other state-of-the-art digitally controlled buck converter. [ABSTRACT FROM PUBLISHER]

To study the stability of a nominal cyclic steady state in power electronic converters, it is necessary to obtain a linearization around the periodic orbit. In many past studies, this was achieved by explicitly deriving the Poincaré map that describes the evolution of the state from one clock instant to the next and then locally linearizing the map at the fixed point. However, in many converters, the map cannot be derived in closed form, and therefore this approach cannot directly be applied. Alternatively, the orbital stability can be worked out by studying the evolution of perturbations about a nominal periodic orbit, and some studies along this line have also been reported. In this paper, we show that Filippov's method—which has commonly been applied to mechanical switching systems—can be used fruitfully in power electronic circuits to achieve the same end by describing the behavior of the system during the switchings. By combining this and the Floquet theory, it is possible to describe the stability of power electronic converters. We demonstrate the method using the example of a voltage-mode-controlled buck converter operating in continuous conduction mode. We find that the stability of a converter is strongly dependent upon the so-called saltation matrix—the state transition matrix relating the state just after the switching to that just before. We show that the Filippov approach, especially the structure of the saltation matrix, offers some additional insights on issues related to the stability of the orbit, like the recent observation that coupling with spurious signals coming from the environment causes intermittent subharmonic windows. Based on this approach, we also propose a new controller that can significantly extend the parameter range for nominal period-1 operation. [ABSTRACT FROM AUTHOR]

In this article, first integrated circuit (IC) implementation of parallel synchronized switching harvesting on inductor (p-SSHI) is presented for triboelectric energy harvester targeting 1 Hz to 5 Hz mechanical motions. It is accompanied by on-chip buck and switched capacitor DC-DC converters, all capable of handling 70 V levels. Unlike piezoelectric harvesters, triboelectric nanogenerators (TENGs) can produce very high open-circuit voltages; thus, the proposed system utilizes this property within the technology limits to maximize the extracted power. An in-house manufactured TENG using steel and polytetrafluoroethylene (PTFE) is modeled for sub-5 Hz motions. The energy is extracted and stored in an external capacitance until its voltage reaches 70 V, which is achieved in three press-and-release mechanical cycles. 70-to-2 V down conversion is carried on by 70-to-10 V buck converter followed by a 10-to-2 V switched capacitor DC-DC converter. A chip is manufactured in $0.18~\mu \text{m}$ HV BCD process with an active area of 6.25 mm2. End-to-end peak efficiency is measured as 32.71% for 1 Hz motion with a 722 $\mu \text{W}$ total power delivery to the load for 4 ms. [ABSTRACT FROM AUTHOR]

An ultra-low quiescent current dual-mode buck converter system is designed for IoT application, which includes a double clock time (DCT) and a pulse-width-modulation (PWM) control modes. The proposed DCT mode can reduce the conversion loss over a wide loading range from nA-to-mA and achieve seamless mode transition from DCT to PWM control. Implemented in a $0.18\mu \text{m}$ CMOS, this converter achieves a peak efficiency of 92.7%/94.7% in DCT/PWM and >80% efficiency from $10~\mu $ A to 50 mA (5000x), with a wide input voltage from 2 V to 5 V. A quiescent current of 470 nA including bandgap voltage reference and internal oscillator is achieved. The DCT-to-PWM mode selection mechanism achieves an undershoot of 80 mV at $11~\mu \text{s}$ recovery time when load current jumps from $6.67~\mu \text{A}$ to 50 mA. [ABSTRACT FROM AUTHOR]

This article describes the designing process of a low-cost class-D audio amplifier with digitized global feedback after the output filter, using a signal microcontroller. Various approaches to the feedback-based distortions elimination of class-D amplifiers are discussed. Hardware architecture of the author’s designed class-D amplifier with digital audio input interface, output voltage feedback path relays on SAR-ADC, and output power stage in multiphase bridge tide load configuration is shown. The selection method of the output low-pass filter parameters and power stage phase count was explained. A model of class-D amplifier with PID digital compensator and control loop interfaces is presented. Efficient high-speed digital PID compensator implementation on fixed-point 16-bit DSP core is exhibited. Procedure for control loop gain and phase plots measurements and self-tuning of PID feeding under damped second-order plants is presented along with simulations of loop properties influences on tuning effects. The results of the prototype device measurements such as Bode plots or output voltage frequency spectrum are presented. A big effort has been put on a useful, complete and transparent description for the development process of the presented class-D amplifier arrangement. The described class-D amplifier is the first solution with single feedback control from the output of LC filter based on a microcontroller with embedded ADC and PWM hardware with ensuring full audio bandwidth reproduction width THD distortion level below 0.25% at 1 kHz. The amplifier has been designed with the solicitude of device cost by using low-volume inductors in the output filter and by utilization of the built-in microcontroller ADC and PWM interfaces. [ABSTRACT FROM AUTHOR]

A circuit-oriented geometrical approach in predicting subharmonic oscillation (SHO) of voltage-mode switching converters is presented. It is based on a straightforward graphical analysis of the operation of the converter without using advanced mathematical techniques. It is shown that the slope of the output of the compensator at the trip point is an important factor in determining the onset of SHO. The critical condition of SHO of the buck converter working in continuous conduction mode (CCM) is derived and expressed in terms of circuit parameters that serve as the design guideline for avoiding SHO. The proposed approach is applied to analyze three schemes, namely, proportional, dominant-pole and Type-III compensation. The analysis of SHO in discontinuous conduction mode (DCM) for both the buck and the boost converters are also included to demonstrate the universality of the proposed approach. Crucial Cadence simulation results and measurement results are presented to verify the analysis. [ABSTRACT FROM AUTHOR]

An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 \mum CMOS process verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance comparing to the conventional design. [ABSTRACT FROM AUTHOR]