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This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index. [ABSTRACT FROM PUBLISHER]

Information on the submission of papers for publication in the journal "IEEE Transactions on Circuit & Systems. Part I: Regular Papers" is presented.

Harmonic content modulation of the oscillator output voltage can contribute to flicker noise up-conversion in LC-tuned oscillators. The paper reports a quantitative analysis of the effect in Van der Pol oscillators using the framework of the impulse sensitivity function (ISF). It is shown that most of the up-conversion efficiency results from the first harmonic of the ISF, which is not perfectly in quadrature to the output voltage waveform, and from the first harmonic of the transistor current, which is slightly lagging the voltage waveform. A closed-form expression of 1/f3 phase noise in voltage-limited LC-tuned oscillator is derived that is in good agreement with circuit simulations. The paper also shows that the values of both phase shifts are determined by the non-linearity of the active element and are linked to the relevant oscillator parameters, i.e., excess gain and tank quality factor. [ABSTRACT FROM PUBLISHER]

Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations. [ABSTRACT FROM PUBLISHER]

Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliability and robustness to failures of nanometer integrated circuits. In fact, signal propagation on interconnects slows down as temperature rises; for long wires crossing regions at different temperatures, such as the clock network, thermally induced delay and skew get altered and may result in timing faults. Failures of this kind are difficult to face due to their transient nature. This paper focuses on clock tree design for the class of embedded systems-on-chip with spatially nonuniform but temporally stationary thermal profiles. We contribute two algorithms for the thermal-aware clock network design that take into account on-chip temperature variations of this nature. The experimental results that we have collected on a number of examples and for different thermal profiles show that, in the presence of on-chip spatial temperature gradients, clock trees designed using a standard methodology incur very significant skew violations, thus originating circuit failures. Instead, clock networks designed using the algorithms presented in this paper always satisfy the initial skew bound. [ABSTRACT FROM PUBLISHER]

Dichotomy, or monostability, is one of the most important properties of nonlinear dynamic systems. For a dichotomous system, the solution of the system is either unbounded or convergent to a certain equilibrium, thus periodic or chaotic states cannot exist in the system. In this paper, a new methodology for the analysis of dichotomy of a class of nonlinear systems is proposed, and a linear matrix inequality (LMI)-based criterion is derived. The results are then extended to uncertain systems with real convex poly- topic uncertainties in the linear part, and the LMI representation for robust dichotomy allows the use of parameter-dependent Lyapunov function. Based on the results, a dynamic output feedback controller guaranteeing robust dichotomy is designed, and the controller parameters are explicitly expressed by a set of feasible solutions of corresponding linear matrix inequalities. An extended Chua's circuit with two nonlinear resistors is given at the end of the paper to demonstrate the validity and applicability of the proposed approach. It is shown that by investigating the convergence of the bounded oscillating solutions of the system, our results suggests a viable and effective way for chaos control in nonlinear circuits. [ABSTRACT FROM AUTHOR]

There are mainly two factors responsible for rapidly escalating production test costs of today's RF and high-speed analog circuits: 1) the high cost of high-speed and RF automatic test equipments and 2) long test times required by elaborate performance tests. In this paper, we propose a low-cost signature test methodology for accelerated production testing of analog and RF integrated circuits. As opposed to prior work, the key contribution of this paper is a new test generation algorithm that directly tracks the ability of input test waveforms to predict the test specification values from the observed test response, even in the presence of measurement noise. The response of the device-under-test (DUT) is used as a ‘signature’ from which all of the performance specifications are predicted. The applied test stimulus is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. While existing low-cost test approaches have only been applied to low- and medium-frequency analog circuits, the proposed methodology extends low-cost signature testing to RF integrated circuits by incorporating modulation of a baseband test stimulus and subsequent demodulation of the obtained response to obtain the DUT signature. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester. [ABSTRACT FROM AUTHOR]

We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 × 32 pixels. The convolution processor operates on a pixel array of size 32 × 32, but can process an input space of up to 128 × 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second. [ABSTRACT FROM AUTHOR]

This paper presents a new detailed analysis of low-voltage differential signaling (LVDS) output buffers that are intended for use in high-speed integrated circuits. Three theoretically possible architectures of a LVDS output driver are discussed in rigorous detail, resulting in the recognition of the most power-conserving circuit configuration. An innovative realization of this identified low-power architecture is presented in this paper along with computer simulation results and test lab measurement data. The novel LVDS driver is designed using a unique hetero-junction bipolar transistor structure. Computer simulation results show total current consumption of 6.3 mA for the bipolar driver at a 1-GHz clock frequency while operating from a positive supply voltage between 1.7 and 3.3 V, as well as demonstrate full stage compliance with all the requirements of the IEEE 1596.3-1996 standard. The presented version of the buffer was utilized in a multiplexer/demultiplexer chip set that was fabricated in a modern 50-GHz-fT SiGe technology. Test results of the LVDS output buffer taken from five different chip samples reveal high-quality output eyes with more than 0.99 UI opening and close matching between the measured parameters and simulation results. [ABSTRACT FROM AUTHOR]

This paper presents a spectrally weighted balanced truncation (SBT) technique for tightly coupled integrated circuit interconnects, when the interconnect circuit parameters change as a result of statistical variations in the manufacturing process. The salient features of this algorithm are the inclusion of the parameter variation in the RLCK interconnect, the guaranteed passivity of the reduced transfer function, and the availability of provable spectrally weighted error bounds for the reduced-order system. This paper shows that the variational balanced truncation technique produces reduced systems that accurately follow the time- and frequency-domain responses of the original system when variations in the circuit parameters are taken into consideration. Experimental results show that the new variational SBT attains, in average, 30% more accuracy than the variational Krylov-subspace-based model-order reduction techniques. [ABSTRACT FROM AUTHOR]

Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number of wires. In addition, it has small penalty on the network performance, represented by the average latency and comparable codec area overhead to other schemes. [ABSTRACT FROM AUTHOR]

Memristive oscillators are a novel topic in nonlinear circuit theory, where the behavior of the reactive elements is emulated by the memristor. This paper presents symmetric and asymmetric memristive two-gate relaxation oscillators. First, the analysis of the two series memristors is introduced to study the effect of changing their polarities, as well as the mobility factor to be used in the two-gate relaxation oscillator instead of the RC circuit. The generalized analysis for the proposed memristive two-gate oscillator is introduced, where the generalized expressions for the oscillation frequency and conditions for oscillation are derived then four special cases for different mismatching of the memristors are introduced; showing a perfect matching with the PSPICE simulations. Finally, the discussion and comparison are proposed to discuss the four special cases and MATLAB simulations are also provided to study the effect of the memristance and the mobility ratio between the memristors on the oscillation frequency. [ABSTRACT FROM PUBLISHER]

Provides a listing of current staff, committee members and society officers. [ABSTRACT FROM PUBLISHER]

Provides a listing of current staff, committee members and society officers. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

Provides a listing of current staff, committee members and society officers. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

The article presents guidelines on how researchers can publish their studies on integrated circuits and systems in the future issues of "IEEE Transactions on Circuits and Systems."

This paper introduces a dual-mode digital dc-dc converter combining the predictive and feedforward control with the conventional PID controller to achieve fast transient response and low overshoot. An additional predictive or jerk component is added to the conventional PID controller to speed up the transient response and reduce the settling time by approximately 50%. This predictive term is based on the second derivative of the error signal and introduces zero to the loop response which leads to increased bandwidth and improved phase margin. In addition, a feedforward control is also employed to further improve the transient by evaluating the change in the inductor current during the on and off time of the power transistors. Theoretical analysis and simulations were carried out to analyze the proposed design and algorithm. The proposed design is verified on silicon with a prototype of a digital dc-dc converter fabricated in CMOS 0.18 μ m process. The digital dc-dc converter achieved a settling time of 4 μs and an overshoot of 15 mV for a step-load transient of 450 mA, which are improved significantly as compared to the prior arts. [ABSTRACT FROM PUBLISHER]

As externally powered microsystems become more common, designers need better tools to understand power delivery systems such as non-resonant capacitive coupling. In this paper we present the first general method which allows a designer to easily model power delivery through capacitive coupling. The method uses a power iteration technique which allows one to analyze systems when the time to charge the coupling capacitor is longer than a charge cycle, enabling us to analyze a greater range of systems than previously possible. In fact, we are able to model the entire system with an equivalent resistance. We show that our model accurately reproduces both static and dynamic characteristics of the exact solution and that this model is general, in that it is valid for capacitor charge times that are longer as well as shorter than a charge cycle. This model also reveals several regions of operation where different parameters (e.g., capacitance, frequency and series resistance) dominate, allowing the designer to quickly and intuitively understand the design space for capacitive power transfer. [ABSTRACT FROM PUBLISHER]

In this paper, a novel class of element-wise inverse Jacket transforms (EIJT) with many parameters are proposed for signal length N = 3 × 2r. The EIJT has 2N-1 independent parameters. It is shown that the inverse transform of the proposed EIJT can be easily obtained by taking each reciprocal entry of the forward matrix of Jacket transform and then transposing the resulting matrix. Their fast transforms are also developed. Due to their simplicity, the proposed EIJT transforms may be used in many transform-based applications, where their independent parameters may provide more degrees of freedom such as affording an additional secret key in watermarking and encryption applications. [ABSTRACT FROM PUBLISHER]

Stability conditions for 2-D shift-varying systems are presented. The shift-varying nature of such systems emerges in applications such as adaptive filtering or adaptive image processing, where the coefficients are neither static nor periodic. The forms considered in this paper are the Givone-Roesser and the Fornasini-Marchesini models, both of which are discrete 2-D state-space filters. The sufficient conditions for BIBO stability that are proven herein are an outgrowth of the 1-D time-varying state-space conditions that have been previously established. The nature of feedback in the 2-D space is explored and found to be much more complex than for the 1-D case. However, it is also shown that when every feedback path is guaranteed to satisfy a variation on exponential stability, then BIBO stability of these two models can be assured. Further conditions are also established which engage the Lyapunov equation and guarantee the exponential stability requirement. [ABSTRACT FROM PUBLISHER]

In this paper and in its companion, a novel cut-based decomposition for transfer functions of linear time-invariant circuits is introduced and an invariance property, with respect to the cut, is proven for the set of quantities introduced by this cut-based decomposition. These results naturally lead to a novel feedback theory of electric circuits which, unlike Bode's feedback theory, is based on the unambiguous decomposition of transfer functions. Such feedback theory provides a natural extension to the elementary model of feedback amplifiers based on block diagrams, from system theory to circuit theory, and a natural extension to Blackman's formula. [ABSTRACT FROM PUBLISHER]

A compact-size analog maximum power point tracking (AMPPT) technique is proposed in this paper for high power efficiency in the photovoltaic (PV) system. Combining existing MPPT approaches, we present a fast and accurate tracking performance. Here, a wide-range current multiplier, which tracks the maximum power point (MPP) in the solar power system, is implemented to detect the power slope condition of the solar panel. Experimental results show that the proposed technique can rapidly track the MPP with a high tracking accuracy of 97.3%. Furthermore, the proposed system can connect to the grid-connected inverter to supply ac power. [ABSTRACT FROM PUBLISHER]

In this paper, a single-chip 60-V battery charger prototype is presented. The newly proposed charge mode transition can ensure smooth transitions between incremental current (IC), constant current (CC), and constant voltage (CV) modes. The charger sources a current of 136 mA in CC mode and has an efficiency up to 92% during the charging sequence. Intentional saturation of both the IC and CV regulation loops ensure the stability of the charger throughout the charging sequence. Bonding PAD designed to remove the constraints on the aspect ratio of input transistors as a prevention of antenna effect is also disclosed. The proposed design has been implemented on silicon using the TSMC 0.25 μm 1-poly 3-metal bipolar-CMOS-DMOS (BCD) 60-V process. [ABSTRACT FROM PUBLISHER]

Continuous valued number system (CVNS) has the fulfilment of being used for building resistive-type distributed neural networks (DNNs). CVNS DNNs benefit form scalability and higher noise immunity compared to the conventional DNNs. In this paper, CVNS is used to design synapse-neuron modules to cope with the environment resolution. These modules can be employed as building blocks of distributed neural networks. A 4-3-2 network is designed and trained to justify the functionality of the proposed structure. This prototype is simulated and laid out in 0.18 μm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, the design of fractional delay (FD) filters using the Hermite interpolation is investigated. First, the transfer function of fixed FD filters is obtained from the Hermite interpolation formula by using variable substitution. Then, two implementation methods for the Hermite-based FD filters are presented. One is the derivative sampling scheme using an analog differentiator, the other is the Shannon sampling scheme with an auxiliary digital differentiator. Next, the proposed method is applied to design wide-range variable fractional delay (VFD) filters and some extensions are made. Finally, several numerical examples are demonstrated to show the effectiveness of the proposed Hermite interpolation design method. [ABSTRACT FROM PUBLISHER]

In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are completely insensitive to transient faults at their internal nodes and output node independent of the size and technology of the CMOS transistor. The proposed latches tolerate transient faults regardless of the energy of the striking particle. The proposed latches offer faster speed, higher reliability to transient faults with lower costs regarding power and area than most of the latches recently proposed in the literature. The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch. [ABSTRACT FROM PUBLISHER]

Photovoltaic (PV) energy harvesting is commonly used to power autonomous devices, and maximum power point tracking (MPPT) is often used to optimize its efficiency. This paper describes an ultra low-power MPPT circuit with a novel sample-and-hold and cold-start arrangement, enabling MPPT across the range of light intensities found indoors, which has not been reported before. The circuit has been validated in practice and found to cold-start and operate from 100 lux (typical of dim indoor lighting) up to 5000 lux with a 55 cm2 amorphous silicon PV module. It is more efficient than non-MPPT circuits, which are the state-of-the-art for indoor PV systems. The proposed circuit maximizes the active time of the PV module by carrying out samples only once per minute. The MPPT control arrangement draws a quiescent current draw of only 8 μA, and does not require an additional light sensor as has been required by previously reported low-power MPPT circuits. [ABSTRACT FROM PUBLISHER]

Most of the traditional RF circuits are static or minimally tunable using some digital controllability. For example, high power, low power and shut down modes are available in some commercially available transceivers. If available, the tuning knobs affect different specifications in an interdependent manner, resulting in changing several specifications when only one needs to be tuned. This is not enough for power optimal operation of complete self-aware self-adaptive circuits and systems. Independent or orthogonal tunability of the important conflicting specifications using built-in tuning knobs allow optimal adaptation of the wire-less systems. In this paper we demonstrate the design and benefits of orthogonal tuning knobs using an inductorless LNA as a test vehicle. The design of an orthogonally tunable LNA is discussed that has a 14 dB Gain tuning range and 30 dB OIP3 tuning range as its power consumption goes down by 20×. Measurement results on this LNA validate the concept of orthogonal tunability. Use of this orthogonally tunable LNA within an adaptive wireless receiver framework shows power savings of 2× compared to a static system and an extra savings of 22% compared to a traditional nonorthogonal adaptive system. [ABSTRACT FROM PUBLISHER]

In this paper a 1-V supply, 15-bit ΔΣ ADC design for audio applications is presented. The second order CIFB ΔΣ modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 μm CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 μW and the decimator consumes 170 μW. The core area of the ADC is 0.5 mm2. The modulator occupies 0.3 mm2 and the decimator occupies 0.2 mm2. [ABSTRACT FROM PUBLISHER]

The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage. [ABSTRACT FROM PUBLISHER]

In this paper, a single compensation formula of adaptive conditional-probability estimator (ACPE) applied to fixed-width Booth multiplier is proposed. Based on the conditional-probability theory, the ACPE can be easily applied to large length Booth multipliers (such as 32-bit or larger) for achieving a higher accuracy performance. To consider the trade-off between accuracy and area cost, the ACPE provides varying column information to adjust the accuracy with respect to system requirements. The 16-bit ACPE Booth multiplier with w = 3 reduces 28.9% silicon area with only 0.39 dB signal-to-noise ratio (SNR) loss when compared with post-truncated (P-T) Booth multiplier. Furthermore, the ACPE Booth multipliers are applied to two-dimensional (2-D) discrete cosine transform (DCT) to evaluate the system performance. Implemented in a TSMC 0.18 CMOS process, the DCT core with ACPE (w = 3) can save 14.3% area cost with only 0.48 dB peak-signal-to-noise-ratio (PSNR) penalty compared to P-T method. [ABSTRACT FROM PUBLISHER]

Most wavelet filters reported in the literature have irrational coefficients. Hardware implementation can be simpler if the filter coefficients are rational valued. In this paper, we present novel methods to rationalize both orthogonal and biorthogonal filter coefficients with perfect reconstruction and vanishing moments preservation. Rational orthogonal filter coefficients are obtained using lattice structures. Rational biorthogonal filter coefficients are obtained using the complementary filter technique in which one set of filter coefficients is expressed in terms of the other. The rationalized filters have characteristics that are very close to the original irrational filters. The techniques are simple yet general enough to be used for almost any filter bank unlike the techniques in previously reported works. [ABSTRACT FROM PUBLISHER]

In a conventional analog adaptive forward equalizer (FE), parasitic capacitance introduces an undesired RC pole at the output node of the equalizer. At high data rates, this pole can introduce intersymbol interference (ISI) that degrades performance. This paper considers the effect of the parasitic pole and presents two approaches to deal with the parasitic pole. The first approach uses an extra tap in the FE; the second uses chopping. Also, the filtered-x LMS (FX-LMS) algorithm is used to allow the equalizer to adapt and correct for the parasitic pole. Implementations of the FX-LMS algorithm and the chopper technique are presented. The conventional and new architectures and various adaptation algorithms are compared via simulation. [ABSTRACT FROM PUBLISHER]

Aiming for the simultaneous realization of constant gain, accurate input impedance match, and minimum noise figure over a wide frequency range, the circuit topologies and detailed design of two broadband dual-loop negative feedback power-to-current low noise amplifiers (LNAs) are presented in this paper: 1) a resistive indirect-feedback power-to-current LNA, which requires an active part with two output terminal pairs, and 2) a transformer feedback power-to-current LNA, which requires a transformer in its current feedback path having a high turn ratio with high magnetic coupling. For both LNAs the feedback networks and active part implementations are discussed in detail. It is shown that for this purpose a novel stacked transformer can be realized using only two metal layers. The two LNAs are designed to be implemented in a 0.2 m GaAs p-HEMT technology process to verify the theory presented. Counter measures are applied to deal with the effects of bond wires and the effects of transformer parasitics on the circuit performance are analyzed. Simulation results show that the resistive indirect-feedback power-to-current LNA exhibits a 0.6-0.8 dB noise figure, an input return loss well below dB, a 200 mS voltage-to-current gain (which corresponds to 23 dB power gain for a 50 load) from 0.3 GHz to 4 GHz, a dBm third-order input intercept point (IIP3) and a 23 dBm second-order input intercept point (IIP2) at 2 GHz. It consumes 73 mA current from a 4 V power supply. The transformer-feedback power-to-current LNA achieves a 0.5-0.8 dB noise figure, an input return loss of less than dB, a 22 dB power gain from 0.8 GHz to 4 GHz, and a 0 dBm IIP3 and 22 dBm IIP2 at 2 GHz while drawing 53 mA current from the 4 V power supply. [ABSTRACT FROM PUBLISHER]

Novel nonvolatile universal memory technology is essential for providing required storage for nanocomputing. As a potential contender for the next-generation memory, the recently found “the missing fourth circuit element,” memristor, has drawn a great deal of research interests. In this paper, by starting from basic memristor device equations, we develop a comprehensive set of properties and design equations for memristor based memories. Our analyses are specifically targeting key electrical memristor device characteristics relevant to memory operations. Using our derived properties, we investigate the design of read and write circuits and analyze important data integrity and noise-tolerance issues. [ABSTRACT FROM PUBLISHER]

This paper presents a sub-Nyquist rate sampling receiver architecture that exploits signal sparsity by employing compressive sensing (CS) techniques. The receiver serves as an analog-to-information conversion system that works at sampling rates much lower than the Nyquist rate. A parallel-path structure that employs current mode sampling techniques is used. The receiver performance is quantified analytically. Useful and fundamental design guidelines that are unique to CS are provided based on the analytical tools. Simulations with a 90-nm CMOS process verify the theoretical derivations and the circuit implementations. Based on these results, it is shown that an instantaneous receiver signal bandwidth of 1.5 GHz and a signal-to-noise-plus-distortion ratio of 44 dB are achievable. The receiver power consumption is estimated to be 120.8 mW. A comparison with state-of-the-art high-speed analog-to-digital conversions reveals that the proposed approach improves the figure of merit by a factor of three if the signal exhibits a 4% sparsity. [ABSTRACT FROM PUBLISHER]

This paper presents a tutorial overview of \Sigma\Delta modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge \Sigma\Delta architectures, with emphasis on their application to the next generation of wireless telecom systems. [ABSTRACT FROM PUBLISHER]

Rotary traveling-wave oscillators (RTWOs) are a new transmission-line based approach to gigahertz rate oscillators. This paper presents the fundamental theory of RTWOs in both the weakly nonlinear and strongly nonlinear regions of operation, including their multimode characteristics, quality factor, nonlinearity, and edge rate of the oscillating waveform. Finally we use the theory to derive analytic expressions for thermally induced phase noise. Our theoretical results are then compared with accurate simulations. [ABSTRACT FROM PUBLISHER]

The main focus of this paper is the implementation of mixed-signal peak current mode control in low-power dc–dc converters for portable applications. A DAC is used to link the digital voltage loop compensator to the analog peak current mode loop. Conventional DAC architectures, such as flash or \Delta\Sigma are not suitable due to excessive power consumption and limited bandwidth of the reconstruction filter, respectively. The charge-pump based DAC (CP-DAC) used in this work has relatively poor linearity compared to more expensive DAC topologies; however, this can be tolerated since the linearity has a minor effect on the converter dynamics as long as the limit-cycle conditions are met. The CP-DAC has a guaranteed monotonic behavior from the digital current command to the peak inductor current, which is essential for maintaining stability. A buck converter IC, which was fabricated in a 0.18 \mu \m CMOS process with 5 V compatible transistors, achieves a response time of 4 \mu \s at fs=3\ \MHz and Vout=1\ \V, for a 200 mA load-step. The active area of the controller is only 0.077 \mm^2, and the total controller current-draw, which is heavily dominated by the on-chip senseFET current-sensor, is below 250 \mu \A for a load current of Iout=50\ \mA. [ABSTRACT FROM PUBLISHER]

A general transposed series-parallel topology of a switched-capacitor converter is presented and analyzed in this paper. This topology evolved from the conventional series-parallel through rectangular matrices based topologies to partial arbitrary matrices which are constructed of different size strings of capacitors to arbitrary matrices, based on a bank of equally valued capacitors. Theoretically, these topologies have a large number of dc/dc voltage ratios, which lead to the capability to achieve very accurate fixed dc/dc voltage ratios. These topologies also have the capability for “fine tuning” when voltage regulation is necessary. For the general transposed series-parallel topology, it is shown that the number of possible dc/dc voltage transfer ratios escalates exponentially with an addition of each capacitor as the sum of partition functions. Therefore, relatively fewer components are required for an assumed accurate voltage ratio. Dispersion of parameters in the capacitance value is considered. Small ripple analysis, losses calculations and efficiency considerations are also discussed. Simulations are performed for 2.2 and 2.25 voltage ratios. The simulations are in good agreement with the theoretical calculations. [ABSTRACT FROM PUBLISHER]

Address Event Representation (AER) is an emergent technology for assembling modular multiblock bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since the introduction of the technology. Spatial-contrast AER retinae are of special interest since they provide highly compressed data flow without reducing the relevant information required for performing recognition. The reported AER contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighborhood. This resulted in compact circuits but with the penalty of all pixels generating output signals even if they sensed no contrast. In this paper, we present a spatial-contrast retina with a signed output: Contrast is computed as the relative difference (not the ratio) between a pixel's local light and its surrounding spatial average and normalized with respect to ambient light. As a result, contrast is ambient light independent, includes a sign, and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast-computation circuit is based on Boahen's biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive-current-based biasing. As a result, the contrast-computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. The retina includes an optional global reset mechanism for operation in ambient-light-independent Time-to-First-Spike contrast-computation mode. A 32 \times 32 pixel test prototype has been fabricated in 0.35-\mu\m CMOS. Experimental results are provided. [ABSTRACT FROM PUBLISHER]

Digital receiver frontends have emerged as a possible solution for the next-generation serial I/O receiver design in advanced CMOS technologies. The challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. With a power budget of < 20~\mW/Gb/s, the feasibility of an ADC-based receiver is limited by the high-speed analog-to-digital converter (ADC) and complex digital processing in current fabrication technologies. In this paper, various designs and architectures for each component of an ADC-based receiver and their performance trade-offs are discussed. The design requirement of an ADC and digital processing can be relaxed with the aid of simple mixed-mode circuitry. More complex digital processing techniques are becoming feasible with the scaling of CMOS technology. However, the improvement from scaling is limited by the substantial leakage current, and the rate of improvement is slowing beyond 32 nm technology node. [ABSTRACT FROM PUBLISHER]

Soft errors are becoming an increasingly important issue for circuit reliability. Traditional techniques to protect against soft errors, like triple modular redundancy (TMR), have a large cost in terms of area and power. This has motivated the development of specific protection techniques for various types of circuits. In this paper, techniques to protect adaptive filters are presented, which provide reasonable reliability with reduced cost and power consumption. An adaptive equalizer case study is used to discuss and evaluate the proposed techniques in terms of both protection and cost. [ABSTRACT FROM PUBLISHER]

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges. [ABSTRACT FROM AUTHOR]

One of the factors limiting the performance of continuous-time sigma-delta modulators (CTSDMs) is clock jitter. This jitter can be classified as synchronous and accumulated/long-term jitter. A clock that is derived from a phase-lock loop contains both types of jitter. In this paper, we present a framework that can be used to obtain the output spectrum in the presence of jitter, either synchronous or accumulated or a combination of both. First, a general expression for the output power spectral density (PSD) of the CTSDM in the presence of clock jitter is derived. Based on this, analytical expressions for the output PSD are obtained for particular cases of synchronous and long-term jitter. These are validated against behavioral simulations. [ABSTRACT FROM AUTHOR]

This paper presents a new fully integrated sensing interface and signal-conditioning application-specific integrated circuit (ASIC) for automotive accelerometers based on an "injection-nulling switch" (INS) technique. The INS technique simplifies the design of both the switched-capacitor (SC) sensing amplifier and its supporting building blocks without jeopardizing its performance. This is done by counteracting the impact of charge injection and clock-feedthrough effects on sensitivity, resolution, and offset. It also decreases the number of opamps, capacitors, and switches being used. This results in reduction of power consumption, potential switching noise, and kT/C noise (sampled thermal noise which increases with the number of SC pairs being used) in the ASIC. A two-chip approach has been adopted in the implementation, with ±50 g sensing element and ASIC. The built-in trimming circuitry and signal-conditioning blocks, which includes a self-test circuit, are implemented internally to eliminate the need for external components. The experimental results have shown that the sensing system IC has achieved a power consumption of 10 mW (2 mA at 5 V), a maximum noise root spectral density of 11.87 µVpk / √Hz equivalent to rms noise root spectral density of 0.187 mg/ √Hz at 15.63 Hz, a signal-to-noise dynamic range of 77 dB for 500-Hz bandwidth and 74 dB for 1-kHz bandwidth based on 50 g, and a maximum clock noise of 1.562 mV. The die size of the ASIC is 2.8 mm × 2.3 mm using a standard 0.6-µm CMOS technology. [ABSTRACT FROM AUTHOR]