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This paper presents a digital battery management unit (BMU) with built-in resistance (BIR) compensation, modulated frequency detection (MFD), and multi-mode protection (MMP) techniques to realize fast, efficient and safe charging. The charger incorporates the proposed BMU based on the low-dropout (LDO) regulator. With BIR compensation, a large rated current in the proposed pulsed constant current (PCC) mode charges the battery, and reduces the charging time by omitting the constant-voltage (CV) mode. The MFD technique allows continuous monitoring and obtains precise BIR compensation with accelerating sampling speed. The MMP technique can alleviate safety concerns while charging, including over-voltage protection (OVP), over-current protection (OCP), and the proposed accidental fluctuation protection (AFP). The digital BMU, implemented in 28 nm CMOS, occupies 0.014 mm2 of silicon area. Experimental results show that the proposed circuit saves 73.3% of charging time with 1.5A charging current, and 21.5% ADC dynamic power with 1A charging current. For the digital controller IC, the power consumption is $59.1~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

Diffusion-driven instabilities with pattern formation may occur in a network of identical, regularly-spaced, and resistively-coupled cells if and only if the uncoupled cell is poised on a locally-active and stable operating point in the Edge of Chaos domain. This manuscript presents the simplest ever-reported two-cell neural network, combining together only 7 two-terminal components, namely 2 batteries, 3 resistors, and 2 volatile NbOx memristive threshold switches from NaMLab, and subject to diffusion-driven instabilities with the concurrent emergence of Turing patterns. Very remarkably, this is the first time an homogeneous cellular medium, with no other dynamic element than 2 locally-active memristors, hence the attribute all-memristor coined to address it in this paper, is found to support complex phenomena. The destabilization of the homogeneous solution occurs in this second-order two-cell array if and only if the uncoupled cell circuit parameters are chosen from the Edge of Chaos domain. A deep circuit- and system-theoretic investigation, including linearization analysis and phase portrait investigation, provides a comprehensive picture for the local and global dynamics of the bio-inspired network, revealing how a theory-assisted approach may guide circuit design with inherently non-linear memristive devices. [ABSTRACT FROM AUTHOR]

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index. [ABSTRACT FROM PUBLISHER]

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed. [ABSTRACT FROM AUTHOR]

An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis ANN, two analysis ANNs and a proposed self-inspection machine (SIM). For a given design request, the SAM synthesizes a layout first, followed by analyzing the performance of the layout automatically, and finally improves the layout confidence through self-inspection. Compared to the modeling functions of analysis ANN, the synthesis ANN behaves as an inverse model, of which the inputs are desired inductor performances while the outputs are geometrical parameters of the layout. However, multi-value problems might occur in obtaining geometries of inductors, suggesting with evidence from mathematic relationships between geometrical and electrical parameters of an inductor. A multi-valued training dataset will mislead the synthesis ANN, resulting in unqualified layouts. To deal with this issue, a solution space contraction technique (SSCM) is also proposed. Furthermore, the SIM suspends most of the failures by comparing the output of analysis ANN back to the input of synthesis ANN. An electromagnetic simulation tool is used for experiments, and the effectiveness of the proposed SAM is proven by 6,500 inductor samples. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

In this paper, a novel saturation-based control method is proposed for high-order sliding mode (HOSM) dynamics with upper-triangular nonlinearities. Firstly, a new HOSM dynamics with upper-triangular nonlinearities is constructed based on the traditional HOSM dynamics, so as to reduce the uncertainties in the control input channel. Then, a HOSM controller is established by means of the adding a power integrator method such that the new HOSM dynamics is locally stabilized. Finally, the saturation-based controller is constructed by a combination of the saturation technique and the local HOSM controller to guarantee that the sliding variables can converge into a domain of attraction in a finite time and retain inside it thereafter. The rigorous stability analysis is made by the Lyapunov theory. A simulation example is also given to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid precoding processor for millimeter wave (mmWave) multiple-input-multiple-output (MIMO) communication systems. The proposed architecture supports 64 antennas with 4-to-8 RF chains, and 4-bit phase resolution for each phase shifter in the analog beamformer. A polar decomposition (PD) engine is designed to achieve a 2.4-to- $8.6\times $ lower latency with 1.5-to- $1.7\times $ less normalized gate count compared to the singular value decomposition (SVD)-based implementation for the same functionality. Multiplicands are combined to reduce 55% area by utilizing the distributive property. Approximate phase extraction and low-precision multiplication for quantized phase extraction are adopted, which leads to 43% and 41% area reductions, respectively. The proposed hybrid precoding processor is designed in a 40-nm CMOS technology. It delivers a throughput of up to 10,288 kMat/s and consumes 170.9 mW at 278 MHz. It outperforms the state-of-the-art hybrid precoding processors with 5.5- $13.7\times $ higher normalized area efficiency and 6.9- $38.4\times $ lower normalized energy. [ABSTRACT FROM AUTHOR]

This paper proposes a fingerprint scanning analog front-end (AFE) for a $41\times32$ under-glass mutual-capacitive fingerprint sensor. As the mutual-capacitive fingerprint sensor is a smaller version of a projected-capacitive touch screen, this transparent fingerprint sensor can be mounted underneath screen cover glass. However, such glass significantly diminishes the signal-to-noise ratio (SNR) of fingerprint scanning AFE in proportion with increasing glass thickness. Moreover, external noise interferences from the display and charger are severe in displays with thin form factor. The proposed fingerprint scanning AFE can achieve a 17 atto-farad capacitance resolution using high-voltage (20 V) transmitters and multi-channel receivers comprising a pipelined readout amplifier, mixer, and second-order low-pass filter (128 kHz). A differential sensing structure and band-pass filtering are employed in the receiver front-end to enhance the noise immunity. A differential phase-encoded sequential driving transmitter with a proposed on-chip replica channel mitigate random offsets in the readout amplifier with high matching accuracy. Measurement results show that the fingerprint scanning integrated circuit (IC) fabricated by a $0.18 ~\mu \text{m}$ BCD (Bipolar-CMOS-DMOS) process achieved a 13.4 dB SNR at a frame rate of 120 Hz under a 0.2 mm-thick cover glass. The prototype IC provides 20 VPP noise immunity from 0 to 500 kHz and consumes 23.2 mW from a 3.3 V supply. [ABSTRACT FROM AUTHOR]

This paper investigates the exponential synchronization (ES) problem for complex networks (CNs) under an intermittent adaptive event-triggered control (IAE-TC) strategy which is based on dynamic IAE-TC during the control activation intervals. In this control mechanism, the intermittent controller has adaptability to the evolution results of the controlled networks and is activated only when the event-triggered condition is violated. Then, by employing this kind of control strategy and the Lyapunov method, some sufficient conditions are proposed to achieve the ES of CNs and it is proven that the Zeno behavior can be eliminated. Besides, an application about the islanded microgrid system and some numerical simulations are provided to verify the effectiveness of the derived theoretical results. Moreover, in the numerical simulations, it is shown that the dynamic IAE-TC strategy can decrease the number of event-triggered instants more availably than the static one. [ABSTRACT FROM AUTHOR]

This paper investigates the formation control problem for a group of nonholonomic mobile robots (NMRs) with unknown parameters and deception attacks. The information transmitted among different robots is represented by a directed graph and only a subset of the robots can obtain the full information of the desired trajectory directly. For those robots which cannot access to the reference trajectory directly, distributed estimators are designed to estimate the unknown trajectory information by using only locally available information. Besides, the sensor-to-controller transmitting channels and the communication among connected robots are suffering from deception attacks. Adaptive laws and compensation terms are designed to handle the issue of attack-induced uncertainties. Then, a novel distributed resilient formation control scheme is designed, based on which a sufficient condition is developed to guarantee that the formation errors converge to a compact set and all the closed-loop signals are bounded. Experimental results are given to validate the theoretical studies. [ABSTRACT FROM AUTHOR]

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems. [ABSTRACT FROM AUTHOR]

Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design. [ABSTRACT FROM AUTHOR]

In this paper, we present an approach to nonlinear system approximation, called the lattice trajectory piecewise linear (LTPWL) model. The approach involves determining a lattice piecewise linear (PWL) approximation to the state trajectory of a nonlinear system. It has been shown in the literature that the lattice PWL expression can represent any PWL function in any dimension. After the LTPWL approximation has been obtained, the order of each model piece is reduced using a Krylov projection technique. Compared to existing trajectory piecewise linear (TPWL) models, which are quasi-PWL in the whole region, LTPWL models are virtually linear in each subregion. Besides, the single output LTPWL model can be seen as a special kind of TPWL model, in which only one weight is 1, and the other weights are 0. In general, for multiple output LTPWL model, the weights set to be 1 for each component are different, which makes the LTPWL model more flexible in approximation of nonlinear function. The proposed strategy is applied to simulate diode circuits, and the experimental results show that the performance of the LTPWL model is better than that of the traditional TPWL model in terms of approximation accuracy and generalization ability. [ABSTRACT FROM AUTHOR]

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ($SS_{avg}$), off current (${I} _{OFF}$), and on current (${I} _{ON}$) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope. [ABSTRACT FROM AUTHOR]

This paper develops fundamental limits of digital phased arrays and proposes to use this as a map for the future technology investment in this area. Phased arrays, which are becoming ubiquitous in everything from vehicles, to communication systems including cell phones, to drones, satellites, and of course military applications. There is a recent trend toward digital phased arrays where each element in the antenna array is digitized. This allows monolithic integrated circuit integration as well as providing new capability due to digital signal processing. Digital phased arrays are increasingly being implemented with reconfigurable logic. Digitization and reconfigurability comes at a cost of power, which is increasingly becoming the limitation in these systems. This paper develops the fundamental energy limits of digital computation, applies this to phased arrays, and discusses directions for potential future digital phased array development. [ABSTRACT FROM AUTHOR]

This paper proposes a new design methodology to explore the state-of-the-art approximate adders for accelerator architectures conceived in the realm of multiplier-less multiple constant multiplication optimization problem. The proposed methodology is composed of: 1) a search heuristic to seek faster and feasible approximate configurations for the architectures under evaluation; 2) low-power techniques regarding hybrid approximate adders design for accelerators based on trees of shift-and-add operations; 3) high-performance evaluation by exploring parallel prefix adders and low power analysis through the use of the adder optimized by a commercial synthesis tool in the precise part of the approximate adders; and 4) energy efficiency analysis by considering both the approximate techniques and voltage over scaling estimation. Furthermore, improvements are proposed for the state-of-the-art approximate adders under evaluation in this paper. Two case studies are considered to assess the proposed methodology: 1) Gaussian image filter and 2) Sobel operator. The precise and approximate image filters were described in very high-speed integrated circuits hardware description language regarding the proposed methodology. Results are shown after synthesis to a 45-nm standard cell-based technology, where energy reductions ranging from 7.7% up to 73.2% were experienced for multiple levels of quality considering the applications under analysis. [ABSTRACT FROM AUTHOR]

This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes. [ABSTRACT FROM AUTHOR]

The continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells. [ABSTRACT FROM AUTHOR]

First-in first-out (FIFO) queues are ubiquitous building blocks in modern system-on-chips. Big FIFOs are often realized as static random access memories (SRAMs), and in many cases account for a significant portion of the area and power consumption of integrated circuits (ICs). Gain-cell embedded DRAM (GC-eDRAM) technology is an embedded memory alternative to the pervasive SRAM technology in ICs. It consumes less silicon area and less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. In this paper we leverage the unique access patterns implied by the FIFO scheme to design a FIFO realized with GC-eDRAM. We show that such a FIFO is functionally indistinguishable from a FIFO realized with SRAM. The proposed FIFO has no access blockage time due to refresh, and no data integrity issues, and so can be used as an out-of-the-box replacement for FIFOs in existing and future designs, while providing as much as a $2\times $ reduction in both area and power as compared to SRAM. [ABSTRACT FROM AUTHOR]

Interference between users in adjacent channels negatively affects throughput of mobile networks. In this paper we aim at cancellation of interference caused by a nonlinear power amplifier in a generalized orthogonal frequency division system. We propose an interference cancellation method to subtract these out-of-band emissions from the received signal. In contrast to state-of-the-art methods, our proposed method employs over-the-air estimation of power amplifier model parameters together with a particular frequency domain filtering method that allows to generate the required training data. The proposed interference cancellation method is also verified by an experiment on a software defined radio test bench. [ABSTRACT FROM AUTHOR]

In this paper, a novel architecture of an SRAM-based Physical Unclonable Function (PUF) whose unstable cells are identified and masked by a “capacitive tilt” preselection test is proposed. During the preselection test, either one of the cross-coupled inverter nodes is loaded with a digitally controlled capacitance, which can tilt the PUF towards a “1” or a “0”. Any cell which maintains its value during this test is deemed stable. Each capacitor bank is shared between four PUF cells, such that the additional area required is only 20%. This test does not require precision analog voltages, as did previous tests, and can thus be implemented by the user during key enrollment. In a test-chip implementation in TSMC 65nm node, the preselection test identified and disqualified all the cells that were measured as unstable in 18 PUF arrays, of 800 bits each. An overall scheme for PUF stabilization is proposed, composed of two error-reductions steps, comprising Inner and Outer error control blocks. The outer error control is typically a BCH code, which guarantees a required key error rate. The inner error control can either be the proposed tilt test, a BCH code, or another error correction scheme. To maximize the ratio of reliable key bits to physical PUF cells, i.e., the overall PUF code rate, several solutions were analyzed. It is shown that in order to achieve a key error rate of 1E-9, the most efficient construction is a tilt test followed by BCH[184,128,15], with a PUF code rate of 0.49. In addition, the tilt test is more efficient in terms of power, area and execution time than the other inner error correction mechanisms. Therefore, this construction is not only efficient by its overall code rate, but also by its area and its power, and further, it enables a more lightweight BCH implementation for the outer code. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

One of the main causes of expensive IC redesigns is a failure to meet electromagnetic compatibility (EMC) requirements. For this reason, there is a huge demand for verification methods to identify and prevent immunity failures on chip. Strongly nonlinear effects, in particular DC operating point shifts, are a major cause of such immunity failures. Conventional analysis techniques, used to simulate these strongly nonlinear effects, suffer from a few drawbacks. They can be time-consuming and suffer from convergence issues. Moreover, they do not provide insight into the root causes of the nonlinear behavior. In this paper, an automated method is proposed that overcomes the mentioned drawbacks and identifies causes of immunity failures by listing critical distortion contributions. The method is applicable to very large, strongly nonlinear integrated circuits. It uses a simple model that determines the nonlinear contribution of one device in its linearized environment. Because the computation time is negligible, the analysis can be repeated for many devices and interference frequencies. Additionally, the method gives insight into the drivers responsible for the distortion effects, such that the designer can efficiently solve the problem. The method is demonstrated by applying it to a practical test case. [ABSTRACT FROM AUTHOR]

The paper presents pixel receivers for massively parallel transmission of video signal between capacitive coupled integrated circuits (ICs). The receivers meet the key requirements for massively parallel transmission, namely low-power consumption below a single $\mu \text{W}$ , small area of less than 205 $\mu \text{m}^{\mathbf {2}}$ , high sensitivity better than 160 mV, and good immunity to crosstalk. The receivers were implemented and measured in a 3-D IC (two face-to-face stacked chips fabricated in CMOS 180 nm process). The maximum throughput of 20 Mbps of single receiver has been achieved using a return-to-zero (RZ) code. The static and dynamic power consumption of the single receiver are below $0.2~\mu \text{W}$ and $0.3~\mu \text{W}$ /MHz, respectively. The design approach for cost-effective inter-chip massively parallel transmission of photosensor signals with pulse position modulation (PPM) has been also performed. With this approach and the developed receivers it is possible to transfer between chips 9–10 bit images at a speed of over 1k fps. [ABSTRACT FROM AUTHOR]

This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fsrms at a data rate of 25.78125 Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents an IC that extends the voltage capability of a low voltage battery charger to 100V for accurately and reliably charging lithium ion (Li-Ion) battery stacks of up to 18 cells. The IC interfaces with a buck converter battery charger that utilizes external nFET control and an external inductor current sensing resistor. The voltage extender IC provides voltage level translation for the nFET control signals and the current sensing function while supporting an input power supply voltage of up to 100V and output battery voltage of up to 80V. The inductor current sense voltage is translated with a ping-pong amplifier capable of driving a bi-directional input voltage to a fully differential output with a maximum load current of 10 mA at 20 MHz bandwidth and less than $500~\mu \text{V}$ offset. The combined system of the voltage extender IC and battery charger achieved 97% efficiency at a 4-A charging current. The battery charging voltage accuracy was better than ± 0.5% at 80V. [ABSTRACT FROM AUTHOR]

This paper describes the design of a touch screen panel (TSP) readout IC having an in-band noise immunity. The proposed IC employs a cascaded spread spectrum TSP driving scheme combining chirp spread spectrum (CSS) and pseudo-random (PR) orthogonal sequences. The CSS shows the 12-dB spread gain prior to an application of PR sequences, resulting in total -24-dB in-band noise immunity. The proposed IC adopts trans-impedance amplifier (TIA) with differential current scaler (DCS), providing dynamic range of an analog front-end (AFE) only for a capacitive change from touches. The IC was fabricated in a 0.13- $\mu \text{m}$ standard CMOS. The measurement result shows that the proposed AFE achieves 54.2-dB SNR and 240-Hz scan rate with 11.5-mW power consumption. The readout IC was demonstrated with 5.3-inch $31\times16$ TSP. [ABSTRACT FROM AUTHOR]

This paper presents a post-regulation power management integrated circuit for energy harvesting applications. It incorporates a power budget tracking mechanism to adaptively control the power consumption of a near-threshold-voltage microcontroller based on the time-varying available input power. In addition, the proposed integrated circuit adapts the clock frequency of the microcontroller to the supply voltage under the time-varying input available power to prevent timing violations for the sequential logics of the microcontroller. A prototype shows the adaptive power budget tracking can correct timing violations with only 6.26uA quiescent current. It also properly operates sequential logic circuits at as low as 188mV supply voltage and 1.61MHz clock without interruption when powered by a solar energy harvester under the light illuminance range of 1000–6000lx. This adaptive power tracking structure enables the near-threshold-voltage microcontroller to maintain a continuous operation at optimized processing speed under the varying power condition without violating the timing requirements. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable front-end (FE) circuit for acquiring various low-frequency biomedical signals. An energy and area-efficient tunable filter is proposed for adapting the FE bandwidth to the signal of interest. The filter is designed using a switched-R-MOSFET-C (SRMC) technique to realize the needed ultra-low cutoff frequency. An 8-bit SAR ADC, following the filter, quantizes the signal, while the SAR control logic is re-used to accurately program the filter bandwidth from 40 Hz to 320 Hz with a 40 Hz step. The prototype chip includes the complete FE system, formed of an instrumentation amplifier (IA), a programmable-gain amplifier (PGA), and the proposed tunable filter followed by the SAR ADC. Implemented in 0.13 $\mu \text{m}$ CMOS technology, the IC occupies a 0.6 mm2 active area while consuming 6.3 $\mu \text{W}$ dc power from a 2-V supply. Measurement results show a FE gain range of 43–55 dB with an integrated input-referred noise (${V_{\text {IRN}}}$) of 3.45 $\mu V_{\text {rms}}$ , a 66 dB dynamic range (DR), and a total-harmonic distortion (THD) of −68 dB at an input amplitude of 6 $\text{m}V_{PP}$. The effective number of bits (ENOB) for the ADC is 7.921 bits at 1-kS/s. In real-time Electrocardiogram (ECG), Electromyography (EMG), and Electroencephalography (EEG) measurements, high-fidelity waveforms are acquired using the proposed FE IC, validating the system’s reconfigurability and high-linearity. [ABSTRACT FROM AUTHOR]

On-chip training of support vector machine (SVM) is limited by its low speed and large resource cost. In this paper, a novel integrated circuit implementation of the modified sequential minimal optimization (MSMO) algorithm for fast on-chip SVM training is carried out to speed up the training process of hardware systems. The dual-mode configurable pipelines with the table-driven-based Gaussian kernels are implemented to accelerate the prediction error updating process of the MSMO algorithm and to adapt to both linear and nonlinear datasets with different feature vector dimensions. Efficient MSMO scheduler is proposed to effectively control the computation and data flows of the system. The presented design is verified on a field-programmable gate array using three datasets with different feature vector dimensions. The experimental results show that the design improves the training speed and adaptability of the hardware system without excessively increasing chip area or power consumption, which facilitates the low-cost fast on-chip SVM training. [ABSTRACT FROM AUTHOR]

Mixed-signal machine learning (ML) classification has recently been demonstrated as an efficient alternative for classification with power expensive digital MOSFET circuits. In this paper, a topology based on independent double-gate (IDG) FinFET devices is proposed for classifying high-dimensional input data into multi-class output space with less power and area as compared with state-of-the-art MOSFET classifiers. To facilitate a high-resolution multiplication as a part of the classifier predictions, ML features and feature weights are, respectively, fed to the back and front gate inputs of the individual IDG-FinFET transistors. A classifier that considers the decisions of the individual predictors is designed at 30 nm FinFET technology node and operates at 333 MHZ with nominal supply voltage of one volt. To evaluate the performance of the classifier, a reduced MNIST dataset is generated. The original resolution is reduced from $28 \times 28$ features to $9 \times 9$ features and the most important features are selected with sequential backward selection algorithm. The system is simulated in SPICE, exhibiting prediction accuracy of 90%, energy consumption of 25 pJ per classification (over four times lower than similar state-of-the-art classifiers), area of 1,365 ${\mu }\text {m}^{2}$ , and a stable response under a wide range of system variations. [ABSTRACT FROM AUTHOR]

We study the security feature of static random access memory (SRAM) against the data imprinting attack and provide a solution to protect the SRAM from this attack. There are four main contributions in this paper. First, the negative-bias temperature-instability (NBTI) degradation of PMOS transistors in the conventional SRAM cell that causes the data imprinting effect is explained. Second, the data imprinting effect that leaks the stored information in the conventional SRAM cell is investigated. Third, a novel low transistor-count transmission-gate-based master–slave SRAM cell is proposed to periodically toggle the stored data for reducing the data imprinting effect. Fourth, an efficient imprinting analysis flow is proposed to evaluate the proposed data-toggling SRAM for quantifying the data imprinting effect. Based on a 65-nm CMOS process, we implement and prototype the proposed 1k-byte data-toggling SRAM design. We perform our imprinting analysis flow on various SRAM ICs and benchmark our proposed data-toggling SRAM IC against the non-toggling SRAM IC and a commercial Lyontek SRAM IC. From the measurement results, the non-toggling SRAM and Lyontek SRAM suffer from 60% and 81% data imprinting effects, respectively, whereas our data-toggling SRAM has only 11% data imprinting effect (at 160-kHz toggling frequency). The data-toggling SRAM could switch between high security (< 5% data imprinting effect) high power mode for hardware security applications and low power (< 0.1mW) low security mode for power-saving applications. Particularly, our data-toggling SRAM could feature as low as ~1% data imprinting effect when increasing the toggling frequency to 1.6 MHz by compromising the power dissipation. Using the image analysis flow, the stored information is revealed in both the non-toggling and Lyontek SRAM ICs but is well protected in the proposed data-toggling SRAM IC. [ABSTRACT FROM AUTHOR]

This paper presents a novel time-variant model of multiplying delay-locked loops. A simple feed-forward model of the multiplexed ring oscillator mathematically describes the edge realignment process and, by providing an explicit tuning input, allows to be embedded into the time-variant multiplying delay-locked loop model without requiring approximations. Verification of the multiplexed ring oscillator model against detailed circuit simulations is presented. Closed-form expressions for the multiplying delay-locked loop phase noise, as a function of the system parameters and noise sources, are provided. [ABSTRACT FROM AUTHOR]

This paper considers a large class of memristor circuits of arbitrary order, and containing an arbitrary number of flux- or charge-controlled memristors, for which a state equation (SE) description can be obtained. By means of the SEs, it is shown that the state space of each circuit can be decomposed in infinitely many manifolds, and that in the autonomous case, each manifold is positively invariant and is characterized by a different reduced-order dynamics and attractors. These results are the basis for extending the analysis to the non-autonomous case, where time-varying independent sources are present. In particular, the chief result obtained in this paper shows how to analytically design external pulses for programming memristor circuits, i.e., how invariant manifolds and attractors can be changed and controlled by applying suitable charge or flux sources via time-varying voltage and/or current pulses with finite time duration. The main results are obtained by relying on a recently introduced technique for the analysis of memristor circuits in the flux-charge domain. [ABSTRACT FROM AUTHOR]

For spaceborne instrumentation, the prohibitive cost of a flight traditionally favors programmable solutions such as field programmable gate arrays (FPGAs). As scientific goals become more ambitious, the FPGA-based solutions are showing limitations, especially with restricted launch vehicle capacity and available solar power. In this paper, modern integrated circuit technology is adopted to realize two fully integrated spectrometer SoCs to support spaceborne telescopic sensing. The system specifications are derived from the scientific principles of radio-frequency spectroscopy while each component strives for a simple and reliable implementation. Realized in 65-nm CMOS technology, Design A operates at 2.6 GHz with a three-bit ADC, a 2048-point FFT with 8192-point polyphase filter bank, and a billion-count accumulator. Design B more than doubles the bandwidth, reaches 6 GS/s by interleaving the ADC. The FFT size is also quadrupled to 8192. Both designs include integrated phase locked loops and tunable clock distribution networks. Design A consumes a peak power of 650 mW and Design B consumes 1.5 W. They represent the highest level of integration among similar endeavors and achieve orders of magnitude of improvement over traditional solutions in terms of size, weight, and power consumption. Both designs are actively involved in NASA’s spectroscopy missions. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method to reduce the water interference on the touch panel based on mutual-capacitance sensing in human finger detection. As the height of a finger (height >10 mm) is far larger than that of a water-drop (height <1 mm), if the density distribution of electrical field of the touch panel’s sensing cell is high in the high-height space (height >10 mm) and low in the low-height space (height <1 mm), the sensing cell can be designed to distinguish the finger from the water-drop. To achieve this density distribution of the electrical field, the mutual-coupling electrical field shaping (MEFS) technique is employed to build the sensing cell. The drawback of the MEFS sensing cell is large parasitic capacitance, which can be overcome by a readout IC with low sensitivity to parasitic capacitance. Experiments show that the output of the IC with the MEFS sensing cell is 1.11 V when the sensing cell is touched by the water-drop and 1.23 V when the sensing cell is touched by the finger, respectively. In contrast, the output of the IC with the traditional sensing cell is 1.32 and 1.33 V when the sensing cell is touched by the water-drop and the finger, respectively. This demonstrates that the MEFS sensing cell can better distinguish the finger from the water-drop than the traditional sensing cell does. [ABSTRACT FROM AUTHOR]

The emerging area of network science and engineering is concerned with the study of structural characteristics of networks, their impact on the dynamical behavior of systems as revealed through their topological properties, random evolution of networks, information spreading along a network, and so on. This area spans a wide range of applications in different disciplines. A topic of great interest in this area is the notion of network criticality. Most measures of network criticality are defined by the paths that flow through the nodes or edges. Since computing all the paths is computationally intractable, only the shortest paths are usually used for computing criticality metrics. Thus, measures that implicitly capture the impact of all the paths will be useful. The recently introduced concepts of the resistance distance and the Kirchhoff Index are two such measures. In this paper, we study these metrics and present several results that extend, generalize, and unify earlier works reported in the literature. In developing these results, the role of circuit theoretic concepts is emphasized. We also relate our works to Foster’s theorems and present a generalization that captures and retains the circuit theoretic elegance of Foster’s original theorems. [ABSTRACT FROM AUTHOR]

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be $471.6~\mu \text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10−12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC. [ABSTRACT FROM AUTHOR]

Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and sub-ns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/($\mu $ mV), which is an $1.7\times $ improvement on the next best reported level shifter for this type of application. [ABSTRACT FROM AUTHOR]

The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and $\text{I}_{\mathbf {on}}/\text{I}_{\mathbf {off}}$ ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, data-dependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce data-dependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices. [ABSTRACT FROM AUTHOR]

Although the multiband-structured subband adaptive filter (MSAF) and its convergence analysis have been widely studied, the existing analyses are carried out only in the decimated time domain. In this paper, we present a new theoretical mean-square analysis of the multi-sampled MSAF (MS-MSAF) algorithm in the original time domain, whereas the MS-MSAF algorithm extends the original sub-sampled number to a general value. Both the transient and steady-state performances are investigated, which provides a guideline for increasing the convergence rate of the MSAF. Then, the tracking ability is studied in a non-stationary environment. Moreover, the approximative analytical minimum mean-square deviation and optimum step size are derived. Simulation results illustrate the derived performance expressions, which show that there is a relatively good match between theory and practice. [ABSTRACT FROM AUTHOR]

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications. [ABSTRACT FROM AUTHOR]

This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offset frequency, and the measurements indicate a significant improvement in the overall front-end interference robustness, while sensitivity remains unaffected. To optimize notch performance, the BB impedance is analyzed in detail. The front-end RF range is 750 MHz–3 GHz with an RF channel bandwidth of 20 MHz corresponding to 10-MHz BB bandwidth. The notch frequency is programmable from 16, which is less than one octave from the channel edge, up to 160 MHz. The gain-compression improvement is upto 9 dB, while IIP2 can be increased by more than 26 dB without calibration and IIP3 is 1 dBm. The current overhead for the notch function is between 7.5 and 30 mA, but it only exists under strong blocker conditions as the notch filter can be switched OFF if strong blockers are absent. The total front-end current consumption excluding the notch filter varies with LO frequency from 31 to 44 mA from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels–coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub- $V_{\mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort. [ABSTRACT FROM AUTHOR]

In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18- $\mu \text{m}$ , 1-poly, and 4-metal CIS technology with a pixel array of $128 \times 160$ is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor $C_{\textit {FD}}$ on the floating diffusion node, which is remnant in VM. [ABSTRACT FROM AUTHOR]