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This paper presents a novel minimum entropy filter design for a class of stochastic nonlinear systems, which are subjected to non-Gaussian noises. Motivated by stochastic distribution control, an output entropy model is developed using a radial basis function neural network, while the parameters of the model can be identified by the collected data. Based upon the presented model, the filtering problem has been investigated, while the system dynamics have been represented. As the model output is the entropy of the estimation error, the optimal nonlinear filter is obtained based on the Lyapunov design, which makes the model output minimum. Moreover, the entropy assignment problem has been discussed as an extension of the presented approach. To verify the presented design procedure, a numerical example is given, which illustrates the effectiveness of the presented algorithm. The contributions of this paper can be summarized as follows: 1) an output entropy model is presented using a neural network; 2) a nonlinear filter design algorithm is developed as the main result; and 3) a solution of the entropy assignment problem is obtained, which is an extension of the presented framework. [ABSTRACT FROM AUTHOR]

The rapid expansion of analog and neuromorphic memristive applications has proven that their reconfigurable and reprogrammable characteristics will be major proponents for pushing beyond Moore’s Law. The lack of easily accessible and reliable solid-state memory elements (mem-elements) results in an ever-increasing body of the research lacking physical verification, and an associated high barrier to entry for researchers. This paper serves to fix this deficiency by introducing a novel universal interface circuit, which when connected to different peripheral circuits, can be used to build fundamental mem-elements. There is an abundance of mem-element emulators, we adopt their advantages into our design to foster practical and broadly applicable mem-element circuits. In comparison to other similar state-of-the-art emulators, our circuit utilized up to 42.9% fewer active components which consumed up to 31.9% less power with an associated reduction of size by 41.7%. Our proposed emulator continues to operate with hysteresis at over 180 kHz, which is two orders of magnitude higher than other similar emulators and commercially available solid-state memristors, whilst maintaining floating terminal connections. Rigorous theoretical, simulation and experimental results are conducted with good agreement with applications given, demonstrating the ability of the universal interface to discretely build mem-elements. [ABSTRACT FROM AUTHOR]

This paper presents an inductor-less switched capacitor based energy harvester, which can simultaneously harvest from 2 energy sources (Solar + Piezo). The proposed harvester employs maximum power point tracking algorithm, by changing the conversion ratios of the charge pumps for piezo and solar sources, and output voltage control by varying the switching frequency. The proposed MPPT algorithm can match the input impedance of two sources simultaneously. Implemented in 65nm CMOS, the proposed harvester can generate a fixed output between 1.8 and 2.5 V output while delivering 35 $\mu \text{W}$ to 70 $\mu \text{W}$ power with a peak power conversion efficiency of 74.6%. [ABSTRACT FROM AUTHOR]

In this paper we explore the effects of pole-zero compensation in the settling performance of operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a proficient technique that provides an in-depth comprehension of the time domain behavior from the contour plots of the Normalized Settling Time. Starting from the case of a single-pole amplifier, we show the conditions upon which the settling time is degraded by the slow time constant set by the pole-zero doublet. Then, we extend these results to two-pole amplifiers and provide a useful design equation. Design examples of a two-stage and a single-Miller three-stage OTAs confirm the validity of the proposed theoretical models. [ABSTRACT FROM AUTHOR]

This paper proposes a novel robust fault detection (FD) approach and designs a set-theoretic unknown input observer (SUIO) for linear parameter-varying (LPV) systems with both state and output equations scheduled by inexact scheduling variables. First, for such LPV systems, we propose a novel robust FD method by combing the set theory with the unknown input observer, which considers the bounds of measurement errors of scheduling variables to generate FD-oriented sets. In general, as long as sensors with sufficiently high precision are equipped to measure the scheduling variables, the bounds of measurement errors of scheduling variables can be less conservative than those direct bounds of scheduling variables, which can reduce robust FD conservatism in this way. Second, we give the unknown input decoupling condition of SUIO for such LPV systems and propose an SUIO design method under this condition for robust state estimation (SE). Besides, stability conditions for the proposed methods are established via matrix inequalities. At the end of this paper, a case study is used to illustrate the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

Memristors are intensively proposed in many applications, such as biosensors and machine learning. Regarding their analog characteristics, memristance decoder is, therefore, an essential part for every memristor-based system. As memristor is a temperature sensitive device, this paper proposes a memristance decoder circuit with the self-temperature calibration. Its main building block is a comparator that is based on current mode circuit to achieve high performance at low power. The design provides configurable precision based on the available energy and supports both synchronous and asynchronous schemes. Moreover, the VTEAM model is modified to include the temperature effect on the memristance in the analysis. The simulation results, based on UMC 65-nm low-leakage CMOS technology, show the following comparator’s characteristics: 1.70% maximum offset, 2.91-ns worst case latency, 343-MHz maximum frequency, and 48.79-fJ maximum energy per comparison. The Monte Carlo simulation shows the metastable state in determining the memristor value. This can be solved by extending the clock period or applying a metastability resolver. The proposed memristor model reveals that the memristance at high resistive state degrades quadratically with the rise of the temperature and at 85°C nearly reaches the memristance of low resistive state. The possibility of decoding error due to the temperature effect is demonstrated via simulations. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a method to obtain necessary and sufficient stability conditions for systems governed by one-dimensional nonlinear hyperbolic partial-differential equations with closed-loop integral controllers, when the linear frequency analysis cannot be used anymore. We study the stability of a general nonlinear transport equation where the control input and the measured output are both located on the boundaries. The principle of the method is to extract the limiting part of the stability from the solution using a projector on a finite-dimensional space and then use a Lyapunov approach. This paper improves a result of Trinh, Andrieu, and Xu, and gives an optimal condition for the design of the controller. The results are illustrated with numerical simulations where the predicted stable and unstable regions can be clearly identified. [ABSTRACT FROM AUTHOR]

This paper presents a novel time-variant model of multiplying delay-locked loops. A simple feed-forward model of the multiplexed ring oscillator mathematically describes the edge realignment process and, by providing an explicit tuning input, allows to be embedded into the time-variant multiplying delay-locked loop model without requiring approximations. Verification of the multiplexed ring oscillator model against detailed circuit simulations is presented. Closed-form expressions for the multiplying delay-locked loop phase noise, as a function of the system parameters and noise sources, are provided. [ABSTRACT FROM AUTHOR]

In this paper, we propose and analyze a pulse-output digital-to-frequency converter (DFC) generating square waves, which uses a digital-to-time converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system, and explore possibilities and limits of this approach in terms of cleanness of the output spectrum. The behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worst-case spur, which leads to a simple design equation. This is useful to determine the DTC requirements [number of bits and integral non-linearity (INL)], given a certain spurious-free dynamic range (SFDR) target. We show that the maximum spur strength (in dBc) depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL, and other impairments) and increases with the ratio by 6 dB/octave. [ABSTRACT FROM AUTHOR]

This paper investigates the existence of nonimpulsive unique solution and stochastic stability problems for the discrete-time linear rectangular descriptor Markov jump systems at two cases. For every case, the sufficient and necessary conditions, in terms of strict linear matrix inequalities, are eventually proposed to guarantee that the discrete-time linear rectangular descriptor Markov jump systems are column (row) regular, column (row) causal, stochastically stable, and have a unique solution. In addition, some assumptions are introduced to ensure that there is no impulse in the solution at the instant when the Markov process jumps. Moreover, the concrete procedures on how to apply the results obtained in this paper are presented as well. Finally, an example is provided to demonstrate the effectiveness of the results. [ABSTRACT FROM AUTHOR]

Most conventional CMOS technologies possess the so-called zero-temperature coefficient (ZTC) operating point where the transistor’s drain current becomes nearly independent of temperature due to the mutual temperature cancellation of threshold voltage and carrier mobility. This paper discusses how this ZTC point can be exploited in the design of current and voltage references with low supply voltages. Besides a theoretical overview regarding the ZTC behavior, a current reference in a standard 0.25- $\mu \text{m}$ CMOS technology operable from 1.3 V is presented. To further explore the possibilities of this approach, a voltage reference with a nominal supply voltage of just 0.5 V is designed and fabricated in a 130-nm technology. Measurement results are given for both circuits. [ABSTRACT FROM AUTHOR]

Pinched hysteresis behavior is considered evidence of the existence of the memristive element. Recently, the multi-lobes (more than two) behavior has been discovered in some memristive devices. In this paper, a fractional-order flux/voltage-controlled memristive model is introduced that is able to develop multiple symmetric and asymmetric pinch-off points. Generalized closed-form expressions for the necessary conditions of multiple pinch-off points existence are derived in addition to the coordinates of the pinch-off points in the $I\!-\!V$ plane. Closed-form expressions for the minimum and maximum achievable resistances are derived. Moreover, different illustrative numerical examples have been given verifying the calculated expressions. Finally, in order to verify the multiple pinch-off behaviors, the proposed emulator circuit is introduced, analyzed, and verified using both SPICE simulations and experiments to validate the proposed models. Different fractional-order cases have been experimentally tested using different excitation signals such as sinusoidal, square, and triangular signals showing the circuit-ability to generate the multiple pinch-off points. [ABSTRACT FROM AUTHOR]

In this paper, the robustness to model mismatch of a preexisting collocated boundary adaptive feedback law is investigated. This control law was originally designed for an antidamped pure wave partial differential equation (PDE). Actuation and measurements are located at the same boundary. Adaptive terms account for uncertain parameters located at the antidamped boundary, opposite to the collocated actuation and measurement. By extending and transforming the system state using, in particular, backstepping, this paper establishes that this controller is robust to sufficiently small in-domain damping. In particular, both stability and attractivity (convergence) are established similarly as in the nominal case. Note moreover that, assuming that some parameters are known, the exponential stability to an attractor holds. Simulations are performed to illustrate the interest of this study to attenuate mechanical vibrations in an oil-drilling context. [ABSTRACT FROM AUTHOR]

This paper is concerned with the power system state estimation (PSSE) problem that aims to find the unknown operating point of a power network based on a given set of measurements. We first study the power flow (PF) problem as an important special case of PSSE. PF is known to be nonconvex and NP-hard in the worst case. To this end, we propose a set of semidefinite programs (SDPs) with the property that they all solve the PF problem as long as the voltage angles are relatively small. Associated with each SDP, we explicitly characterize the set of all the complex voltages that can be recovered via that convex problem. As a generalization, the design of an SDP problem that recovers multiple nominal points and a neighborhood around each point is also cast as a convex program. The results are, then, extended to the PSSE problem, where the measurements used in the PF problem are subject to noise. A two-term objective function is employed for each convex program developed for the PSSE problem: 1) the first term accounting for the nonconvexity of the PF equations and 2) other one for estimating the noise levels. An upper bound on the estimation error is derived with respect to the noise level, and the proposed techniques are demonstrated on multiple test systems, including a 9241-bus European network. Although the focus of this paper is on power networks, yet the developed results apply to every arbitrary state estimation problem with quadratic measurement equations. [ABSTRACT FROM AUTHOR]

This paper aims to investigate the fuzzy constrained matrix game (MG) problems using the concepts of recurrent neural networks (RNNs). To the best of our knowledge, this paper is the first in attempting to find a solution for fuzzy game problems using RNN models. For this purpose, a fuzzy game problem is reformulated into a weighting problem. Then, the Karush–Kuhn–Tucker (KKT) optimality conditions are provided for the weighting problem. The KKT conditions are used to propose the RNN model. Moreover, the Lyapunov stability and the global convergence of the RNN model are also confirmed. Finally, three illustrative examples are presented to demonstrate the effectiveness of this approach. The obtained results are compared with the results obtained by the previous approaches for solving fuzzy constrained MG. [ABSTRACT FROM AUTHOR]

In this paper, the application of the theory of Lissajous figures to the creation of pinched hysteresis loops, considered to be a characteristic of memristive systems, is demonstrated and experimentally verified using designed electronic circuits in the form of an input impedance. The relationship between the Lissajous-based model of the pinched hysteresis loop and a previously reported integrator-multiplier model is clarified. Important special cases are highlighted and necessary conditions to obtain a pinch point, loops with positive or negative inclination, as well as no pinch point are given. We show that in devices (memristors or other devices) and circuits which exhibit this behavior, a nonlinearity that performs the necessary frequency doubling mandated by the theory must exist. [ABSTRACT FROM AUTHOR]

In this paper, we present completely analytic design equations for a narrowband filtering power divider with an excellent isolation performance over a wide frequency range. For providing the complete design equations, the even–odd mode analysis on the circuits has been carried out. The design theory and equations allow a filtering power divider containing frequency-independent inverters to have infinite isolation over the entire frequency range. The presented design theory is significant in a sense that it enables designing a filtering power divider with a high isolation over a wide frequency range when the divider contains frequency-variant inverters in practice. Using the closed-form equations, all circuit element values and detailed physical dimensions of filtering power divider can be found based on a pre-specified filtering response. Therefore, our design method can provide a filtering power divider design guideline for the various specifications required by communications systems. For verifying the presented design method and analytic design equations, a third-order lumped-element narrowband filtering power divider has been designed, fabricated, and measured. We have also implemented a filtering power divider using microstrip resonators to verify that the presented design method and equations can be applied to distributed-element filtering power divider designs. The measured results have shown a good agreement with theoretical results. [ABSTRACT FROM AUTHOR]

Low-cost accurate digital realization of the spiking neural networks is crucial to investigate the behaviors of human brain performance. This paper presents a multiplierless burst-mode Fitz–Hugh Nagumo (MBM-FHN) model, which is used for generating the burst-mode of the FHN neuron model. Using extra parameters (time-varying function) in neuron equations and estimating it by linear function, efficient low-cost and high-speed implementation is achieved. The simulation results show that the MBM-FHN model generates the similar bursting patterns of the original FHN neuron. The comparison shows that the MBM-FHN model has a better performance and best cost reduction related to the original neuron model especially in overall saving and speed-up parameters. [ABSTRACT FROM AUTHOR]

The main focus of this paper is the evolution of complex behavior in a system of coupled nonlinear memristor circuits depending on the applied coupling conditions. Thereby, the parameter space for the local activity and the edge-of-chaos domain will be determined to enable the emergence of the pattern formation in locally coupled cells according to Chua’s principle. Each cell includes a Niobium oxide-based memristor, which may feature a locally active behavior once it is suitably biased on the negative differential resistance region of its DC current-voltage characteristic. It will be shown that there exists a domain of parameters under which each uncoupled cell may become locally active around a stable bias state. More specifically, under these conditions, the coupled cells are on the edge-of-chaos, and can support the static and dynamic pattern formation. The emergence of such complex spatio-temporal behavior in homogeneous structures is a prerequisite for information processing. The theoretical results are confirmed by measurements as well as by the numerical simulations of the accurate device and circuit models. [ABSTRACT FROM AUTHOR]

The low-voltage low-power sinh-domain (SD) implementations of integer- and fractional-order FitzHugh–Nagumo (FHN) neuron model have been introduced in this paper. Besides, the effect of fractional-orders on the external excitation current and dynamics of the neuron has been examined in this paper. The proposed SD designs of FHN neuron model have the benefits of: 1) low-voltage operation; 2) integrability, due to resistor-less design and the employment of only grounded components; 3) electronic tunability of performance parameters; and 4) low-power implementation due to the inherent properties of SD technique. HSPICE simulator tool and Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan 130-nm CMOS process was used to evaluate and verify the correct functioning of the model. In addition, to experimentally verify the operation of the proposed fractional-order FHN neuron model, field-programmable analog array (FPAA) implementation of the model has been presented, and the proper functioning of the model has been verified. To the best of the authors’ knowledge, this is the first paper that describes the electronic realization of the fractional-order FHN neuron model. In addition, it is the first time that the FPAA implementation of any fractional-order neuron model has been presented. [ABSTRACT FROM AUTHOR]

The topic of this paper is the development of biological models for 3D reaction–diffusion phenomena that can be used in any circuit electronic design automation environment for the simulation of biosensors. Biological systems that involve such 3D phenomena are described by partial differential equations. Our approach consists in discretizing these equations according to the finite-difference method and converting the resulting ordinary differential equations into an assembly of elementary electronic equivalent circuits that are directly simulated with SPICE. The main interest of this approach is the ability to couple such models with third-party SPICE models of electronic circuits, sensors, and transducers, i.e., models from any physical domain ruled by Kirchhoff laws, allowing modeling and simulation of any multi-physics systems in a conventional circuit design environment, here CADENCE. The tool is validated on simple problems for which analytical solutions are known. Then, the interest of the approach is illustrated on the study of a biosensor. [ABSTRACT FROM AUTHOR]

This paper presents an improved method for reducing high-order dynamical system models via clustering. Agglomerative hierarchical clustering based on performance evaluation (HC-PE) is introduced for model order reduction. This method computes the reduced order denominator of the transfer function model by clustering system poles in a hierarchical dendrogram. The base layer represents an $n{\textrm {th}}$ order system, which is used to calculate each successive layer to reduce the model order until finally reaching a second-order system. HC-PE uses a mean-squared error (MSE) in every reduced order, which modifies the pole placement process. The coefficients for the numerator of the reduced model are calculated by using the Padé approximation (PA) or alternatively a genetic algorithm (GA). Several numerical examples of reducing techniques are taken from the literature to compare with HC-PE. Two classes of results are shown in this paper. The first sets are single-input single-output models that range from simple models to 48th order systems. The second sets of experiments are with a multi-input multioutput model. We demonstrate the best performance for HC-PE through minimum MSEs compared with other methods. Furthermore, the robustness of HC-PE combined with PA or GA is confirmed by evaluating the third-order reduced model for the triple-link inverted pendulum model by adding a disturbance impulse signal and by changing model parameters. The relevant stability proofs are provided in Appendixes A and B in the supplementary material. HC-PE with PA slightly outperforms its performance with GA, but both approaches are attractive alternatives to other published methods. [ABSTRACT FROM AUTHOR]

Filters in cochlear models use different coefficients to break sound into a 2-D time-frequency representation. On digital hardware with a single sampling rate, the number of bits required to represent these coefficients requires substantial computational resources such as memory storage. In this paper, we present a cochlear model operating at multiple sampling rates. As a result, fewer bits are required to represent filter coefficients on hardware as opposed to all the filters operating at a single sampling rate; with a 108-filter cochlear implementation, up to nine times fewer coefficients are needed. We present an implementation of this model in Matlab and on an Altera Cyclone V field-programmable gate array. We also demonstrate the capability of our model to encode sound at various intensity levels and with real-world signals. [ABSTRACT FROM AUTHOR]

This paper presents a systematic method to analyze the stability of systems with single delay in which the coefficient polynomials of the characteristic equation depend on the delay. Such systems often arise in, for example, life science and engineering systems. A method to analyze such systems was presented by Beretta and Kuang in a 2002 paper, but with some very restrictive assumptions. This paper extends their results to the general case with the exception of some degenerate cases. It is found that a much richer behavior is possible when the restrictive assumptions are removed. The interval of interest for the delay is partitioned into subintervals so that the magnitude condition generates a fixed number of frequencies as functions of the delay within each subinterval. The crossing conditions are expressed in a general form, and a simplified derivation for the first-order derivative criterion is obtained. Illustrative examples are also presented in this paper. [ABSTRACT FROM AUTHOR]

We study in this paper, a class of constrained linear-quadratic (LQ) optimal control problem formulations for the scalar-state stochastic system with multiplicative noise, which has various applications, especially in the financial risk management. The linear constraint on both the control and state variables considered in our model destroys the elegant structure of the conventional LQ formulation and has blocked the derivation of an explicit control policy so far in the literature. We successfully derive in this paper, the analytical control policy for such a class of problems by utilizing the state separation property induced from its structure. We reveal that the optimal control policy is a piecewise affine function of the state and can be computed offline efficiently by solving two coupled Riccati equations. Under some mild conditions, we also obtain the stationary control policy for an infinite time horizon. We demonstrate the implementation of our method via some illustrative examples and show how to calibrate our model to solve dynamic constrained portfolio optimization problems. [ABSTRACT FROM AUTHOR]

It is well known that active learning can simultaneously improve the quality of the classification model and decrease the complexity of training instances. However, several previous studies have indicated that the performance of active learning is easily disrupted by an imbalanced data distribution. Some existing imbalanced active learning approaches also suffer from either low performance or high time consumption. To address these problems, this paper describes an efficient solution based on the extreme learning machine (ELM) classification model, called active online-weighted ELM (AOW-ELM). The main contributions of this paper include: 1) the reasons why active learning can be disrupted by an imbalanced instance distribution and its influencing factors are discussed in detail; 2) the hierarchical clustering technique is adopted to select initially labeled instances in order to avoid the missed cluster effect and cold start phenomenon as much as possible; 3) the weighted ELM (WELM) is selected as the base classifier to guarantee the impartiality of instance selection in the procedure of active learning, and an efficient online updated mode of WELM is deduced in theory; and 4) an early stopping criterion that is similar to but more flexible than the margin exhaustion criterion is presented. The experimental results on 32 binary-class data sets with different imbalance ratios demonstrate that the proposed AOW-ELM algorithm is more effective and efficient than several state-of-the-art active learning algorithms that are specifically designed for the class imbalance scenario. [ABSTRACT FROM AUTHOR]

This paper studies an $H_{\infty }$ model reduction problem for interval frequency negative imaginary (IFNI) systems. For a given IFNI system, our goal is to find a reduced-order IFNI system satisfying a pre-specified $H_{\infty }$ approximation error bound over the finite-frequency interval. Necessary and sufficient conditions in terms of matrix inequalities are derived for the existence and construction of an $H_{\infty }$ reduced-order IFNI system. An improved iterative algorithm is provided to solve the matrix inequalities and to minimize the $H_{\infty }$ approximation error. The proposed method is further clarified via the application to the electrical circuits, such as high-order Sallen–Key low-pass filter, piezoelectric tube scanner, and RLC circuit. The simulation results on these electrical circuits are compared with the finite-frequency interval Gramians-based model reduction method both in the frequency domain and time domain. [ABSTRACT FROM AUTHOR]

In this paper, a full-order observer design method is proposed for port-Hamiltonian systems. The proposed method is based on the notion of contractive port-Hamiltonian systems. It is the first structure preserving observer design for a broad class of input-state-output port-Hamiltonian systems. The design procedure consists of solving a matching equation, similar to the Interconnection and Damping Assignment Passivity-Based Control (IDA-PBC) for controller design. The matching equation, as shown in the paper, has some closed-form solutions for general class of mechanical and electromechanical systems. As another feature of the proposed method, it is shown that the existence of solution of the corresponding matching equation for a linear port-Hamiltonian system is equivalent to the detectability property of that system. Upon these facts, the proposed method can be considered as a counterpart of IDA-PBC for observer design. Simulations for some benchmark examples, including ball and beam, magnetic levitation, and permanent magnetic synchronous motor, show the potency and applicability of the method. [ABSTRACT FROM AUTHOR]

In this paper, we consider the identification of matrix state-space models (MSSM) of the following form: \begin{align*} \mathbf {X}(k+1) &= \mathbf {A}_2 \mathbf {X}(k) \mathbf {A}_1^T + \mathbf {B}_2 \mathbf {U}(k) \mathbf {B}_1^T \\ \mathbf {Y}(k) &= \mathbf {C}_2 \mathbf {X}(k) \mathbf {C}_1^T + \mathbf {E}(k) \end{align*} for all time dependent quantities and matrices of appropriate dimensions. Due to the large size of these matrices, vectorization does not allow the use of standard multivariable subspace methods such as N4SID or MOESP. In this paper, the resulting Kronecker structure that appears in the system matrices due to vectorization is exploited for developing a scalable subspace-like identification approach. This approach consists of first estimating the Markov parameters associated to the MSSM via the solution of a regularized bilinear least-squares problem that is solved in a globally convergent manner. Second, a bilinear low-rank minimization problem is tackled which allows to write a three-dimensional low-rank tensor and consequently to estimate the state sequence and the lower-dimensional matrices $\mathbf {A}_1,\mathbf {A}_2,\mathbf {B}_1,\mathbf {B}_2,\mathbf {C}_1,\mathbf {C}_2$. A numerical example on a large-scale adaptive optics system demonstrates the ability of the algorithm to handle the identification of state-space models within the class of Kronecker structured matrices in a scalable manner which results in more compact models. [ABSTRACT FROM AUTHOR]

In this paper, the analysis of a current feedback compensation architecture compatible with pixels having the 2-transistors and 1-capacitor structure is evaluated. The aim of the circuit presented and analyzed, is to cleanly reach a programming pixel current level below 50 nA with an average 10% of error. Here, we also present the method to achieve robustness in the operation of the loop, observed through a series of measurements. All the peripheral blocks implementing the design are presented and analyzed through simulations as well as verified experimentally. Sources of noise are identified and eliminated, while the new techniques for better isolation from digital noise are described and tested on a newly fabricated driver. Multiple versions of the previously proposed circuit are outlined, simulated, fabricated, and measured to evaluate their performance. [ABSTRACT FROM AUTHOR]

In this paper, we present a framework for analytically estimating the output quality of common digital signal processing (DSP) blocks that utilize approximate adders. The framework is based on considering the error of approximate adders as an additive noise (approximation noise) that disturbs the output of the DSP block in question. A signal processing theoretical modeling approach for describing the power of the approximation noise which is the integral of error spectral density over the bandwidth, is developed. The output qualities of DSP blocks, such as finite impulse response filter, discrete cosine transform, and fast Fourier transform, which utilize approximate adders, are thus estimated. The accuracy of the proposed framework is evaluated by comparing mathematical model predictions to simulation results by using the signal-to-noise ratio (SNR) metric. The inaccuracy of the SNRs predicted by the framework was, on average, less than 2.5dB compared with that obtained from simulations. Therefore, a mathematical optimization approach based on Lagrange Multipliers for optimizing design parameters is also presented. The optimization is realized by choosing a proper configuration of the target block, such as determining the data width of the inexact computation part for each approximate adder in the design. [ABSTRACT FROM AUTHOR]

Sensitivity analysis is an important tool for describing power system dynamic behavior in response to parameter variations. It is a central component in preventive and corrective control applications. The existing approaches for sensitivity calculations, namely, finite-difference and forward sensitivity analysis, require a computational effort that increases linearly with the number of sensitivity parameters. In this paper, we investigate, implement, and test a discrete adjoint sensitivity approach whose computational effort is effectively independent of the number of sensitivity parameters. The proposed approach is highly efficient for calculating sensitivities of larger systems and is consistent, within machine precision, with the function whose sensitivity we are seeking. This is an essential feature for use in optimization applications. Moreover, our approach includes a consistent treatment of systems with switching, such as dc exciters, by deriving and implementing the adjoint jump conditions that arise from state-dependent and time-dependent switchings. The accuracy and the computational efficiency of the proposed approach are demonstrated in comparison with the forward sensitivity analysis approach. This paper focuses primarily on the power system dynamics, but the approach is general and can be applied to hybrid dynamical systems in a broader range of fields. [ABSTRACT FROM AUTHOR]

Dynamic element matching (DEM) is often applied to multi-bit DACs to avoid nonlinear distortion that would otherwise result from inevitable mismatches among nominally identical circuit elements. Unfortunately, for such a DEM DAC to fully achieve this objective its constituent 1-bit DACs must be free of inter-symbol interference (ISI), i.e., the error from each 1-bit DAC must not depend on prior samples of the DAC's input sequence. This paper provides the first quantitative general analysis of the effects of ISI on the continuous-time outputs of DEM DACs. The analysis provides some surprising insights such as the conclusion that for certain types of DEM the only nonlinear distortion caused by ISI is second-order distortion. The paper also presents a digital pre-distortion technique that cancels the second-order distortion in the DEM DAC's first Nyquist band if information about the 1-bit DAC mismatches is available. [ABSTRACT FROM PUBLISHER]

Incremental analog-to-digital-converters (IADCs) are variants of $\triangle \Sigma $ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18- $\mu \text{m}$ process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well. [ABSTRACT FROM AUTHOR]

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation. The proposed architecture performs the task of Nth root simply by shift-add operations and enables easy tradeoff between the speed (or precision) and the area. Technically, we divide the Nth root computation into three different subtasks, and map them onto three different classes of the CORDIC accordingly. To overcome the drawback of narrow convergence range of the CORDIC algorithm, we adopt several innovative methods to yield a much improved convergence range. Subsequently, in terms of convergence range and precision, a flexible architecture is developed. The architecture is validated using MATLAB with extensive vector matching. Finally, using a pipelined structure with fixed-point input data, we implement the example circuits of the proposed architecture with radicand ranging from zero to one million, and achieve an average mean of approximately 10−7 for the relative error. The design is modeled using Verilog HDL and synthesized under the TSMC 40-nm CMOS technology. The report shows a maximum frequency of 2.083 GHz with $197421.00~{\mu }\text{m}^{2}$ area. The area decreases to $169689.98~{\mu }\text{m}^{2}$ when the frequency lowers to 1.00 GHz. [ABSTRACT FROM AUTHOR]

In this paper, a procedure for the analysis and design of nonlinear circuits based on the Carleman linearization is presented. Since this procedure starts with the general network equations which are derived by Kirchhoff’s law, it can be used for a variety of circuits. The proposed procedure is applied for oscillator and RF mixer circuits which are a crucial part of every wireless communication system. Based on the general network equations, a transformation into equivalent polynomial differential equations is performed using the not widely known method of Kerner. This polynomial differential equation is further transformed into an equivalent infinite-dimensional system of linear differential equations. Since the infinite-dimensional linear system cannot be solved in general, an approximation by a finite one is performed using a self-consistent technique. The obtained finite linear system is used for the approximation of the infinite-dimensional linear system on a predefined interval. The approximation is utilized for the design and analysis process of the circuit, which is a challenging problem until now. [ABSTRACT FROM AUTHOR]

In this paper, the receding horizon near-optimal tracking control problem about a class of continuous-time nonlinear systems with fully unknown dynamics is considered. The main challenges of this problem lie in two aspects: 1) most existing systems only restrict their considerations to the state feedback part while the input channel parameters are assumed to be known. This paper considers fully unknown system dynamics in both the state feedback channel and the input channel and 2) the optimal control of nonlinear systems requires the solution of nonlinear Hamilton–Jacobi–Bellman equations. Up to date, there are no systematic approaches in the existing literature to solve it accurately. A novel model-free adaptive near-optimal control method is proposed to solve this problem via utilizing the Taylor expansion-based problem relaxation, the universal approximation property of sigmoid neural networks, and the concept of sliding mode control. By making approximation for the performance index, it is first relaxed to a quadratic program, and then, a linear algebraic equation with unknown terms. An auxiliary system is designed to reconstruct the input-to-output property of the control systems with unknown dynamics, so as to tackle the difficulty caused by the unknown terms. Then, by considering the property of the sliding-mode surface, an explicit adaptive near-optimal control law is derived from the linear algebraic equation. Theoretical analysis shows that the auxiliary system is convergent, the resultant closed-loop system is asymptotically stable, and the performance index asymptomatically converges to optimal. An illustrative example and experimental results are presented, which substantiate the efficacy of the proposed method and verify the theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit multi-channel resistor–resistor-string digital-to-analog converter (RRDAC) using a shared R-string scheme for an area efficient display source driver. The proposed scheme relaxes the required equivalent resistance value of R-string of each channel by sharing a channel R-string that is simultaneously connected to the same tap of a global R-string. Thus, the overall DAC size can further be minimized while maintaining the same accuracy. That is, if the proposed scheme is implemented with the same size as the conventional RRDAC, higher accuracy can also be achieved. For the verification of shared resistor string scheme, a 12-bit RRDAC was fabricated using 0.35- $\mu$ m standard CMOS technology. Compared with the conventional RRDAC, the proposed design showed a 15% reduction in size, a DNL of 0.49 LSB and an output voltage deviation of 9. 3mV for eight different chips. Also, the area per channel was 0.0465 mm2. [ABSTRACT FROM AUTHOR]

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ($\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB. [ABSTRACT FROM AUTHOR]

In this paper, we develop and test a piecewise model for the reset and set transitions of a bipolar ReRAM memristive device in the flux-charge space, instead of the usual voltage–current one. To do so, we consider the devices as memristors. The model used is very simple and provides accurate simulation results. It also allows the development of simple expressions for the conductance and power consumption, as well as the characterization of the ReRAM memristive device in voltage–current domain by using two points for any reset or set cycle. We consider the case of a ramp input signal with different slopes to obtain the model parameters, and we compare the predictions of our model with experimental results. [ABSTRACT FROM AUTHOR]

This paper focuses on the data-driven filtering problem on nonlinear systems with bounded noises and quantized measurements which are subject to logarithmic quantization. Because the accurate system model is unknown, an almost-optimal data-driven filter is designed from an available data set within the nonlinear set membership framework. The set is composed of system inputs and quantized measurements, which can be more easily obtained than the mathematical model. The logarithmic quantization is dependent on the fact that its quantization error serves as a multiplicative noise which widely exists in many applications. For a further improvement of estimation performance, a preliminary approximation is obtained by neural network technique. Two numerical examples are given to illustrate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

Radix- $2^{k}$ delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutator architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. A 1024-point FFT processor with two parallel data paths is implemented in 65-nm CMOS process technology. The FFT processor occupies an area of 3.6 mm2, successfully operates in the supply voltage range from 0.4–1 V and the maximum clock frequency of 600 MHz. For low voltage, high performance applications, the processor is able to operate at 400 MHz and consumes 60.3 mW or 77.2 nJ/FFT generating 800 Msamples/s at 0.6 V supply. [ABSTRACT FROM AUTHOR]

A common source RF amplifier can be designed to be either power or conjugately matched at the output but not both, since the required load impedances are distinct. In this paper, we have shown that using a drain-gate feedback network brings the power and conjugate match impedances closer together, up to a point where they coincide at a cost of slightly decreased efficiency. We have thoroughly analyzed the output power, return loss, and efficiency tradeoffs and developed a complete design methodology. As a design example, a broadband feedback class-A amplifier has been designed and fabricated in a 130-nm RFCMOS process. The amplifier achieves 7-dBm peak output power and maximum power efficiency of about 20% in the frequency range from 6 to 9 GHz. Input and output return losses are better than 8.5 and 9.5 dB, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a novel amplitude shift keying modulation technique, suitable for biomedical implants, which works by switching a class-E amplifier between two tuned modes of operation selected by the input data level. Using this technique, transmission of power and data could be accomplished with higher power transfer efficiency compared with the commonly used drain/collector amplitude modulation topology. We also present a practical design methodology covering details of the class-E power amplifier together with its inductive link and the proposed modulator circuit. This methodology can be further utilized in other applications like cochlear implants for which we will compare the performance of both topologies at the same operating conditions. Moreover, we implemented both topologies, and we made various physical measurements at the same inductive link and set-up conditions. Both theoretical and measurement results will justify the advantage of our proposed topology and its overall energy efficiency over a typical one (42% to 30%). Utilizing a carrier frequency of 10 MHz and a modulation index of 10%, our system is able to transmit data at a bit rate of 1 Mbps, while delivering 24-mW power at the nominal coil separation of 6 mm. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of a novel broadband low-noise amplifier (LNA) with larger than seven-octave bandwidth. To achieve good impedance matching, flat gain, and low noise over larger than seven-octave bandwidth, the combination technique of shunt-resistive feedback, dual inductive-peaking techniques as well as a compact improved active load supporting broadband RF biasing from dc to 20 GHz, is proposed for LNA design. The gain and noise improvement principles of the proposed technique are also analyzed theoretically. Based on the theoretical study, a three-stage LNA with larger than seven-octave bandwidth, i.e. 0.1 to 20 GHz, is designed and verified using a 0.15- $\mu \text{m}$ GaAs pHEMT technology. The LNA experimental results show a high gain of 28.6 dB, good noise figure of 3.1 to 5.8 dB, and output $P_{\mathrm {-1\,\,dB}}$ of 7.8 to 12.7 dBm over the broad frequency range of 0.1 to 20 GHz. The proposed LNA has a compact chip size of only 1.53 mm2 including testing input/output pads. [ABSTRACT FROM AUTHOR]

In this paper, a control technique is presented for an undamped, pinned–pinned Euler–Bernoulli beam with control inputs and bounded disturbances on one boundary. The control strategy drives the system to its origin at an arbitrary exponential rate in the presence of the disturbances. This is achieved in two main steps. First, a backstepping transformation is used to convert the marginally stable Euler–Bernoulli beam system to a new form that has an exponentially stable homogeneous form. Control inputs are needed to fully convert the system to this form; however, since they are distorted by unknown bounded disturbances, the next step implements a sliding mode controller to account for them. The proposed sliding manifolds require a combination of classical and “second order” techniques in order to avoid discontinuous chattering on the physical system. Therefore, the continuous sliding mode controllers developed return the beam to its origin at an arbitrary exponential rate, and do so in the presence of unknown bounded disturbances on the boundary. The main contributions of this paper with respect to previous backstepping designs for the Euler–Bernoulli beam are that all three of the following goals are accomplished together: (i) steady-state position is the origin, (ii) decay rate has no theoretical restrictions, and (iii) is robust to bounded disturbances. [ABSTRACT FROM AUTHOR]

The stability property of delayed neural networks (NNs) along the whole delay axis is studied in this paper. Such a complete stability problem with respect to the delay parameter has not been addressed in the community of NNs. Most of the existing studies focus on the stability interval of delay starting from zero and are not applicable for the complete stability problem. In this paper, we will present some examples to show that there are various types of stability intervals for NNs, demonstrating the necessity of the complete stability analysis. We will adopt a frequency-sweeping approach to study delayed NNs in this paper. As a result, the complete stability problem with respect to delay for NNs can be systematically solved. The approach is applicable in the general case and simple to implement. Finally, some representative examples illustrate the approach. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’s output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation. And the coupling coefficient ( $k$ ) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power ( $P_{\mathrm {sat}}$ ), and 12.9-dBm output 1-dB compression point ( $P_{\mathrm {1\,dB}}$ ). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz). [ABSTRACT FROM AUTHOR]

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especially for the clock source with LPF-J, our equation predicts that the return-to-zero (RZ) DAC SNR is better than what the conventional analysis foresees due to the high-pass filter function derived in our analysis. Our analysis completely captures both WN-J and LPF-J in NRZ and RZ DAC, and is verified in both MATLAB simulation and measurement with the difference of less than 2 dB. [ABSTRACT FROM AUTHOR]

Elliptic curve cryptography (ECC) has received attention, because it can achieve the same security level as other asymmetric methods while using a key with smaller length. Although ECC is more efficient compared with other asymmetric methods, the fast computation of ECC is always desirable. In this paper, a fixed-base comb point multiplication method has been used to perform regular point multiplication. In addition, two low-complexity (LC) and low-latency (LL) architectures for the regular point multiplication using fixed-base comb method have been proposed. The point multiplication architectures have been implemented using field-programmable gate array and application-specific integrated circuit (ASIC). The LC architecture implementation results over $GF(2^{233})$ , $GF(2^{163})$ , and $GF(2^{283})$ show 62%, 46%, and 152% efficiency improvement, respectively. In addition, the LL architecture has 55%, 44%, and 76% reduction in point multiplication required time, respectively, over $GF(2^{233})$ , $GF(2^{163})$ , and $GF(2^{283})$. Moreover, ASIC results show 100% energy improvement for the LC architecture implementation results over $GF(2^{163})$. In addition, the LL architecture has 99% reduction in point multiplication required time, respectively, using a pentanomial. [ABSTRACT FROM AUTHOR]