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Using reinforcement learning (RL) algorithm to optimize guidance law can address non-idealities in complex environment. However, the optimization is difficult due to huge state-action space, unstable training, and high requirements on expertise. In this paper, the constrained guidance policy of a neural guidance system is optimized using improved RL algorithm, which is motivated by the idea of traditional model-based guidance method. A novel optimization objective with minimum overload regularization is developed to restrain the guidance policy directly from generating redundant missile maneuver. Moreover, a bi-level curriculum learning is designed to facilitate the policy optimization. Experiment results show that the proposed minimum overload regularization can reduce the vertical overloads of missile significantly, and the bi-level curriculum learning can further accelerate the optimization of guidance policy. [ABSTRACT FROM AUTHOR]

The complexity and size of recent deep neural network (DNN) models have increased significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a viable scaling approach to provide substantial computation capability and on-chip memory for efficient process of such DNN models. However, communication using metallic interconnects in prior chiplet-based accelerators poses a major challenge to system performance, energy efficiency, and scalability. Photonic interconnects can adequately support communication across chiplets due to features such as distance-independent latency, high bandwidth density, and high energy efficiency. Furthermore, the salient ease of broadcast property makes photonic interconnects suitable for DNN inference which often incurs prevalent broadcast communication. In this paper, we propose a scalable chiplet-based DNN accelerator with photonic interconnects named ASCEND. ASCEND introduces (1) a novel photonic network that supports seamless intra- and inter- chiplet broadcast communication, and flexible mapping of diverse convolution layers, and (2) a tailored dataflow that exploits the ease of broadcast property and maximizes parallelism by simultaneously processing computations with shared input data. Simulation results using multiple DNN models show that ASCEND achieves 71% and 67% reduction in execution time and energy consumption, respectively, as compared to other state-of-the-art chiplet-based DNN accelerators with metallic or photonic interconnects. [ABSTRACT FROM AUTHOR]

Tree-based machine learning models, like random forests and decision trees, are low-complexity solutions that provide an efficient prediction for a wide range of applications. These models are particularly interesting for energy-constrained platforms since they can be implemented with simple logical operations. Tree-based accelerators are also intrinsically resilient to errors, and this can be leveraged to boost energy efficiency with approximate computing techniques. The key operations in these models are comparisons to constants, making comparators excellent candidates for approximation. This paper presents a technique to approximate comparisons to constants called C2PAx, which is capable of reducing the area and energy of tree-based accelerators. The method consists in finding alternative constants that reduce circuit area while keeping an efficient prediction performance. It is also shown that the selection of the constant parameters directly influences both hardware complexity and model performance, demanding cross-layer optimization. For that, we extend an existing framework that generates VLSI tree-based accelerators, inserting our approximation proposal that allows selecting the constant parameters that maximize energy efficiency at the cost of minor accuracy drops. Simulation results demonstrate that C2PAx outperforms the Don’t Care logic approximation technique when accuracy and energy are jointly considered. C2PAx trades accuracy for significant reductions in the VLSI area, power, delay, and energy consumption compared to precise models. [ABSTRACT FROM AUTHOR]

This paper investigates the fixed-time stabilization problem for a class of nonlinear systems via event-triggered control. The event-triggered mechanism can be applied to the nonlinear system with the coexistence of low-order and high-order nonlinearities. In order to deal with these low-order and high-order terms as well as achieve the objective of fixed-time stabilization, the initial value of the system is divided into two cases, and then the event-triggered controller is designed, respectively. By switching control theory, it is proved that the nonlinear system is globally fixed-time stable under the designed controller and the Zeno behavior can be excluded. Finally, two simulations show that the proposed technology is effective. [ABSTRACT FROM AUTHOR]

Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a novel all-digital background calibration of timing mismatch for a time-interleaved analog-to-digital converter (TIADC). For two different calibration strategies, the absolute calibration and the relative calibration, the inductive expressions of modulation matrices are derived from the coefficient matrices provided by different estimation methods. Based on the modulation matrix, we develop a digital calibration architecture, which enables the output of TIADC to be modulated firstly before being corrected, so the costly matrix multiplication processing can be avoided. This calibration architecture also enables the estimation process of each channel to be independent and can be executed simultaneously, which accelerates the convergence speed of the timing mismatch. We show the efficiency of the calibration structure by simulations, including examples from the literature. Numerical simulation demonstrates that the convergence speed of the timing mismatch has been improved by at least 27%, compared with the estimation method depending on the specified reference channel. The result of FPGA-based hardware implementation shows that the spurious-free dynamic range (SFDR) is improved by 37.63dB. [ABSTRACT FROM AUTHOR]

In this paper, we present a reconfigurable Physically Unclonable Functions (PUF) based on the Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM), which exploits thermal noise as the true dynamic entropy source. Therefore, the MRAM cells could be configured to random final states with stochastic switching mechanism. The proposed PUF is constructed and reconfigured by combining the small-capacity true random number generator (TRNG) and high-reliability secure hash algorithm (SHA-512), realizing the dynamic transformation between SOT-MRAM based last level cache and PUF (In-Cache-MPUF). Thanks to the full reconfigurability and the high endurance of SOT-MRAM, the proposed In-Cache-MPUF can achieve $10^{\textbf {14}}$ maximum PUF bits per cell, which has greatly motivated the implementations compared with the traditional weak PUFs utilizing the static entropy source of process variations. The Monte-Carlo simulation results using 40 nm technology and a compact MTJ model show that the proposed PUF has desirable randomness as the digitized bit streams passing all the NIST tests, achieving 50.0428% uniqueness as well as 49.9236% uniformity. It also shows comparable reliability to the state-of-the-art works: a maximum bit error rate of 0.14% and 0.12% at 100 °C and 0.9 V, respectively. In addition, the system level performance is tested and validated by gem5. [ABSTRACT FROM AUTHOR]

Approximate computing (AC) has been considered as a promising paradigm to improve the energy-efficiency of computing hardware for error-tolerant applications, with negligible quality degradation to the output. Dividers frequently limit the performance of a computing system; however, they have not received as much attention as multipliers and adders in AC. In this paper, an energy-efficient and high-performance approximate divider is proposed based on logarithmic conversion and piecewise constant approximation. In this design, the range for the conversion between binary and logarithmic numbers is first expanded from $\mathbf {[{0,1}]}$ to $\mathbf {[-0.5,1]}$. A heuristic search algorithm is then devised to find the most accurate constant set to approximate the reciprocal of the divisor, by minimizing a statistical error. The hardware implementation is presented for both floating-point (FP) and integer dividers. With a high configurability, the proposed divider results in a mean relative error distance (MRED) from 2.78% to 0.046%, indicating a high accuracy among state-of-the-art approximate dividers. Compared to the half-precision FP divider, the proposed divider with a MRED of 0.74% can achieve nearly $\mathbf {90\times }$ improvement in PDP. Moreover, compared to state-of-the-art approximate dividers, the proposed design is in the Pareto Frontier in terms of power delay product (PDP) and MRED. The three image processing application results demonstrate that the proposed divider can result in the highest peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) even with truncation. [ABSTRACT FROM AUTHOR]

Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery. [ABSTRACT FROM AUTHOR]

This paper proposes two architectures for the acceleration of Number Theoretic Transforms (NTTs) using a novel Montgomery-based butterfly. We first design a custom NTT hardware accelerator for Field-Programmable Gate Arrays (FPGAs). The butterfly architecture is expanded to a Modular Arithmetic Logic Unit (MALU) and for greater reuse and easier programmability a six-stage pipeline Linux-ready RISC-V core is extended with custom instructions. The performance of the proposed architectures is assessed on a Xilinx Ultrascale+ FPGA and with an Application-Specific Integrated Circuit (ASIC) on $28{n}\text{m}$ CMOS technology. In FPGA, the results for custom acceleration show reductions of 30%, 90% and 42% in the number of Lookup tables (LUTs) and registers, Block RAMs (BRAMs) and Digital Signal Processors (DSPs), while providing a speedup of 1.9 times, in comparison with the state of the art. The ASIC results show that at 1 GHz the proposed architecture is in average 45% and 52% less area and power hungry, respectively, compared to the state of the art. Furthermore, the proposed MALU, operating as an additional execution unit, increases the overall area of the extended RISC-V core by only 10%, without significant changes in the frequency of operation. [ABSTRACT FROM AUTHOR]

As model size and the number of layers increase, Deep Neural Networks (DNNs) demand enormous computational power and throughput to meet exceedingly high prediction accuracy’s of today’s machine learning (ML) applications. Spatial hardware accelerators have been proposed that optimize the dataflow and exploit sparsity to provide a significant decrease in power consumption. As spatial architectures are traditionally designed with metallic interconnects, significant power is expended for data movement for different dataflows. In this paper, we exploit extended wireless technology to design a power-efficient and high-throughput DNN accelerator, e-WiNN, that can be configured for all representative dataflows and arithmetic precisions. We leverage novel circuit design by utilizing Dadda-algorithm based Multiply-and-Accumulate (MAC) circuits for 4-bit, 8-bit and 16-bit inputs to reduce area, power and delay constraints in 14 nm predictive technology. Our novel wireless transmitter integrates on- off keying (OOK) modulator with power amplifier that results in significant energy savings. To reduce the area overhead, we cluster wireless transceivers into groups of four such that both weights and input features can be effectively multicast to reduce the data movement. The energy efficient transceiver circuit is implemented in state-of-the-art BSIM 32 nm FinFET technology model and our link budget considers required RF power for different frequencies and inter-PE distance at three different antenna directivities including isotropic. Our detailed RTL modeling and cycle-accurate simulation results show that e-WiNN achieves 36.3% latency reduction and 76.1% energy saving when compared to state-of-art wire interconnected accelerators; 70.3% area reduction and 41.6% energy saving at the cost of 11% latency increase when compared to prior wireless accelerators on various neural networks (AlexNet, VGG16, and ResNet-9/50). [ABSTRACT FROM AUTHOR]

Neural networks (NNs) with large scales of artificial neurons are increasingly used in recognition and classification tasks. In power-constrained scenarios, the tradeoff between performance and hardware consumptions must be carefully evaluated before silicon tape-out. In this paper, we proposed a systematic approach to design ultra-low power NN system. This work is motivated by the facts that NNs are resilient to approximation in many of the computations and NNs are outputting statistical tensors which are acceptable to less-than-perfect results. We resort to the front-back end approach with a twofold aim: (1) a fast and accurate design approach is proposed by estimating the computing quality of low-power approximate adder arrays, and it is adopted to evaluate the neural network system; (2) a quality configurable engine with different approximation degrees while processing NNs is implemented. The proposed work is demonstrated with a comprehensive keyword spotting (KWS) system as an ultra-low power NN engine. The experimental environment is setup with ten keywords from the google speech command dataset (GSCD) using an industrial 22-nm ultra-low-leakage (ULL) process. Comparing to the state-of-the-art KWS processors, the proposed approximate NN engine can demonstrate over 60% improvement in power efficiency and $1.1\times $ area efficiency while achieving similar recognition accuracy. [ABSTRACT FROM AUTHOR]

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC. [ABSTRACT FROM AUTHOR]

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm2. When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage. [ABSTRACT FROM AUTHOR]

The device faults commonly exist in microgrids (MGs) and often undermine the system stability. However, the existing distributed methods generally design control protocols based on the absence of faults or only considering actuator faults, which limits the applicability of controllers in MG systems. Therefore, this paper investigates an adaptive prescribed fixed-time performance (PFTP) consensus fault-tolerant control (FTC) problem for the voltage regulation of a nonlinear islanded MG inverter-based distributed generators (DGs) with output contactor and actuator fault via the state event-triggered mechanism. The PFTP method for the voltage restoration synchronization error is proposed by constructing a novel performance function to increase the speed of voltage recovery. Based on the estimation properties of fuzzy logic system, an unknown nonlinear function and the residual term of output contactor are estimated. Then, an adaptive state event-triggering mechanism is designed to reduce the communication burden, and its main advantage is that the control protocol is updated in the aperiodic way at the triggering instants. Further, according to backstepping technology, a novel adaptive event-triggered consensus FTC protocol is constructed to achieve the voltage regulation of islanded MG, and a parameter adaptive law is designed to compensate the adverse effects of the output contactor fault. Based on the Lyapunov stability theory, it is proved that the voltage recovery synchronization error satisfies the PFTP, and all signals in the closed-loop systems are cooperatively uniformly ultimately bounded. Finally, the proposed control strategy is also validated by using the MATLAB. [ABSTRACT FROM AUTHOR]

Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and thus has potential in privacy-preserving computing. However, efficiency is still the bottleneck. In this paper we present an area-efficient and highly unified reconfigurable multi-core architecture (named ReMCA) for full Residue Number System (RNS) variant of Fan-Vercauteren variant of Brakerski’s scheme (RNS-BFV), which employs a variable number of reconfigurable processing elements (PEs) and RNS channels. The PE unit can be flexibly configured as NTT, INTT or modular multiplier, thereby avoiding the need of other extra computational units. To reduce the computational complexity, ReMCA merges the pre/post-processing into NTT/INTT and unifies the read/write structure of NTT and INTT. Also, a conflict-free memory access pattern that doesn’t need separate bit-reversal operation is proposed to optimize the memory access. Furthermore, targeting different computational requirements, a unified hardware architecture mapping model and data memory organization model are introduced, and all the computing units that RNS-BFV involved are optimized and mapped on ReMCA. ReMCA is evaluated on a Xilinx Virtex-7 FPGA platform. Running at 250MHz, it can perform 2260 homomorphic multiplication per second. When normalized to the same parameter set, the throughput and Area-Time-Products (ATPs) of ReMCA achieve $1.45\times \sim 5.51\times $ and $1.58\times \sim 5.12\times $ improvements. [ABSTRACT FROM AUTHOR]

Multiple Signal Classification (MUSIC) is a high-performance Direction of Arrival (DOA) estimation algorithm, which has been widely used. The algorithm needs to calculate the covariance matrix, eigenvalue decomposition and spectral peak search. In the paper, the hardware structure of the existing Jacobi algorithm for Hermitian matrices is proposed. On this basis, a novel hardware acceleration of the MUSIC algorithm for sparse arrays and uniform linear arrays is proposed, and the sparse array is a nested array. There are two designs, Design 1 supports 1~10 nested array elements or 1~32 uniform linear array elements, distinguishes 1~32 sources, configures snapshots 1~2048, and the maximum number of iterations and iteration accuracy of the complex Jacobi algorithm. Design 2 only needs $101.8~\mu $ s to complete a DOA estimation when the number of array elements is 8, the number of sources is 1, and the snapshots is 128. In more detail, the Root Mean Squared Error (RMSE) of both can reach 0.03°. The logic resources on the Zynq-7000 development board are 14,761 and 28,305 Look-Up Tables (LUTs), respectively. [ABSTRACT FROM AUTHOR]

This paper considers weakly and strongly input-to-state stability (ISS) of a discrete-time time-varying delayed system with synchronous impulses and switches. By employing the uniformly asymptotically stable function and mode-dependent dwell time conditions, ISS criteria are derived using the Krasovskii and Razumikhin techniques. The time differences of the Krasovskii functionals or the Razumikhin functions can be mode-dependent and time-varying, which release constraints of some existing results. As subsequent results, we apply the derived ISS criteria to the multi-agent systems (MASs). Finally, two examples considering the quasi-consensus of MASs are given to verify the established results. [ABSTRACT FROM AUTHOR]

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted input-referred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations. [ABSTRACT FROM AUTHOR]

In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a field programmable gate array (FPGA)-based, high-performance and energy-resource efficient stereo matching processor. The proposed processor executes block-level PatchMatch-based stereo matching algorithm with a random search strategy to avoid estimation of all disparity levels. To take advantages of different block scales, a coarse-to-fine multi-scale propagation (MSP) scheme is proposed for label update. Based on that, a dedicated hardware architecture is further proposed to explore the benefit of the algorithm. Experimental results show that the proposed FPGA-based processor, running at 350MHz, achieves a peak performance of $1920\times 1080.165$.7 frame per second (FPS) at 128 disparity levels with 3.35W power dissipation. The energy and resource efficiency of the proposed design outperforms state-of-the-art FPGA-based stereo matching processors. When disparity level increases to 256, the computing resource increment of the proposed design is much less than existing designs because random search instead of winner-takes-all (WTA) is utilized. Moreover, unlike existing dedicated stereo matching processors which output only disparity information, the proposed design is also capable of deriving plane slant. This information can be beneficial for follow-up tasks like 3D reconstruction. [ABSTRACT FROM AUTHOR]

This paper focuses on establishing an adaptive boundary observer for fully coupled reaction-diffusions partial differential equations (PDEs) containing unknown parameters. Firstly, the state error system is transformed into an intermediate system by finite dimensional backstepping-like transformation, and then we convert the intermediate system to a target system by infinite dimensional backstepping transformation. Secondly, a least-squares type parameter adaptive law is given. Thirdly, exploiting an ad hoc persistent excitation condition, the exponentially convergent of the observer will be established by applying Lyapunov functional. Finally, we use simulation analysis for Chemical Tubular Reactor model to demonstrate the validity of the results. [ABSTRACT FROM AUTHOR]

This paper proposes a distributed cooperative control strategy for cyber-physical microgrids in a distributed sparse network with communication delays by using predictive control theory, which enables each distributed generator (DG) unit to achieve voltage restoration. In the proposed control strategy, we first design a primary droop-free model predictive controller to make the output voltage track its nominal set points timely, with the neighbor-based error information a secondary distributed coordinated predictive controller is then proposed to actively compensate the general communication delays for cyber-physical microgrids caused by low-bandwidth communication networks. Sufficient conditions, in terms of communication network connectivity and control gains for the system stability are derived by using the tools of special matrix theory and algebraic graph theory. The proposed control protocols are fully distributed and can be implemented through a sparse communication network and thus, satisfy the plug-and-play feature of the future smart grid. The effectiveness of the control strategy in compensating communication delays is also verified by real-time simulation experiments in OPAL-RT on a test microgrid. [ABSTRACT FROM AUTHOR]

Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a single type of neuron model, which has slow speed and poor scalability. This paper proposes a general FPGA-based neuromorphic hardware acceleration platform (FPGA-NHAP), supporting the effective inference and acceleration of SNN network with low power, high speed and good scalability. First, a neuron computing unit is designed to simulate the both LIF and Izhikevich (IZH) neurons with the parallel spike caching and scheduling technique. Second, a novel integrated driven update algorithm is proposed to complete the spike encoding of external data, reducing the waiting time of neuron state update effectively. Third, the proposed platform is implemented using a RISC-V processor and a Xilinx FPGA, simulating 16,384 neurons and 16.8 million synapses with a power consumption of 0.535 W. Finally, two different three-layer SNN networks are deployed on the proposed platform for recognition tasks on the MNIST and Fashion-MNIST datasets, achieving the accuracy of 97.70%, 85.14% (LIF) and 97.81%, 83.16% (IZH), frame rates of 208 frame/s, 128 frame/s (LIF) and 206 frame/s, 141 frame/s (IZH), respectively. [ABSTRACT FROM AUTHOR]

This paper presents a new architecture, based on CORDIC and parabolic synthesis methodology, for computing Nth root of a complex number. The proposed architecture uses the pretreatment for normalization and parabolic synthesis method to calculate the Nth root of modulus of the input complex number and performs the conversion between the plane coordinate form and the polar coordinate form of the complex number by CORDIC, which not only ensures the accuracy but also has an ultra-low computation latency. MATLAB simulation result indicates that our proposed method can calculate the Nth root of the complex numbers in the form of fixed-point number with an error of $2.16 \boldsymbol {\times {10^{ - 6}}}$. Under TSMC 40nm CMOS technology, the report shows that the area consumption is $27390.72 \boldsymbol {\mu m^{2}}$ at the frequency of 1GHz and the power consumption is 2.3549mW. More importantly, the computation latency of the proposed architecture is only 60.18% of the latest architecture in the same calculation accuracy. [ABSTRACT FROM AUTHOR]

Memristive LSTM networks have been proven as a powerful Neuromorphic Computing Architecture (NCA) for various time series forecasting tasks and are recognized as the next generation of AI. However, a lack of model explainability makes it hard to properly interpret forecasting results for existing memristive LSTM networks, which makes this NCA unreliable, unaccountable and untrustworthy. In this paper, an interpretable memristive (IM) LSTM network design is proposed for time series forecasting, where the mixture attention technique is embedded into IM-LSTM cells for characterizing the variable-wise feature and the temporal importance. The updating rules and training approach are also presented for this interpretable memristive LSTM network. We evaluate this approach on a probabilistic residential load forecasting task incorporating PV. By improving model interpretability, the most influential predictive factors can be verified by Built Environment domain experts, demonstrating the effectiveness of our design. [ABSTRACT FROM AUTHOR]

This paper introduces a new true random number generator (TRNG) based on a three-edge ring oscillator. Our design uses a new technique with a time-to-digital converter to effectively acquire jitter accumulated independently by each edge. As a part of the security evaluation, we present the stochastic model of the TRNG’s digital noise source and estimate a lower bound of the min-entropy per random bit. Starting from the obtained entropy bound, we propose a procedure for selecting and implementing an area-efficient and throughput-optimal post-processing function based on the best known linear codes that will increase the output min-entropy rate to more than 0.999. The proposed TRNG exquisitely balances low design effort and resource consumption with high throughput and a high min-entropy rate, making it more suitable for randomness-demanding and resource-constrained platforms than the state-of-the-art. The complete implementation of the TRNG digital noise source and the post-processing occupies 33 slices and achieves a throughput of 12.5 Mbps on Xilinx Zynq-7000 FPGAs. The min-entropy of the generated random bits is assessed by NIST SP 800-90B entropy estimators, and the tested sequences pass the AIS-31 test suit. [ABSTRACT FROM AUTHOR]

Many energy harvesters (EH) deliver an ac voltage and require a rectifier as a consequence. This paper describes how the rectifier affects the power flow transmitted from the EH to the load and how to tackle the different voltage amplitudes. This study has been performed using analytical calculations, numerical modeling and experiments. To reach the maximum power transfer, conventional methods apply a fraction of the open-circuit voltage delivered by the EH. In contrast, this study points out that the optimum operating point must be shifted by a quantity depending on the rectifier characteristics. This difference is particularly important when the EH provides relatively small ac voltages. Two classic rectifiers are covered: a diode bridge (DB) and a MOSFET bridge (MB). An approximated solution of the analytical model is proposed and allows to optimize the EH without cumbersome numerical computations. Experiments are conducted first with a function generator and then with an electromagnetic EH prototype. The outcomes from the analytical model and the numerical model are in good agreement with the experimental results. A new regulation method is proposed for maximizing the power transferred from the ac EH to the load. [ABSTRACT FROM AUTHOR]

Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q, $Q_{T} < Q_{VAR}$ , and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in $Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger $Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −194.2 dBc/Hz. [ABSTRACT FROM AUTHOR]

In this paper, a miniature dual-band absorptive bandstop filter (ABSF) design with improved lower passband performance is proposed. Specifically, a stepped-impedance short-circuited stub is introduced to a bridged-T coil-based dual-band ABSF design, such that the insertion loss around the desired passband center frequency can be largely reduced while the absorptive stopband performance remains intact. This also helps equalize the lower passband insertion loss response and achieve a flatter passband, which is especially advantageous when cascading multiple ABSFs for improving the stopband rejection or increasing the number of stopbands. Closed-form design formulas are established to facilitate the synthesis of proposed dual-band ABSF. As an example, a 4.8/9.6-GHz dual-band ABSF in GaAs is realized with a measured insertion loss within 0.85± 0.12 dB from dc to 2.6 GHz. The circuit size is only 1.6 mm $\times $ 1.84 mm, and the corresponding electrical size is $0.013\lambda _{0} \times 0.015\lambda _{0}$ at the designated passband center frequency of 2.4 GHz. Application of the proposed dual-band ABSF for the passband performance improvement of cascaded ABSF designs is also demonstrated, and good performance is obtained. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

This paper adopts a quantization-dependent Lyapunov function to study the output feedback stabilization problem of a switched system subject to output event-triggered sampling and quantization. First, a new event-triggered mechanism related to quantization parameters is proposed, which can obtain a trade-off between the event-triggered frequency and quantization density on the premise of ensuring asymptotic stability of the switched system. Moreover, sufficient conditions are obtained to ensure asymptotic stability of the switched system by a quantization-dependent Lyapunov function. Lastly, through a numerical simulation and PWM-driven boost converter system, we demonstrate the availability of the proposed quantization-dependent Lyapunov function and event-triggered mechanism methods based on quantization parameters, respectively. [ABSTRACT FROM AUTHOR]

In this paper, an analysis method is presented to mathematically characterize the harmonic current generated by the voltage at fundamental or harmonic frequency in the transistor of a high-frequency harmonic oscillator. Using this analysis method, the relationship between the second harmonic voltages and the fourth harmonic drain current in the transistor is investigated, and the requirement on the second harmonic voltages for fourth harmonic boosting is found. Moreover, an approach of modeling the voltage-current relationship in the transistor of a high-frequency harmonic oscillator at harmonic frequency as an equivalent linear relationship is proposed. This modeling method facilitates the design of the second harmonic embedding network around the transistor, thus helping to propose a harmonic oscillator topology in which the requirement on the second harmonic voltages for fourth harmonic boosting is fulfilled. Using the proposed fourth harmonic boosting technique, a 0.6-THz radiator array is designed in 40-nm bulk CMOS. In measurement, the 0.68- $\text {mm}^{2}$ radiator array achieves a radiated power of 0 dBm and a DC-to-THz efficiency of 0.08% at 586.7 GHz under a 0.9-V supply voltage. [ABSTRACT FROM AUTHOR]

Residual block is a very common component in recent state-of-the art CNNs such as EfficientNet/EfficientDet. Shortcut data accounts for nearly 40% of feature-maps access in ResNet152. Most of the previous DNN compilers/accelerators ignore the shortcut data optimization. This paper presents ShortcutFusion, an optimization tool for FPGA-based accelerator with a reuse-aware static memory allocation for shortcut data, to maximize on-chip data reuse given resource constraints. From TensorFlow DNN models, the proposed design generates instruction sets for a group of nodes which uses an optimized data reuse for each residual block. The accelerator design implemented on the Xilinx KCU1500 FPGA card $2.8\times $ faster and $9.9\times $ more power efficient than NVIDIA RTX 2080 Ti for $256\times 256$ input size. Compared to the result from baseline, in which the weights/inputs/outputs are accessed from the off-chip memory exactly once per each layer, ShortcutFusion reduces the DRAM access by 47.8-84.8% for RetinaNet, Yolov3, ResNet152, and EfficientNet. Given a similar buffer size to ShortcutMining, which also “mine” the shortcut data in hardware, the proposed work reduces off-chip access for feature-maps $5.27\times $ while accessing weight from off-chip memory exactly once. [ABSTRACT FROM AUTHOR]

Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of $m$ contiguous bits (a segment of $m$ bits) is extracted from each of the two $n$ -bits operand, the two segments are in input to a small $m\times m$ internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications. [ABSTRACT FROM AUTHOR]

In this paper, two types of coplanar stripline (CPS)-based multimode stepped-impedance resonators are proposed for exploration of wideband balanced filters with intrinsic common-mode (CM) suppression. Such CPS multimode resonators (MMRs) can be readily terminated with either a pair of open- or short-circuited ends with no need of via holes. With resorting to a proper impedance ratio, the first three modes of each MMR are assembled to construct a wide differential-mode (DM) passband. Afterwards, two distinctive broadside-coupled sections are further investigated based on their open- and short-ended circuit models, respectively. Characteristic impedances and effective dielectric constants can be adequately obtained by virtue of an efficient quasi-static approach under the odd- and the even-mode operations. As such, two types of CPS-MMR-based bandpass filters each with five transmission poles are synthetically designed. For experimental validation, the proposed balanced filters are finally fabricated and measured with the help of two identical pairs of balanced-to-balanced microstrip-to-CPS transitions. Theoretical, simulated, and measured results are found in reasonable agreement with each other with/without the transitions, thus demonstrating that the proposed CPS-based MMRs are well characterized with the wideband DM transmission and intrinsic CM suppression. [ABSTRACT FROM AUTHOR]

Private Set Intersection Cardinality (PSI-CA) is one of the most concerned issues with the protection of privacy, in which two parties jointly compute the intersection cardinality without revealing their respective private sets. There are important applications of PSI-CA in real society, e.g., strongly privacy-preserving data statistics in contact tracing for health authorities to fight the outbreaks of highly contagious diseases. In this paper, we present a novel quantum PSI-CA protocol, in which we adopt oblivious quantum key distribution, secure quantum summation and quantum counting algorithm. The proposed PSI-CA protocol not only ensures the approximatively perfect security but also achieves the linear communication complexity, i.e., ${O(N)}$. Furthermore, we define a new privacy protection problem, i.e., Privacy-preserving Condition Query (PCQ), and provide an efficient solution to the PCQ problem based on the proposed quantum PSI-CA protocol. Finally, we verify the correctness and the feasibility of the proposed quantum PSI-CA protocol by circuit simulations in IBM Qiskit. [ABSTRACT FROM AUTHOR]

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOx memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between $5.2\times - 17.3\times $ , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of an oscillator-doubler architecture which is used to generate THz signals. In this architecture, the doubler obtains the optimum fundamental-frequency load impedance for second harmonic generation without causing problems related to instability. The oscillator creates voltages close to the optimum voltage condition, which leads to maximum power being delivered to the doubler connected to the oscillator tank. Compared to a signal generator composed of an oscillator and a conventional doubler with short-circuit load at the fundamental frequency, the proposed circuit has higher output power and DC-to-THz conversion efficiency. Based on this architecture, a 0.3-THz signal generator is designed in 40-nm CMOS. In this 0.3-THz signal generator, an inductor-sharing configuration is proposed to increase the transistor size in the cross-coupled oscillator, thus increasing the power density of the signal generator. Besides, the impact of the doubler fundamental-frequency load impedance on the conversion gain of the doubler is introduced. Also, a method of suppressing the unwanted mode in the cross-coupled oscillator is proposed. The output of this circuit is radiated through on-chip antennas. The measured radiated power and the DC-to-THz efficiency of the chip are -3.8 dBm and 0.37%, respectively, with an output frequency tuning range of 4.8%. [ABSTRACT FROM AUTHOR]

Of particular interest in this paper is to study the active synchronization (act-synchronization) problem for double-integrator network systems without velocity information. To this end, scaling parameters are suggested to quantify the degree of act-synchronization for different agents. And weighted gains are employed to assure that there is a simple zero eigenvalue with the other ones sharing positive real parts. An auxiliary variable is introduced to mitigate the unavailability on velocity information. Thus only the directed spanning tree requirement in the content of algebraic graph theory is required. This exhibits a clear distinction from signed-graph or scaled consensus as non-unitary signs for scaling parameter and weighted gain are allowed. It is shown that the condition for act-synchronization is related to weighted gain, scaling parameter, the real and imaginary parts of the involved eigenvalues. With the constraint on identical weighted gain and scaling parameter for position and auxiliary variables, it is proven that act-synchronization can be exponentially guaranteed using the Lyapunov-based technique. Finally, the multiple unmanned ground vehicles system and the 10-generator in IEEE 39-bus system are given to facilitate the proposed configuration and the theoretical findings. [ABSTRACT FROM AUTHOR]

This paper deals with global synchronization problem of multiple discrete-time Markovian jump memristor-based neural networks (DTMJMNNs) with mixed mode-dependent delays via a novel event-triggered impulsive coupling control (ETICC). The parameters of the multiple DTMJMNNs and the mixed time delays (both discrete and distributed delays) switch randomly according to a Markov chain. In the ETICC strategy, the controller does not work all the time, but only works at impulse instants determined by specific events. In particular, the coupling matrix can be non-Laplacian. By using the Lyapunov stability theory, linear matrix inequalities (LMIs), and the Kronecker product, some sufficient conditions for global synchronization of multiple DTMJMNNs under the event-triggered strategy are derived. Two examples are presented to test the validity of the theoretical analysis results. [ABSTRACT FROM AUTHOR]

Large-scale neuromorphic computing requires the multi-chip network to provide high computing power. Efficient routing schemes and on-chip router design are necessary for handling various inter-chip transmission patterns. In this paper, we propose a hybrid-mode on-chip router that supports both multicast and unicast routing for the large-scale neuromorphic simulation. Two routing schemes, namely Cache-like Spike Weight Indexing and General Unicast Flow Control, are proposed to accommodate the chip-to-chip transmission of spike and non-spike data. This work is evaluated on a neuromorphic platform built with an $8\times 8$ FPGA chips array. Running a simulation of 1M neurons at 200MHz, the proposed router achieves a processing latency of 25ns and a chip-to-chip latency of 287ns. Working in the unicast mode, the router can synchronize status flags of all chips within $5 ~\mu \text{s}$. Moreover, it reduces the peak spike traffic by 25.65% with the help of Load-aware Multicast Routing, compared with other multicast routing strategies. [ABSTRACT FROM AUTHOR]

Spatially coupled serially concatenated codes (SC-SCCs) are constructed by coupling several classical turbo-like component codes. The resulting spatially coupled codes provide a close-to-capacity performance and low error floor, which have attracted a lot of interest in the past few years. The aim of this paper is to perform a comprehensive design space exploration to reveal different aspects of SC-SCCs, which is missing in the literature. More specifically, we investigate the effect of block length, coupling memory, decoding window size, and number of iterations on the decoding performance, complexity, latency, and throughput of SC-SCCs. To this end, we propose two decoding algorithms for the SC-SCCs: block-wise and window-wise decoders. For these, we present VLSI architectural templates and explore them based on building blocks implemented in 12nm FinFET technology. Linking architectural templates with the new algorithms, we demonstrate various tradeoffs between throughput, silicon area, latency, and decoding performance. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps. However, because SNNs contain extra time dimension information, the SNN accelerator will require more buffers and take longer to infer, especially for the more difficult high-resolution object detection task. As a result, this paper proposes a sparse compressed spiking neural network accelerator that takes advantage of the high sparsity of activation maps and weights by utilizing the proposed gated one-to-all product for low power and highly parallel model execution. The experimental result of the neural network shows 71.5% mAP with mixed (1,3) time steps on the IVS 3cls dataset. The accelerator with the TSMC 28nm CMOS process can achieve $1024\times 576.29$ frames per second processing when running at 500MHz with 35.88TOPS/W energy efficiency and 1.05mJ energy consumption per frame. [ABSTRACT FROM AUTHOR]

In this paper, a class of flexible riser systems modeled by partial differential equations (PDEs) with the backlash is considered. The backlash is formulated as the addition of a linear input and a interference-like term, then an new auxiliary item is introduced to compensate for the impact of this backlash. In addition, the constraint problem for the position and the velocity is also taken into consideration. To solve this constrain problem, the logarithmic barrier Lyapunov function is employed. For the flexible riser system, two kinds of adaptive controllers are proposed under the following two cases. One controller is designed when only the parameter of backlash is unknown. On the basis of this result, the other controller is presented when some system parameters cannot be measured through actual measurement. Then, combing the theory of Lyapunov stability, the two controllers can guarantee the boundedness of all signals in the closed-loop flexible riser system. Further, both the position and the velocity satisfy their corresponding constraint condition. Finally, the simulation example verifies that the proposed control method is effective. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 $\mu \text{s}$ , overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL. [ABSTRACT FROM AUTHOR]

This paper investigates global stabilization via adaptive event-triggered output feedback for a class of uncertain nonlinear systems. Typically, unknown polynomial-function rate is admitted in the unmeasurable-state dependent growth of the systems. This calls for an advanced compensation strategy based on dynamic high gain, which in turn requires more intelligent execution in the event-triggered control architecture. To this end, a novel event-triggering mechanism is designed with two events separately evaluating the behaviors of dynamic gain and the controller signal. Particularly, the event on controller signal is enforced to suspend for a certain time after each execution to guarantee a positive lower bound for the inter-execution intervals. More importantly, the suspension time and the threshold therein are both online adjusted according to dynamic gain (rather than pre-specified), which could become small enough as the dynamic gain increases. This ensures timely execution for the effectiveness of adaptive compensation. Then, with the dynamic gain delicately designed to counteract the influence of the execution error, an event-triggered controller via adaptive output feedback is proposed to make the original system states and observer states converge to zero. Further attempt is performed for more efficient resource saving and disturbance tolerance. [ABSTRACT FROM AUTHOR]

In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction. [ABSTRACT FROM AUTHOR]

As the low-density parity-check (LDPC) code has a powerful error-correcting performance and can achieve high throughput, it is being used in many application areas and recently adopted as a channel coding method in the 5G New-Radio communication standard. Unlike other LDPC codes, the 5G LDPC code has various irregular lifting sizes to support diverse message lengths. To meet the demanding requirements of the 5G standard, many solutions have been presented, but all of them are either impractical or fail to satisfy all the requirements. This paper, for the first time, proposes an area-efficient QC-LDPC decoder that satisfies the peak throughput requirements of the 5G standard and supports all the lifting sizes specified in the 5G standard. Instead of relying on full parallelism like in the previous works, this work tries partial parallelism to mitigate the hardware complexity, which leads to high efficiency in hardware complexity. In addition, a novel memory access scheduling method is proposed to solve the data access and alignment problems caused by the partially parallel structure, which is effective in supporting all the lifting sizes. A LDPC decoder realized in 65-nm CMOS technology demonstrates that its decoding throughput is greater than 20Gbps and its area is smaller than the existing decoders. [ABSTRACT FROM AUTHOR]

In this paper, a highly efficient gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) from 4.6 to 5.5 GHz with the consideration of the influence of the peaking transistor’s output capacitor $(C_{\mathrm {out}}$) operated in Class-C state is presented. Based on the load-modulation behavior analysis, the effect of the $C_{\mathrm {out}}$ of the peaking transistor on the performance of the wideband DPA has been theoretically analyzed for the first time by directly evaluating the value of the peaking transistor’s $C_{\mathrm {out}}$. A hybrid matching technique has been proposed to ensure that the DPA can realize a proper load-modulation with high back-off efficiency in a wide bandwidth. In this method, the peaking transistor is matched using a simple T-shape band-pass type network with the $C_{\mathrm {out}}$ of the peaking transistor in Class-C operation state compensated properly, while the carrier transistor is matched using a 2-point matching method. For verification, a wideband GaN MMIC DPA with the frequency range of 4.6 to 5.5 GHz was designed using a 0.25- $\mu {\mathrm{ m}}$ GaN on silicon-carbon high-electron-mobility transistor process. Experimental results show that the fabricated DPA can realize the output power of 41.1-41.6 dBm and the drain efficiency (DE) of 57.6%-63.3% at saturation in the whole frequency band. The measured DE at 6-dB power back-off is 51%-56.4%. Good linearity with high average efficiency performance was obtained when excited by a 160-MHz modulated signal after linearization. [ABSTRACT FROM AUTHOR]