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High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They include a brief description of each converter, tables and curves with relevant information, such as voltage gain, voltage stresses and component count, and the identification of the use of coupled inductor or transformer based on the analysis of dc magnetizing current. Moreover, theoretical analysis and experimental results on a 50 kHz and 200 W prototype of selected isolated SEPIC with voltage doubler cell are presented to validate the proposed topology and concept. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CS value, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2 in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMT of the oscillator at 10 MHz offset are −188.2 dBc/Hz and −200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from −104.1 to −108.2 dBc/Hz at 1 MHz offset. The jitter FoMj is −236.2 dB. [ABSTRACT FROM AUTHOR]

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]

This paper introduces a fully integrated switched-capacitor (SC) DC-DC boost converter suitable for energy harvesting in miniature sensor systems with varying harvesting source and battery voltages. Unlike the conventional SC DC-DC boost converters, where efficiency is optimized only for a few topology-dependent voltage conversion ratios (VCRs), the proposed soft-charging-based SC converter achieved VCR-insensitive evenly high efficiency for a wide range of input and output voltages. A test chip was fabricated in 180nm process, and the measured peak efficiency and average efficiency are 85.3% and 83.6%, respectively, for 1.8V regulated output voltage and a wide range of input voltages (0.95–1.8 V). Also, a peak efficiency of 88.9% and average efficiency of 87.6% are achieved for a wide range of battery output voltages (3.0–4.2 V) and a 1.2V harvesting source input voltage. [ABSTRACT FROM AUTHOR]

Ring amplifiers are an advantageous new amplifier architecture, but designing them needs to be done in a time consuming process using manual transient simulations. AC based design criteria are of limit usability, because of their large signal operation. This paper presents an alternative design approach for ring amplifiers. A set of cost functions and parameters is developed and the parameters’ effect on the amplifier’s stability, accuracy and power consumption is explained in detail. The optimization process is derived from a simple ring-amplifier model and a stability criterion. This criterion is analyzed in the context of circuit parameters, design constraints and other ring-amplifier designs. A new battery-based self-biased ring-amplifier architecture is introduced and the first stage integrator of a switched-capacitor Delta-Sigma modulator is realized using the described ring-amplifier architecture. The proposed optimization process is successfully performed using 180 nm and 40 nm technology nodes (second node with two supply voltages) and the three designs are analyzed and compared. The optimization process is derived from a basic ring-amplifier model and can be applied to other ring-amplifier structures. [ABSTRACT FROM AUTHOR]

This paper presents a thermal/RF hybrid energy harvester. The energy harvesting system can scavenge energy from a thermoelectric generator (TEG) and a radio-frequency (RF) energy source simultaneously, and deliver the combined power to a single load. Two techniques are employed in the system to increase the end-to-end efficiency; the rectifying-combination technique is proposed to eliminate the power loss associated with a dedicated AC-DC converter before the combiner and an improved fractional open-circuit voltage (FOCV) maximum power tracking (MPPT) is considered for a high average efficiency. A dynamic power path control extracts the maximum RF power from a cross-coupled differential rectifier, and also behaves as an AC/DC energy combiner. The thermal/RF harvester system achieves a measured peak end-to-end power conversion efficiency (PCE) of 63.4%. The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester. Fabricated in 0.18 $\mu \text{m}$ CMOS technology, the prototype operates at a thermal input voltage ranging from 40 mV to 400 mV and an RF power from −18 dBm to −3 dBm and delivers an output voltage of 1.8 V. The total area of the fabricated circuit prototype is 1.22 mm2. [ABSTRACT FROM AUTHOR]

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power. [ABSTRACT FROM AUTHOR]

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their conversion ratios is also proposed in this work. To verify this method, we demonstrate the design of an example compact MOSCVR. The MOSCVR is capable of simultaneously producing four different output voltages from a single input power supply with only two flying capacitors and twelve switches. The study presented in this work provides not only comprehensive insight but also guidance to find the suitable topology of a compact MOSCVR. [ABSTRACT FROM AUTHOR]

In the memristive version of a standard space-invariant Cellular Nonlinear Network, each cell accommodates one first-order non-volatile memristor in parallel with a capacitor. In case, the resistance switching memory may only undergo almost-instantaneous switching transitions between two possible resistive states, acting at any time, as either the on or the off resistor, the processing elements effectively operate as first-order dynamical systems, and the classical Dynamic Route Map technique may be applied to investigate their operating principles. On the contrary, in case the memristors experience smooth conductance changes, as the bioinspired array implements memcomputing paradigms, each cell truly behaves as a second-order dynamical system. The recent extension of the Dynamic Route Map analysis tool to systems with two degrees of freedom constitutes a powerful technique to investigate the nonlinear dynamics of memristive cellular networks in these scenarios. This paper exploits this system-theoretic technique, called Second-Order Dynamic Route Map, to introduce a novel systematic procedure to design memristive arrays, in which a given memcomputing task is executed by ensuring that, depending upon the network inputs and initial conditions, the analogue dynamic routes of the states of the processing elements, namely capacitor voltages and memristor states, asymptotically converge toward pre-defined stable equilibria. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper presents an inductor-less switched capacitor based energy harvester, which can simultaneously harvest from 2 energy sources (Solar + Piezo). The proposed harvester employs maximum power point tracking algorithm, by changing the conversion ratios of the charge pumps for piezo and solar sources, and output voltage control by varying the switching frequency. The proposed MPPT algorithm can match the input impedance of two sources simultaneously. Implemented in 65nm CMOS, the proposed harvester can generate a fixed output between 1.8 and 2.5 V output while delivering 35 $\mu \text{W}$ to 70 $\mu \text{W}$ power with a peak power conversion efficiency of 74.6%. [ABSTRACT FROM AUTHOR]

This paper presents a turning-point output voltage (TPOV) prediction method to enhance the reference tracking speed of buck converters for dynamic voltage and frequency scaling (DVFS) application. The optimal reference tracking is modeled, and the TPOV is formulated. The parasitic effects are compensated with the proposed calibration scheme. Reference tracking considering load current changes is evaluated with the proposed end-point determination method. Additionally, this work optimizes the feedback network for smooth loop transition, and incorporates the frequency-locking circuit and the error correction path to address the shortcomings of the hysteretic control. The prototype is fabricated in a 0.13- $\mu \text{m}$ CMOS process with a 1.2-V supply voltage. The converter achieves a near-optimum reference tracking over a wide range of output voltages, from 0.5 to 1 V. Various output voltage steps are measured for different load cases. For a 0.5–1-V output voltage step, with a 90-nH inductor and a 1- $\mu \text{F}$ output capacitor, the up- and down-tracking take 558 and 542 ns, respectively, matching the theoretical result of 533 ns. The prototype achieves a peak efficiency of 93.5%, and over 85% efficiency is measured with $\mathrm {V}_{\mathrm {O}}$ from 0.5 to 1 V and $\mathrm {I}_{\mathrm {O}}$ from 130 to 550 mA. [ABSTRACT FROM AUTHOR]

Low-power circuits often employ dynamic voltage scaling and energy harvesting. Such circuits need a power management unit that can convert the voltage source to a wide range of target voltages with high efficiency. Targeting such a power management unit, this paper presents a reconfigurable architecture of switched capacitor (SC) voltage converter. It introduces a design optimization methodology that can determine trade-off among design parameters to meet the goal. The proposed converter employs a reconfigurable topology with four capacitors. It provides 11 conversion ratios: 6 step-down and 5 step-up ratios supporting wide input/output voltage range. An analytical model for the output impedance of the proposed reconfigurable SC topology is presented. Using the model, the proposed optimization methodology can minimize the total power dissipation. To validate the proposed architecture and optimization methodology, the converter has been implemented in a 130-nm CMOS process using integrated capacitors of total size 2.2 nF. Simulation results show that the optimized converter circuit achieves an efficiency range from 83.41% to 74.69% for a load current of $100~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications where usually differential structures are needed. In most cases, the resulting single-ended circuit will be much simpler than the fully or pseudo-differential one. It does not require common-mode feedback circuitry, nor single-ended-to-differential and differential-to-single-ended conversions at the input and output ports. The amplifiers may be single-ended, using, e.g., inverter-based circuits, and the use of baluns can be avoided. The number of pins and pads of the chip can be reduced. In addition, the single-ended opamps of the circuit may require less power than differential ones. These factors and the omission of the common-mode feedback circuits as well as the single-ended/differential converters will usually allow significant power savings. [ABSTRACT FROM AUTHOR]

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator’s loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC’s disadvantageous trade-off between the modulator’s jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM’s loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable. [ABSTRACT FROM AUTHOR]

This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper reports a calibration scheme that can be used to correct the inter-stage gain error in two-stage analog-to-digital converters (ADCs). We measure the static nonlinearity at the raw ADC outputs and compensate it through a feedback path to adjust the gain in the analog domain, which avoids the dynamic range loss in the conventional pure digital calibrations. The proposed scheme detects the error via the missing-code-occurrence probability (MCOP), which is insensitive to the comparator offset and has better immunity to its noise. Besides the gain error, we discuss other DAC linearity issues, such as the implementations of the reference buffer and the low-dropout (LDO) regulator. To verify the MCOP calibration, we design a 12-bit successive-approximation-register ADC, employing the bridge-DAC, in 65-nm CMOS. We integrate the ADC operating at 100 MS/s with the MCOP calibration, the reference buffers, and the LDO. The measurement results demonstrate the linearity enhancement after the proposed calibration, where we improve the signal-to-noise-and-distortion ratio to 61.38 dB, leading to a FoM of 16.7 fJ/conversion step at the Nyquist input frequency. [ABSTRACT FROM AUTHOR]

This paper presents an area- and power-efficient dual-output switched capacitor (DOSC) dc–dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10– $350~\mu \text{A}$ and 1– $10~\mu \text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm2. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta ($\Delta$) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also digital switching energy for the ADC reset. The $\Delta$ -readout process with the proposed MSB-rounding technique shifts the location of the resolvable range using the previous digital code to increase the hit-rate. Finally, the tri-level split monotonic switching scheme minimizes the CDAC switching activity in predictive residue generation for the $\Delta$ -readout process. A prototype ADC was fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies an active area of 0.17 mm2. At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW. [ABSTRACT FROM AUTHOR]

In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplifier followed by a class-B amplifier. The functionality of the class-B transconductance amplifier is dictated by a predefined hysteresis, and operates in parallel with the main amplifier. The proposed solution demands small static power (under 20% of main amplifier power) due to its class-B nature. The experimental results in a 40-nm CMOS technology show more than 45% reduction in slew time, and a 28% shorter slew time for 1% settling time when used in a typical 4.5 bit/stage block commonly used in pipelined analog-to-digital converters. Compared with the core amplifier, HD3 at 500 MHz reduces by more than 10 dB when the SR boosting circuit is activated. [ABSTRACT FROM AUTHOR]

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is shared among multi channels. The dual-sampling architecture for the output amplifiers also reduces the power consumption of the column driver IC, where the operating time of the time-shared DAC and the output amplifier is efficiently handled during the limited 1-horizontal time. The sampling accuracy of the dual-sampling architecture is improved by a simple dummy switch and a source follower. The proposed time-shared DAC with the dual sampling is implemented by a 0.13- $\mu \text{m}$ high-voltage complementary metal-oxide-semiconductor process and integrated in a 960-channel column driver IC, while the effective channel area of the column driver IC is 5520 $\mu \text{m}^{2}$. As a result of driving an 11-inch-wide quad extended graphics array AMOLED panel by using the prototype column driver IC, the panel uniformly generates a clear image. [ABSTRACT FROM AUTHOR]

This paper presents a systematic method to analyze $N$ -path mixers and filters consisting of periodically switched $RC$ -networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint network for simplified analysis of the harmonic transfer functions that describe the signal transfer and folding. Moreover, harmonic transfer cancellations due to the $N$ -path implementation with $N$ equal capacitors switched by $N$ non-overlapping clocks are systematically analyzed. The method is applied to a recently published $N$ -path filter-mixer combination and verified by simulations. [ABSTRACT FROM AUTHOR]

An integrated, power-saving SAR analog-to-digital converter suitable for image sensor applications is presented in this paper. In comparison with previous works, the proposed, build-in passive correlated double sampling (CDS) and programmable gain amplifying (PGA) technique is superior in power, as it achieves correlated noise cancellation and signal amplification without additional OTAs. Furthermore, inspite of a single-ended signal from the image sensor array, single-ended-to-differential sampling is used to enable symmetrical DAC switching. The adopted LSB-first algorithm, utilizing the strong correlation between neighboring pixels, significantly reduces the energy and number of bitcycles per conversion. Additionally, a comparator with four inputs is adopted to keep the DAC array unchanged, avoiding power consumption from the operation of the initial guess for next quantization. Fabricated using a 65-nm process, the 10-bit ADC occupies a die area of 0.19 mm2. The measured DNL and INL are less than +0.68/−0.45 LSB and +1.07/−1.15 LSB, respectively. Operating at 40 MS/s, the ADC provides an SNDR of 55.7 dB and SFDR of 70.9 dB for signal bandwidths of 17.2876 MHz and consumes $415.2~\mu \text{W}$ from a 1.2-V power supply, resulting in a figure of merit of 21.7 fJ/conversion-step. Additionally, the CDS and PGA functionality are verified to be effective in removing reset level influence and providing gains of −6 dB, 0 dB, and 6 dB. [ABSTRACT FROM AUTHOR]

This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches. [ABSTRACT FROM PUBLISHER]

Switch $R-C$ passive $N$ -path mixers and filters enable interference-robust radio receivers with a flexibly programmable center frequency defined by a digital multi-phase clock. The radio frequency (RF) range of these circuits is limited by parasitic shunt capacitances, which introduce signal loss and degrade noise figure. Moreover, the linear periodically time varying nature of switch $R-C$ circuits results in unwanted signal folding which needs to be suppressed by linear time- invariant (LTI) prefiltering by passive LC filters. This paper analyzes the interaction between capacitive or inductive LTI prefiltering and an $N$ -path mixer or filter, leveraging an analysis technique based on the impulse response of the adjoint network. Previously reported results for an inductive source impedance are derived in a simpler fashion, while providing circuit intuition. Moreover, new results for $N$ -path receivers with a shunt capacitor, and a combination of a series inductor and shunt capacitor are derived, as well as design criteria to minimize loss and frequency shifting in the peak response of these circuits. [ABSTRACT FROM PUBLISHER]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – \mu \textm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage. [ABSTRACT FROM PUBLISHER]

Recent innovations in software defined CMOS radio transceiver architectures heavily rely on high-linearity switched-RC sampler and passive-mixer circuits, driven by digitally programmable multiphase clocks. Although seemingly simple, the frequency domain analysis of these linear periodically time variant (LPTV) circuits is often deceptively complex. This paper uses the properties of sampled LPTV systems and the adjoint (inter-reciprocal) network to greatly simplify the analysis of the switched-RC circuit. We first derive the transfer function of the equivalent linear time-invariant filter relating the input to the voltage sampled on the capacitor in the switched-RC kernel. We show how a leakage resistor across the capacitor can be easily addressed using our technique. A signal-flow graph is then developed for the complete continuous-time voltage waveform across the capacitor, and simplified for various operating regions. We finally derive the noise properties of the kernel. The results we derive have largely been reported in prior works, but the use of the adjoint network simplifies the derivation, while also providing circuit insight. [ABSTRACT FROM PUBLISHER]

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- \mu \textm CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients. [ABSTRACT FROM PUBLISHER]

An efficient micro-scale solar power management architecture for self-powered Internet-of-Things node is presented in this paper. The proposed architecture avoids the linear regulator and presents a complete on-chip switched capacitor-based power converter in order to achieve higher end-to-end efficiency. Unlike traditional architectures, where the harvested energy processes twice, the proposed architecture processes the harvested energy only once before it reaches to the load circuit, irrespective of the ambient conditions. The system efficiency has been improved by ~12% over the traditional architecture. The entire power management system has been designed using 0.18- \mu \textm CMOS technology node, and the circuit simulations demonstrate that the proposed architectural changes bring in a system efficiency of 82.4% under different light conditions. In addition to that, a hardware setup is created using commercially available ICs and photovoltaic cells, to validate that the proposed power management system is practically realizable. [ABSTRACT FROM PUBLISHER]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, including on-chip reference buffers. [ABSTRACT FROM AUTHOR]

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at $100^{o}C$ across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses). [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements. [ABSTRACT FROM AUTHOR]