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This paper introduces an accurate frequency regulation method based on a constant on-time (COT) buck regulator designed for point-of-load (POL) regulation with a fast load transient requirement and wide load range. Traditional COT regulators suffer from frequency shift due to load variations. The proposed frequency adjustment circuit helps the COT control engine to reach its target frequency of operation by adjusting the on-time pulse under varying conditions. This circuit includes a phase detector and a voltage-to-current converter block. The phase error between the target clock signal and the PWM is directly used to adjust the width of the on-time pulse. This will fine-tune the bandwidth of the frequency regulation loop, which can help to improve the transient performance of the COT as well. The fabricated chip has been tested under 20A/ $\mu \text{s}$ load transient speed with a 10A load step condition. The measured silicon performance shows that the error of the switching frequency is less than 0.16% in the 400kHz to 1MHz range during steady-state operation. [ABSTRACT FROM AUTHOR]

In this paper, hybrid dynamical systems theory is applied to the analysis and control of switched converters with Pulse-Width Modulated (PWM) inputs. The system is described by a state-space model with continuous flows and discrete jumps, without averaged equations. The modulation effects are captured in full without using time-dependent signals, by enlarging the state vector to include the PWM waveform generation process. Furthermore, the sample-and-hold mechanism associated with the sampling frequency is also taken into account with this approach. A control law is proposed based on a Lyapunov function candidate. Furthermore, convergence sets and the steady state jitter, inherent to PWM-based controllers, are analyzed estimating limit sets for the augmented state. Consequently, output chattering can be bounded. By using hybrid dynamical system theory, the control designer gains a deeper understanding of the effect of modulation in the closed-loop dynamics, avoiding the problems associated with the use averaged models. Experimental results validate the proposed method. [ABSTRACT FROM AUTHOR]

A novel class-D flipped voltage follower (FVF) low-dropout (LDO) regulator is proposed and implemented in this paper to supply high load current with fast transient response for sharp load changes. The proposed class-D control generates a multi-level pulse width modulated (MLPWM) signal to the gate of the control transistor that corresponds to the load level. The MLPWM control signal enables wide loop bandwidth and reduces output ripple. The FVF architecture reduces the output impedance and improves the controller efficiency. A novel feed-forward transition-detection path (FFTDP) controls the gate of the power transistor and allows enhanced switching at high loads. The proposed LDO operates with a wide range of input voltages from 1.2V to 1.8V and dropout of 200mV down to 50mV. The implementation responds to load changes from 0-300mA in 7ns with no observed overshoot/undershoot. The output ripple for the LDO is < 7mV with roughly 2.5mV due to ESR resistance. The LDO achieves FOM $_{\mathbf {V}}=1$ mV with a current efficiency of 99.93% at maximum load current. The prototype chip is fabricated on 28-nm CMOS technology and the controller occupies 0.004mm2. [ABSTRACT FROM AUTHOR]

The growth of IoT applications requires DC-DC converters to have small printed circuit board (PCB) areas and high efficiency over a wide load range. A multi-mode operation of DC-DC converters, therefore, is often necessary to achieve this high efficiency over a wide load range. This paper introduces a tri-mode DC-DC buck converter for IoT applications. The tri-mode operation with PWM, PFM, and multiple-sawtooth PWM (MSPWM) modes helps to retain the high efficiency over the wide load range. The MSPWM mode also enhances a noise margin of the converter, ensuring a regular switching operation at an ultra-light load condition. With a load current prediction scheme, the proposed tri-mode converter requires neither additional load current sensor nor multiple mode controllers. In addition, a soft-start operation is employed to prevent an in-rush current. The proposed tri-mode buck converter has been fabricated through a 0.18- $\mu \text{m}$ CMOS process with a chip area of 0.97 mm $\times0.88$ mm. A load-dependent seamless mode transition is realized, and a maximum converter efficiency of 91% has been measured with a 7.4-MHz switching frequency. [ABSTRACT FROM AUTHOR]

The use of digital pulse-width modulators (DPWMs) as controllers for dc–dc converters is becoming more and more popular, due to the lower sensitivity to process variations, programmability, and easiness to translate complex control algorithm in digital architecture. DPWMs require high resolution to avoid limit cycling. Moreover, especially in high-frequency switching power converters, the reduction of the electromagnetic interference (EMI) is of primary importance. A novel DPWM circuit is proposed in this paper. The circuit uses only standard cells, easing portability to new technological nodes. The DPWM includes a coarse delay stage, based on an enhanced counter-based architecture, which is able to modulate both the frequency and duty cycle. As a result, the proposed DPWM supports spread-spectrum modulation, with arbitrary modulation law, to reduce the EMI. The DPWM also includes a fine delay stage that employs digitally controlled NAND-based delay lines with excellent linearity and resolution. A measurement unit is used to compensate at run time, the process, voltage, and temperature variations. The circuit has been fabricated in low-cost UMC 130-nm CMOS technology and is fit in a 44-pin package. The chip can generate spread-spectrum pulse-width waveforms up to 10 MHz. Measurement of the conducted EMI in buck dc–dc converter is reported in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. [ABSTRACT FROM AUTHOR]

This paper presents the Zero-Crossing-Time-Difference Model (ZCTDM) for a Voltage-Controlled-Oscillator based Operational Transconductance Amplifier (VCO-OTA). The small-signal, linear, discrete-time model provides output current impulses at equidistant time intervals, with their magnitude proportional to the time difference between the zero-crossings of the two VCOs in the VCO-OTA. Compared to the continuous-time phase-domain model (CT-PDM) and the impulse invariant transform model (IITM), ZCTDM accounts for both the high-frequency signal generated at the output near the VCO oscillation frequency and the high-frequency input response. ZCTDM thus captures the complete loop response for a VCO-OTA in a feedback configuration, as long as the output-voltage discharge rate is less than the system update rate, which is the case in most applications. The application of the model is demonstrated with two design examples. The frequency response of the system modeled with ZCTDM is within 0.5dBRMS of the response simulated with an extensive behavioral-model, whereas the results derived using CT-PDM and IITM deviate significantly both qualitatively and quantitatively. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper proposes an ultra-compact 4 to 10-Gb/s 5-tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the $1^{st}$ and $2^{nd}$ Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system’s step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 pspp at 10 Gb/s under a PRBS $2^{31}-1$ pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after −20-dB channel loss. The die area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort and enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40nm testchip, graceful degradation of 0.3 bit/100 mV is achieved when ${{\mathrm {V}}}_{\mathrm {DD}}$ is over-scaled down to 0.8 V, and 1.4 bit/100 mV when further scaled down to 0.6 V. The proposed DAC enables dynamic power-resolution tradeoff with three times (two times) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40 nm consumes $55~\mu \text{W}$ at 27 kS/s ($9.1~\mu \text{W}$ at 13.5 kS/s) at a compact area of $500~\mu \text{m}^{\mathrm {2}}$ and low voltage of 0.55 V. [ABSTRACT FROM AUTHOR]

In this paper, a new voltage-controlled oscillator (VCO)-based 1-1 MASH delta–sigma ADC structure is presented. The proposed architecture does not require any operational transconductance amplifier-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open-loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization error of the first stage as a pulse signal that is applied to the second stage. The input of the first VCO is a very small amplitude signal, and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for the power hungry linearization methods. The proposed idea was simulated at the transistor level, and the results verify the analysis. [ABSTRACT FROM AUTHOR]

This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manchester or pulse-width modulation encoding on high-speed wireline transceivers. A highly digital encoder architecture is leveraged to implement the proposed iPWM and CDC encoding. Energy-efficient operation of the proposed encoding is demonstrated on a high-speed wireline transceiver that can operate from 10 to 18 Gb/s. Fabricated in a 65-nm CMOS process, the transceiver operates with supply voltages of 0.9 V, 1 V, and 1.1 V. With the help of the proposed iPWM encoding, the transceiver can equalize over 27-dB of channel loss while operating at 16 Gb/s with an efficiency of 4.37 pJ/bit. The design occupies an active die area of 0.21 mm2. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital transmitter solution particularly suited for Massive multiple-input and multiple-output (MIMO) systems for mobile communications. Massive MIMO is a key candidate to address the challenges of future mobile communication standards, especially to provide higher capacity in dense urban scenarios. While the required communication theory is elaborated to a great extend, the transceiver hardware complexity remains a potential economical show-stopper. This paper demonstrates that all-digital transmitters can be employed to reduce size, cost, and engineering effort of heavily parallelized transmit architectures. Therefore, today’s all-digital transmitter concepts are analyzed and improvements are suggested to increase performance and feasibility. The realized setups prove that the key specifications of mobile communication standards can be met utilizing dedicated integrated circuits or even by using off-the-shelf FPGAs and their high-speed interfaces. We show that we can generate 8 parallel 5 MHz LTE signals at 2.6 GHz out of a single FPGA with an ACPR of 48 dB with a coding efficiency of 50% using only binary waveforms. [ABSTRACT FROM AUTHOR]

This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential delay-line. The resulting sampled digital word carries information of the threshold-crossings and the distances between them. The proposed 64-tapped adaptable-delay-line-based design is intended as a high-rate oversampling baseband binary quantizer for a high-speed serial link. The data-receiver has been demonstrated to digitize up to 25-Gb/s input binary symbol sequences with an oversampling ratio of eight. Designed in a 45-nm SOI CMOS process, the receiver circuit is fully characterized by applying different symbol sequences at its input while setting its time resolution and dynamic-range/delay to 5 and 320 ps, respectively. Under these conditions, the data-receiver consumes 270 mW of power, and achieves an energy conversion figure of 1.62–4.32 pJ/sampled-digital-bit. The circuit occupies 0.24 mm2 of active silicon area. The proposed receiver offers one of the highest time-resolution and oversampling factor, and among the best energy conversion figures compared with the oversampling time-mode receiver architectures reported so far. [ABSTRACT FROM AUTHOR]

This paper presents a 220-MHz pulse width modulation (PWM) fully integrated KY dc–dc step-up converter utilizing bondwire as power inductor, with discontinuous conduction mode (DCM) calibration control. We develop the first DCM closed-loop PWM controller for the KY converter, including: 1) its parameter design; 2) a DCM closed-loop voltage mode control with Type II compensator; 3) a zero current detection method to activate DCM control; and 4) a DCM calibration loop. Fabricated in 65-nm CMOS, the designed KY converter core occupies 0.93 mm2 and achieves an output conversion range of 1.5–2 V from a 1.2-V input. The measured peak efficiency is 75.2% at 97.5 mW. With a 500-ps rising/falling time of the load current step (56 mA), the undershoot/overshoot is 245/205 mV at 146-/140-ns recovery time, and the dc–dc converter achieves a settling time per load transient step of 2.6 ns/mA, which is competitive with the state-of-the-art boost converters. [ABSTRACT FROM AUTHOR]

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

An ultrasound transmitter based on a high-voltage digital-to-analog converter (HVDAC) is presented in this paper. The transmitter is implemented in a 0.25- $\mu \text{m}$ high-voltage CMOS process provided by foundry, integrating the digital control circuitry and HVDAC on a single chip. By employing a fast-slewing DAC in conjunction with a standard DAC, the proposed circuit is optimized for high-speed operations even for a load with large capacitance, making it well suited for applications where piezoelectric transducers are utilized. With an output loading of 180 pF // $50~\Omega $ , the HVDAC operates at a sampling rate of 150 MS/s, while providing a maximum output swing of 31.5 $\text{V}_{\mathrm {PP}}$. The spurious-free dynamic range is 46 dB at 1-MHz output frequency and 31 dB at Nyquist frequency, which is analyzed in detailed and proved in good agreement with the measurement results. Tested with a chirp signal sweeping from 15.75 to 34.25 MHz in 2- $\mu \text{s}$ and a transducer model centered at 25 MHz with a 13.75-MHz bandwidth, the compressed pulse after matched filtering shows a −6-dB pulse width of 153 ns with a peak sidelobe of −40 dB, which successfully demonstrates the capability for coded signals excitation at high frequency. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio. [ABSTRACT FROM PUBLISHER]

In this paper, the limitations of digital-to-analog (D/A) conversion by Digital Pulse Width Modulation (DPWM) are addressed and the novel Dyadic Digital Pulse Modulation (DDPM) technique for all-digital, low cost, high resolution, Nyquist-rate D/A conversion is proposed. Thanks to the spectral characteristics of the new modulation, in particular, the requirements of the filter needed to extract the baseband component of DPWM signals can be significantly released so that to be suitable to inexpensive integration on silicon in analog interfaces for nanoscale integrated systems. After the new DDPM technique and its properties are introduced on a theoretical basis, the implementation of a D/A converter (DAC) based on the proposed modulation is addressed and its performance in terms of noise and linearity is discussed. A 16-bit DDPM-DAC prototype is finally synthesized on a field-programmable gate array (FPGA) and experimentally characterized. [ABSTRACT FROM AUTHOR]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

A model-based strategy for an efficient power supply control used in a wireless sensor network is presented. The strategy, based on Pulse-Skipping Modulation, regulates the current charging a battery, delivered by a photovoltaic source, resulting in an accurate current regulation and highly efficient power management. The strategy is implemented on a microcontroller unit and compensates for the microcontroller self-absorbed current. The modulation signal is generated through a full software interface, reducing the requirement for external components. Experimental validations, performed on a charger prototype by using a laboratory photovoltaic device simulator, proved that both regulation accuracy, regulation resolution and converter efficiency achieved are superior to the classic Pulse-Width Modulation. The approach results in a simple practical implementation, carries over the advantages of an up-to-date model for the photovoltaic device, and serves the auxiliary purpose of using the photovoltaic source as an instantaneous solar irradiance sensor. [ABSTRACT FROM AUTHOR]

The charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory. [ABSTRACT FROM PUBLISHER]

The type-II optimal normal basis (ONB) is popularly used to represent GF(2^m) for elliptic curve cryptosystems. It is shown in the literature that multiplication in binary fields, including those represented by type-II ONB, shifted polynomial basis, and dual basis, can be transformed into non-symmetric Toeplitz matrix-vector product (TMVP) formulation. In this paper, we show that type-II ONB multiplication can be realized by two symmetric TMVPs (STMVP). Moreover, we have proposed a novel folded TMVP block recombination (TMVPBR) for the computation of STMVP. Based on the proposed folded TMVPBR approach, we have proposed a new digit-serial structure for type-II ONB multiplication, while traditional parallel ONB multipliers are based on non-symmetric TMVPBR approach to achieve subquadratic space complexity architecture. The proposed digit-serial structure also involves subquadratic space complexity. By the theoretical analysis as well as from synthesis result, however, we find that the proposed architecture has significantly less area and less area-delay product compared to the existing digit-serial type-II ONB multipliers. [ABSTRACT FROM AUTHOR]

In this work we model from a system design perspective the realization of a novel mixed-signal approach to pulse width modulation (PWM). The working principle for the approach, along with an implementation scheme comprised of a digital zero-positioning (ZP) followed by a proper digital-to-analog converter (DAC) and comparator, has been introduced in a companion paper. We here focus on analyzing the global system in order to get a model of its performances in terms of dynamic range and non-linearity. Since non-linearities and quantization noise occur between the ZP and the comparator, firstly, upstream models for them are provided; then their effect on the PWM signal is calculated by means of a downstream model of perturbations at the input of an ideal natural sampling PWM. Finally, an exhaustive formula for the resulting dynamic range is given and some configurations of practical interest are proposed. [ABSTRACT FROM AUTHOR]

The trend in transmitter systems is to move the digital domain closer towards the antenna using digital modulators and drivers to reduce circuit complexity and to save power. A common assumption made is that they are capable of generating ideal pulses and thus do not suffer from analog imperfections. But the output signals of real drivers for high frequency operation are not perfectly rectangular anymore, which leads to distortion lowering the signal quality. In this paper the general properties of high frequency digital driver circuits operating at 2.6 GHz are analyzed and the impact of the different effects is presented. The predistortion of such drivers in the context of digital discrete time RF PWM modulators is studied. It has been found that conventional sample based predistortion can only correct the driver nonlinearity from -29 dBc to -49 dBc for the example considered using a 40 MHz bandwidth signal at 2.6 GHz. Therefore a special predistortion scheme considering the impact of pulses adjacent to the other samples is proposed. The mitigation of effects due to the discrete time nature of the signal is considered and discussed in detail. The capabilities of the proposed predistortion scheme are verified by extensive simulations as well as by measurements. By applying the proposed predistortion concept the spectral quality can be further improved to -66 dBc. In addition different scenarios with limited resolution and a carrier frequency offset are analyzed. [ABSTRACT FROM AUTHOR]

An admittance or impedance matrix of a power converter is highly desirable for harmonic analysis of a power system. However, power converters are inherently nonlinear and time-varying systems. Therefore, a small-signal harmonic model needs to be derived. While there have been many methods to obtain the small-signal models of DC-DC converters, most of these methods cannot be directly applied to AC-DC converters. Moreover, while accurate methods exist for obtaining accurate models of open-loop AC-DC converters, there are few existing methods for obtaining accurate models for closed-loop AC-DC converters. This paper proposes an analytical method for obtaining an accurate small-signal harmonic model for a power converter. The proposed method is based on state-variable sensitivity methods, which have been previously used to derive a transfer function of a DC-DC converter. This paper will show what modifications are required to extend it to derive the small-signal harmonic model of a closed-loop AC-DC converter. A small-signal harmonic model of a closed-loop pulse-width modulated (PWM) voltage source converter (VSC) with synchronous frame current controllers and a dc voltage controller is derived based on the proposed method. The results are in good agreement with large-signal simulations by means of PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

This paper proves a novel sampling theorem with constant amplitude and variable width pulses. The theorem states that any bandlimited baseband signal within \pm0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is two-level or three-level. The proof of the sampling theorem uses a simple iterative technique that is guaranteed to converge to the exact PWM representation whenever it exists. The paper goes on to develop a practical matrix based iterative technique to generate the PWM waveform that is guaranteed to converge exponentially. The peak constraint in the theorem is only a sufficient condition. In fact, many signals with higher peaks, e.g., lower than Nyquist frequency sinusoids, can be accurately represented by a PWM waveform. [ABSTRACT FROM PUBLISHER]

Karatsuba algorithm (KA) is popularly used for high-precision multiplication by divide-and-conquer approach. Recently, subquadratic digit-serial multiplier based on (a,2)-way KA decomposition is proposed in [1]. In this paper, we extend a (a,2)-way KA to derive a generalized (a,b)-way KA decomposition with a\neq b. We have shown that (a,2)-way KA and mult-way KA are special cases of the proposed (a,b)-way KA decomposition. Based on the proposed KA decomposition, we have established two types of subquadratic digit-serial multipliers, namely, the KA-based multiplier and the recombined KA-based multiplier. From theoretical analysis, as well as, from synthesis results we have shown that the proposed KA-based multipliers have significantly less delay and less area-delay product (ADP) compared to the existing naive digit-serial multipliers. [ABSTRACT FROM AUTHOR]

Subquadratic multiplication algorithm has received significant attention of cryptographic hardware researchers for efficient implementation public-key cryptosystems. In this paper, we derive a new shifted MPB (SMPB) representation based on modified polynomial basis (MPB). We have shown that by using MPB and SMPB, the proposed double basis multiplication can be transformed into Toeplitz matrix-vector product (TMVP) structure. Furthermore, by employing this formulation of double basis multiplication, we show that three-operand multiplication over GF(2^m) for all trinomials can be realized efficiently by the recursive TMVP (RTMVP) formulation. To perform the three-operand multiplication with the RTMVP formulation, we have derived a new RTMVP decomposition scheme. The proposed single- and double-multiplications can, respectively, use TMVP and RTMVP decompositions to achieve subquadratic space complexity architectures. By theoretical analysis, it is shown that the proposed subquadratic multipliers involve significantly less space complexity and less computation time compared to the existing subquadratic multipliers using TMVP and Karatsuba algorithms. Moreover, our proposed double-multiplication design can be used in several applications involving successive multiplications, such as exponentiation, inversion, and elliptic curve point multiplication. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-time third-order \Sigma\Delta modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed \Sigma\Delta modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-to-noise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V \Sigma\Delta modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering. [ABSTRACT FROM AUTHOR]

Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two variations of polynomial basis representation. SPB/GPB have potential for efficient bit-level and digit-level implementations of multiplication over binary extension fields. This paper presents a (b,2)-way KA decomposition for digit-serial multiplication with low-space complexity. Based on the proposed parallel (b,2)-way KA scheme, we derive a novel scalable SPB/GPB multiplier. Analytical results show that the proposed multiplier could achieve the desired trade-off between space and time complexities. Our proposed multiplier is modular, regular, and suitable for very-large-scale integration (VLSI) implementations. It involves significantly less area complexity, less computation time and less energy consumption compared to the existing digit-serial and scalable multipliers. [ABSTRACT FROM PUBLISHER]

The trend in transmitter systems is to move the digital domain closer toward the antenna using digital modulators and drivers to reduce circuit complexity and to save power. One promising approach is the use of RF pulse width modulation (RF PWM). Unfortunately purely digital discrete time RF PWM suffers from aliasing problems which limit the achievable resolution. For a 40 MHz bandwidth signal at 2.6 GHz carrier frequency for example the achievable signal quality is limited to \sim43 dBc. This paper describes the root cause of this effect, an error in the determination of the cross points, due to the sampled nature of the signal and proposes a method to compensate for it. It is shown that by interpolating the signal and estimating the cross points the signal quality can be significantly improved. The interpolation is simplified by interpolating the decomposed outphasing signals instead of the full signal. This has the advantage that a constant instead of a phase modulated reference function can be used. It is shown that by simple cross point estimation the signal quality can already be improved to 65 dBc. When either considering a second modulator or when using a delta sigma like noise shaping architecture the signal quality can be further enhanced to 75 dBc. [ABSTRACT FROM PUBLISHER]

A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation to overcome frequency-dependent losses in electrical interconnects. Time domain modulation is discussed as a means to enhance the spectral efficiency in channels with sharp frequency roll-off similar to multilevel voltage-domain modulation such as 4-PAM. The transmitter and receiver are high-speed programmable digital-to-time and time-to-digital converters that adapt to channel bandwidth characteristics with a timing resolution of 40 ps. This paper presents a low-jitter, phase rotation architecture for cycle-to-cycle transmit pulsewidth control. The transceiver includes an elastic buffer to move data between synchronous and plesiochronous clock domains and is implemented in 45-nm CMOS SOI. Transmitter and receiver functionality is demonstrated to 10 Gb/s at a BER of under 10^-12 and is compared against NRZ schemes at the same rate. The inductor-less transmitter and receiver active circuitry respectively occupy an area of 93\,\times\,94 and 218\,\times\,160 \mum^2, and consume a total 107 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

This paper presents a frequency-domain analysis of the noise and distortion terms produced by a digital RF modulator that uses pulse width modulation (PWM) for the amplitude modulation and a square wave as RF carrier. Insight in these terms is important as they limit the error vector magnitude (EVM) the modulator can achieve. For each of the terms, frequency-domain expressions are derived which are valid as long as the quantization noise is small and the digital PWM is sufficiently close to natural-sampling PWM. The dependency of the terms on the different system parameters is estimated, and the calculations are supported and complemented with simulation results. The presented analysis improves the understanding of the dominant noise and distortion sources, which can significantly speed up the design of PWM-based transmitters. [ABSTRACT FROM AUTHOR]

A discrete-time pulse width modulator (PWM) with zero baseband distortion for arbitrary band-limited modulating signals is developed in this paper. It is based on adjusting the duty-cycles of the PWM such that the samples of an ideal low-pass filtered version of the PWM signal coincide with the discrete-time samples of the modulating signal. Elaborating on previous approaches in the literature, it is shown that this problem can be stated as a multidimensional inverse function approach, and therefore it can be solved using iterative methods. Starting with the duty-cycle values of a uniform PWM, the successive iterations provide slight duty-cycle corrections that, in the limit, result in zero baseband distortion even for low carrier-to-modulating frequency ratios. Aiming at a practical, real-time implementation two new results are provided. First, explicit bounds on the improvement achievable after each duty-cycle correction are derived. Second, a block processing architecture suitable for real-time implementation is proposed, and the increase of distortion caused by its use is quantified. Several examples with typical band-limited signals demonstrate the performance of the algorithm. [ABSTRACT FROM PUBLISHER]

A novel digital self-oscillating pulse width modulation (PWM) signal generator with a hysteresis comparator is proposed in this study. The proposed generator, referred to as a “2nd-order PWM signal generator” in this paper, utilizes a double integration loop based upon the concept of delta-sigma modulation for precise conversion. A simple 2nd-order PWM signal generator was initially investigated, but it was found to exhibit impractical behavior: the period of the PWM output signal increased slowly with time. An analysis of the limit cycle state of this simple generator using describing function theory shows that the amplitude of the limit cycle is extremely large. Proportional integral (PI) compensation is therefore used to adjust the limit cycle state by varying the proportional gain and the coefficient of the integral. The use of PI compensation suppresses the amplitude of the limit cycle, thus making the 2nd-order PWM signal generator practical. An analysis of this modified generator reveals that the period of the PWM signal can be controlled by the hysteresis width of the comparator and by the proportional gain. As a test case, a switching frequency of 300 kHz is used for the performance evaluation of the proposed PWM signal generator with a sampling frequency of 12.5 MHz. A noise-shaped output is obtained, and a high-precision, ultra-low-distortion PWM signal with a high effective duty cycle resolution is achieved. [ABSTRACT FROM PUBLISHER]

The utilization of a burst-mode power amplifier (PA) together with pulse-width modulation (PWM) is a promising concept for achieving high efficiency in radio frequency (RF) transmitters. Nevertheless, such a transmitter architecture requires bandpass filtering to suppress side-band spectral components to retrieve the wanted signal, which reduces the transmit power and the transmitter efficiency. High efficiency can only be expected with the maximum transmit power and signals with low peak-to-average-power ratios (PAPRs). To boost efficiency for signals with high PAPRs and signals at variable transmit power levels, the burst-mode multilevel transmitter architecture has been widely discussed as a potential solution. This paper presents an efficiency optimization procedure of burst-mode multilevel transmitters for signals with high PAPRs and signals at variable transmit power levels. The impact of the threshold value on the transmitter efficiency is studied, where the optimum threshold value and the maximum transmitter efficiency can be obtained according to input magnitude statistics. In addition, the relation between the threshold value and the efficiency expression of burst-mode multilevel transmitters and those of Doherty PAs is investigated. It is shown that the obtained optimum threshold value, although originally designed for burst-mode transmitters, can also be applied to Doherty and multistage Doherty PAs to achieve maximum transmitter efficiency. Simulations are used to validate the efficiency improvement of the optimized burst-mode multilevel transmitters compared to two-level and non-optimized multilevel transmitters. [ABSTRACT FROM PUBLISHER]

Active pulse-width-modulated (PWM) voltage rectifiers are commonly used to convert ac power from a three-phase grid to a regulated dc voltage with unity input power factor. The output voltage regulation is normally achieved by an outer voltage feedback loop and a sinusoidal pulse-width-modulated (SPWM) inner current loop. Due to output voltage disturbances, such as those produced by a capacitive load, the inner current loop can be easily driven into over-modulation and possible six-step operating regions. Current research efforts have focused on extending the linearity of the modulated voltage in the over-modulation range to reduce the input current harmonics and on studying the closed-loop stability via conventional small-signal linearization around a fixed operating point. Such linear techniques obviously fall short of predicting large-signal transient stability. In this paper, catastrophic bifurcation of the three-phase voltage-source converter is reported. The physical origin of the phenomenon is identified. Boundaries of catastrophic bifurcation in the parameter space are derived. The phenomenon has been verified experimentally. [ABSTRACT FROM PUBLISHER]

This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs. [ABSTRACT FROM PUBLISHER]

This paper introduces a dual-mode digital dc-dc converter combining the predictive and feedforward control with the conventional PID controller to achieve fast transient response and low overshoot. An additional predictive or jerk component is added to the conventional PID controller to speed up the transient response and reduce the settling time by approximately 50%. This predictive term is based on the second derivative of the error signal and introduces zero to the loop response which leads to increased bandwidth and improved phase margin. In addition, a feedforward control is also employed to further improve the transient by evaluating the change in the inductor current during the on and off time of the power transistors. Theoretical analysis and simulations were carried out to analyze the proposed design and algorithm. The proposed design is verified on silicon with a prototype of a digital dc-dc converter fabricated in CMOS 0.18 μ m process. The digital dc-dc converter achieved a settling time of 4 μs and an overshoot of 15 mV for a step-load transient of 450 mA, which are improved significantly as compared to the prior arts. [ABSTRACT FROM PUBLISHER]

While a host of analysis techniques exist to perform steady-state analysis of open-loop converter systems, solutions for close-loop converter systems are distinctly more challenging to obtain. Analysis is done either via computationally intensive time-domain simulation or through reliance on a disconnected collection of published iteration techniques. Moreover, most of these iteration techniques deal with a system containing only one or two converters. This is not adequate to deal with a smart grid or microgrid system, which consists of multiple (more than two) converters. This paper proposes a generalized and systematic solution procedure to obtain the steady state of a system containing multiple closed-loop power converters, in a computationally efficient manner. The solution procedure consists of a general five step approach that can easily be applied to a wide variety of power converter systems. It is shown that numerous previously proposed methods may be viewed as specific implementations of the generalized systematic procedure. A new solution approach, suitable for analysis of tightly coupled multiconverter networks, is developed based on the generalized solution procedure. Results of the new approach are validated against PSCAD/EMTDC simulations for a representative multiconverter network. [ABSTRACT FROM PUBLISHER]

This paper presents an efficient CMOS dc-dc converter with fast transient recovery. A fast-transient control operating in conjunction with a linearly scaled gate-driving technique is used to concurrently improve the transient response and light-load efficiency of a dc-dc converter. The controller operates under a pulse-width modulation mode during steady state and enables a saturation mode during transient to attain fast transient response. The linearly scaled gate-driving technique optimizes the gate-driving voltage with respect to the changing load leading to lower gate-driving loss and better light-load efficiency. A prototype chip was implemented using a commercial 0.35-μm CMOS process to validate the proposed techniques. The measurement result shows a 5% increase in light-load efficiency and achieves an overall maximum efficiency of 90%. Moreover, the transient recovery time of a 450 mA step load change is less than 9 μs. [ABSTRACT FROM PUBLISHER]

This paper presents a transmitter architecture based on a pulse-modulated polar transmitter using multiphase pulsewidth modulation. The modulation to the radio-frequency input signal, instead of conventional drain modulation, significantly reduces the circuit complexity, while the multiphase modulation technique reduces the out-of-band emissions. An 836.5-MHz four-phase prototype transmitter using four class-C power amplifiers in parallel was constructed. Using the transmitter, single-phase, two-phase, and four-phase pulsewidth modulated signals were tested to verify the benefits of using the proposed multiphase architecture. Using a CDMA2000 1X signal, 46.8% efficiency at a 29-dBm output power level was measured while passing the spectral-mask requirements without using any kind of digital predistortion or calibration. [ABSTRACT FROM PUBLISHER]

A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate fs, are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate fs and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio Fs/fmax, the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the ioop filter produce, in the modulator output, a limit cycle of frequency fmax which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to fmax and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator. [ABSTRACT FROM AUTHOR]

Nonlinear phenomena in power electronic circuits are generally studied through discrete-time maps. However, there exist very few circuit configurations (like, for example, the current-mode-controlled dc-dc converters or current programmed H-bridge inverter) for which the map can be obtained in closed form. In this paper, we show that, in a voltage-mode-controlled dc-dc converter, if the switching is governed by pulse-width modulation of the first kind (PWM-1), an explicit form of the stroboscopic map can be obtained. The resulting discrete-time state space is piecewise smooth, divided into five regions, each with a different functional form. We then analyze the bifurcation behavior using the explicit map and demonstrate the different types of border collision bifurcations that may occur in this system as a fixed point moves from one region to another. This includes the very interesting case of a direct transition from periodicity to quasi-periodicity through the route of border collision bifurcation. Mode-locking periodic windows are also obtained at certain ranges of the parameters. The two-parameter bifurcation diagram is presented, showing the domains of existence of different oscillatory modes in the system parameter plane. [ABSTRACT FROM AUTHOR]

This paper presents a simple unified approach to the design of fixed-frequency pulsewidth-modulation-based sliding-mode controllers for dc-dc converters operating in the continuous conduction mode. The design methodology is illustrated on the three primary dc-dc converters: buck, boost, and buck-boost converters. To illustrate the feasibility of the scheme, an experimental prototype of the derived boost controller/converter system is developed. Several tests are performed to validate the functionailties of the system. [ABSTRACT FROM AUTHOR]

An ultra-low quiescent current dual-mode buck converter system is designed for IoT application, which includes a double clock time (DCT) and a pulse-width-modulation (PWM) control modes. The proposed DCT mode can reduce the conversion loss over a wide loading range from nA-to-mA and achieve seamless mode transition from DCT to PWM control. Implemented in a $0.18\mu \text{m}$ CMOS, this converter achieves a peak efficiency of 92.7%/94.7% in DCT/PWM and >80% efficiency from $10~\mu $ A to 50 mA (5000x), with a wide input voltage from 2 V to 5 V. A quiescent current of 470 nA including bandgap voltage reference and internal oscillator is achieved. The DCT-to-PWM mode selection mechanism achieves an undershoot of 80 mV at $11~\mu \text{s}$ recovery time when load current jumps from $6.67~\mu \text{A}$ to 50 mA. [ABSTRACT FROM AUTHOR]

We combine 2-tap feed-forward amplitude equalization with phase equalization by 4-tap integrated pulse-width modulation. In a $\text{V}_{\mathbf {SS}}$ -terminated transmitter, amplitude equalization is selected for pull-up data transmission, and phase equalization for pull-down data transmission, and the strength of equalization can be controlled depending on channel losses. This combines the strength of amplitude equalization with the energy efficiency of phase equalization. A prototype quarter-rate transmitter for memory interfaces, fabricated in a 65nm CMOS process, performed single-ended signaling at a data-rate of 16Gb/s/pin over a channel with a loss of 14.7dB. Its energy efficiency is 1.04pJ/bit/pin and the figure-of-merit is 0.070pJ/bit/pin/dB. [ABSTRACT FROM AUTHOR]