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In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

In a capacitive wireless power transfer system, due to the pF-level coupling capacitance, resonant inductors are commonly used at the primary side to boost voltage and at secondary side to boost the current. However, the inductors are bulky, in particular when it comes to integration, thereby not preferred by some space-sensitive applications like smartphones, smart glasses and headphones. This paper proposes a capacitive wireless power transfer architecture with no inductors at the receiver side. A high conversion ratio step down switched capacitor converter (SCC-CPT), rather than inductors, is used to compensate for the impedance mismatch between the secondary side of the capacitive coupler and the load. The analysis method and its associated design procedure of the SCC-CPT system is developed with the target of clarifying the tradeoffs among the secondary side efficiency, coupler voltage stress, receiver side integrability, and the primary side compensation network gain. Finally, a 7.5 W, 12 MHz SCC-CPT prototype was constructed to validate the proposed analysis and design. The measured system efficiency is 75.6 % at 7.5 W output, and the secondary side switched capacitor converter efficiency is 96.4 %. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

The recently-proposed dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is a promising approach for enabling the implementation of multiple fully-integrated power supplies with superior dynamic and cross-regulation performance in SoCs. However, switching the input and output stages at different frequencies raises many questions about the optimum strategy for controlling such converter topology. This paper explores and analyzes the various classes of controllers that can be employed in the output stage of the DF-SIMO buck converter topology, while taking account of key comparison metrics, such as circuit complexity, stability, steady-state and dynamic performance, and the range of operating conditions each controller may be suitable for. This includes average-based voltage-mode, ripple-based charge-mode, and ripple-based voltage-mode controllers. The predictions made by the analytical expressions derived for the various controllers are verified through system-level and transistor-level circuit simulations. [ABSTRACT FROM AUTHOR]

In this paper, two output matching networks (OMNs) are proposed for integrated class-J and class-J−1 mode power amplifiers (PAs). The first MN provides the required load impedances of the class-J mode (i.e., $Z(f_{0})=R_{\mathrm{ opt}}+jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=-j({3}\pi /{8})R_{\mathrm{ opt}}$), whereas the second MN realizes the optimal impedances of class-J−1 PAs (i.e., $Z(f_{0})=R_{\mathrm{ opt}}-jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=j({3}\pi /{8})R_{\mathrm{ opt}}$). Detailed theoretical analyses are presented for each MN, and the values of matching components (i.e., inductors and capacitors) are obtained in terms of $R_{\mathrm{ opt}}$. Analytical derivations are verified by simulation results, while bandwidth and loss performances of each MN are also characterized. Two proof-of-concept class-J and class-J−1 PAs are designed and implemented in a 0.25- $\mu \text{m}$ GaAs process, where the proposed OMNs are employed in the designed circuits. The manufactured PAs show ≥28 dBm output power, ≥65% drain efficiency, and ≥61% power-added efficiency at 2 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes a family of integrated multiple output isolated dc–dc converters, in which switches are hybrid utilized. Compared with the conventional separate $N$ -output isolated converter, which employs $2N$ primary switches, only $N$ +1 switches are required in the primary side of proposed converters to independently regulate $N$ secondary output voltages. Therefore, the number of switches is greatly reduced, contributing to lower cost. In this paper, detailed topology derivation is first introduced. A diversity of integrated multiple output topologies is derived with different cell connections and different cell configurations, including the asymmetrical flyback, forward as well as a half-bridge. Their performance characteristics are different and thus they are suitable for different applications. Then, in order to obtain a comprehensive insight of the proposed converters, a simplified dual-output asymmetrical flyback converter with three primary switches is taken as an example to be introduced in detail. Each output voltage in the converter is regulated with individual duty cycle, and zero-voltage-switching operation is achieved for all switches over the whole load range. Finally, experimental results based on a prototype circuit with two 12-V/3-A and 5-V/4.8-A outputs are also provided to validate converter effectiveness. [ABSTRACT FROM PUBLISHER]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

Fifth-order T-type resonant converter (RC) topologies for constant current applications are introduced in this paper. Immittance property in passive resonant tanks (PRTs) of the RCs is the key feature for realizing this purpose. In comparison with the lower order PRTs, the fifth-order topologies have more inherent current robustness against load variation, less sensitivity to the parameters variation and current gain tuning ability. At first, resonant networks qualifying the PRT conditions are specified with their topological superiorities description. Without loss of generality, 28 immittance PRTs (IPRTs) are detected as possible candidates that can be used as a voltage source to current source converter. In addition, their immittance operating conditions are analyzed mathematically. For prototyping, a topology has been selected and designed using a method based on minimization of the IPRT elements size. Moreover, closed-form expressions of the output current and voltage/current stresses on the reactive elements are derived and verified for selecting the elements value. The designed prototype is a 150-W constant current RC with tight load regulation ability. Experimental results show that the ZVS operation with low reactive power on the switches as well as minimum losses on the rectifier diodes are achieved in a wide range of load variations. [ABSTRACT FROM PUBLISHER]

A pair of universal current mode control schemes for charging a Li-ion battery for mobile applications are discussed in this paper. The peak-current mode control schemes, based on a single control loop, is universal because it is designed with a single-stage buck charger for both a conventional wall adapter dc source as well as a solar photovoltaic (PV) module of comparable specifications. The charging schemes remove the need for an extra MPPT (maximum power point tracking) power converter stage. This control scheme is non-linear and incorporates all possible scenarios: mode of operation of a battery, current charging rate and power characteristic of input source. The algorithm uses need-based MPPT and ensures minimal battery discharge, and also uses minimum number of sense variables in the circuit. The methods differ in the way MPPT is implemented: perturb and observe (P&O) and fractional open circuit voltage. Simulation results demonstrating battery charge profile, validity of the algorithm under varying insolation conditions and platform workloads are presented, along with a discussion of the trade-offs of the two methods. Proof-of-concept hardware results are also provided. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dual-core LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07–4.91 GHz, while drawing 39–59 mA from a 2.15 V power supply. The measured PN is $-$146.7 dBc/Hz and $-$163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area. [ABSTRACT FROM AUTHOR]

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3F and transmission-line (TL) Class-E3F2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E3F PA are described. The load networks of the Class-E3F and TL Class-E3F2 amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. [ABSTRACT FROM PUBLISHER]

This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed inductor, duty-cycle, switch resistances and the class-E conditions at certain outphasing angle. Three different topologies are deduced from the proposed generalized model. The design equations for the circuit elements are derived analytically using the given class-E conditions. The overall outphasing performance is obtained numerically, and the optimum design settings are determined by the desired output power and efficiency characteristics. It will be shown that the proposed class-E OPAs can ideally maintain high efficiency (>80%) at 12-dB power back-off with a static square-wave drive signal. With 5-MHz UMTS downlink signal, the ideal average efficiency is more than 80%. The spectral and modulation requirements are satisfied when the predistortion is applied to the class-E OPA. [ABSTRACT FROM AUTHOR]

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm2 and 0.11mm2, respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power. [ABSTRACT FROM AUTHOR]

This paper analyzes a new family of dc-dc converters; labeled H-bridge based double-input dc-dc converters. First, it derives four converter topologies by cascading two H-bridge cells and interfacing the cascaded cells to different configurations of inductor, capacitor, and load. Next, it develops a small-signal model of the four converters and combines them into a canonical small-signal model. Finally, it analyzes the power sharing capability of the converters. It also presents simulation and experimental results to verify the theoretical outcomes. [ABSTRACT FROM PUBLISHER]

Quadratic converters have the voltage conversion ratios of two cascaded converters, but with fewer switches. They are not widely used, however, because they are generally less efficient than other converter types, but they can be useful for certain applications. In this paper, the characteristics of quadratic converters are explained, several examples of where they can be used in industrial applications are given, and a new three-phase converter that has been derived from quadratic conversion principles is presented. The feasibility of the new converter is confirmed with results obtained from an experimental prototype. [ABSTRACT FROM AUTHOR]

A millimeter-wave current-reuse voltage-controlled oscillator (VCO) features a single-turn multi-tap inductor and two separate differential-only switched-capacitor arrays to improve the power efficiency and phase noise (PN). Specifically, a single-branch complementary VCO topology, in conjunction with a multi-resonant Resistor-Inductor-Capacitor-Mutual inductance (RLCM) tank, allows sharing the bias current and reshaping the impulse-sensitivity-function. The latter is based on an area- efficient RLCM tank to concurrently generate two high quality- factor differential-mode resonances at the fundamental and 2nd- harmonic oscillation frequencies. Fabricated in 65-nm CMOS technology, our VCO at 27.7 GHz shows a PN of −109.91-dBc/Hz at 1-MHz offset (after on-chip divider-by-2), while consuming just 3.3 mW at a 1.1-V supply. It corresponds to a Figure-of-Merit (FOM) of 187.6 dBc/Hz. The frequency tuning range is 15.3% (25.2 to 29.4 GHz) and the core area is 0.116 mm2. [ABSTRACT FROM AUTHOR]

Optimal voltage-controlled oscillator (VCO) design for ultralow-power (ULP) radios has to fulfill simultaneously multiple requirements such as frequency tuning range, phase noise, power consumption, and frequency pushing. The manual design struggles to approach the full potential that a given topology can achieve. In this work, we prove the role of electronic design automation (EDA) tools by fully supporting the complex design of a ULP complementary Class-B/C hybrid-mode VCO. In the 1st step of the EDA-assisted flow, we perform a worst-case corner of worst-case tuning sizing optimization over a 108-dimensional performance space, offering sizing solutions with power consumption down to $145~\mu \text{W}$ at the worst-case. In the 2nd step, we introduce an automatic layout generation tool to offer valuable insights into the post-layout design space and devise a ready-for-tape-out fine optimization strategy. The hybrid-mode VCO prototyped in 65-nm CMOS occupies a die area of 0.165 mm2 and dissipates $297~\mu \text{W}$ from a 0.8 V supply at 5.1 GHz. The phase noise at 1 MHz offset is −110.1 dBc/Hz, resulting in a competitive Figure-of-Merit (FoM) of 189.4 dBc/Hz well-suited for ULP applications. [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

The efficiency of power amplifiers (PAs) with a small output power (POUT) for short-range wireless sensor networks is limited by the loss in matching networks. To achieve high efficiency, a new design method which calculates the complicated design parameters in a class-F PA with a merged filter and matching networks is proposed. The design method provides a new quantitative conclusion that reducing both the power supply voltage (VDD) and the impedance transformation ratio increases the efficiency of a PA with a small POUT. Using this result, a dual-VDD scheme is realized to increase the efficiency of a transmitter (TX). At a POUT of -20 dBm, compared with the conventional single-VDD scheme, the drain efficiency (DE) of the PA and the global efficiency (GE) of the TX with the dual-VDD scheme are increased by factors of 2.1 and 1.5, respectively. A PA fabricated by a 40 nm CMOS process achieved a DE of 42% at a POUT of -17 dBm. The TX with the PA achieves the highest GE of 28% at a POUT of -20 dBm and the lowest energy of 36pJ/bit (=36\ \muW@1Mbps with on-off keying) among the published results for TXs. [ABSTRACT FROM AUTHOR]