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Information about upcoming events of interest to Computer Society members. [ABSTRACT FROM PUBLISHER]

In the past years, quantum computers more and more have evolved from an academic idea to an upcoming reality. IBM’s project IBM ${Q}$ can be seen as evidence of this progress. Launched in March 2017 with the goal to provide access to quantum computers for a broad audience, this allowed users to conduct quantum experiments on a 5-qubit and, since June 2017, also on a 16-qubit quantum computer (called IBM QX2 and IBM QX3, respectively). Revised versions of these 5- and 16-qubit quantum computers (named IBM QX4 and IBM QX5, respectively) are available since September 2017. In order to use these, the desired quantum functionality (e.g., provided in terms of a quantum circuit) has to be properly mapped so that the underlying physical constraints are satisfied—a complex task. This demands solutions to automatically and efficiently conduct this mapping process. In this paper, we propose a methodology which addresses this problem, i.e., maps the given quantum functionality to a realization which satisfies all constraints given by the architecture and, at the same time, keeps the overhead in terms of additionally required quantum gates minimal. The proposed methodology is generic, can easily be configured for similar future architectures, and is fully integrated into IBM’s SDK. Experimental evaluations show that the proposed approach clearly outperforms IBM’s own mapping solution. In fact, for many quantum circuits, the proposed approach determines a mapping to the IBM architecture within minutes, while IBM’s solution suffers from long runtimes and runs into a timeout of 1 h in several cases. As an additional benefit, the proposed approach yields mapped circuits with smaller costs (i.e., fewer additional gates are required). All implementations of the proposed methodology are publicly available at http://iic.jku.at/eda/research/ibm_qx_mapping. [ABSTRACT FROM AUTHOR]

Histogram computation is a fundamental task often encountered in image processing systems. This plays an important role in various applications like image registration, show-through correction method in scanned image of duplex mode printed document, etc. Mutual information (MI) is one of the best metric for intensity-based multimodality image registration. Similarity measurement between the images consumes significant amount of the execution time in image registration. Computation of MI requires to obtain individual and joint histogram of two images. Typical joint histogram sizes range between 322 and 2562. The demand of hardware resource for computation of histogram increases substantially with increasing of histogram size. The array-based method may not be a suitable candidate in this application, because of large histogram size. Computation of histogram is inherently sequential in nature. But a parallel computation of histogram would reduce the processing time, which is going to help various imaging systems. In this paper, a memory-based parallel algorithm for histogram computation and its possible VLSI architecture have been presented. The architecture is mapped in field programmable gate array. The proposed architecture utilizes 99.66% less of the hardware compared to latest available architecture in the literature and consumes 8.78 mW power. [ABSTRACT FROM AUTHOR]

Computer vision systems have attracted much attention in recent years for use in detecting surface defects on rails; however, accurate and efficient recognition of possible defects remains challenging due to the variations shown by defects and also noise. This paper proposes a coarse-to-fine model (CTFM) to identify defects at different scales. The model works on three scales from coarse to fine: subimage level, region level, and pixel level. At the subimage level, the background subtraction model exploits row consistency in the longitudinal direction, and strongly filters the defect-free range, leaving roughly identified subimages within which defects may exist. At the next level, the region extraction model, inspired by visual saliency models, locates definite defect regions using phase-only Fourier transforms. At the finest level, the pixel subtraction model uses pixel consistency to refine the shape of each defect. The proposed method is evaluated using Type-I and Type-II rail surface defect detection data sets and an actual rail line. The experimental results show that CTFM outperforms state-of-the-art methods according to both the pixel-level index and the defect-level index. [ABSTRACT FROM AUTHOR]

DRAM refresh is responsible for significant performance and energy overheads in a wide range of computer systems, from mobile platforms to datacenters . With the growing demand for DRAM capacity and the worsening retention time characteristics of deeply scaled DRAM, refresh is expected to become an even more pronounced problem in future technology generations . This paper examines content aware refresh, a new technique that reduces the refresh frequency by exploiting the unidirectional nature of DRAM retention errors: assuming that a logical 1 and 0 respectively are represented by the presence and absence of charge, 1-to-0 failures are much more likely than 0-to-1 failures. As a result, in a DRAM system that uses a block error correcting code (ECC) to protect memory, blocks with fewer 1s can attain a specified reliability target (i.e., mean time to failure) with a refresh rate lower than that which is required for a block with all 1s. Leveraging this key insight, and without compromising memory reliability, the proposed content aware refresh mechanism refreshes memory blocks with fewer 1s less frequently. To keep the overhead of tracking multiple refresh rates manageable, refresh groups—groups of DRAM rows refreshed together—are dynamically arranged into one of a predefined number of refresh bins and refreshed at the rate determined by the ECC block with the greatest number of 1s in that bin. By tailoring the refresh rate to the actual content of a memory block rather than assuming a worst case data pattern, content aware refresh respectively outperforms DRAM systems that employ RAS-only Refresh, all-bank Auto Refresh, and per-bank Auto Refresh mechanisms by 12, 8, and 13 percent. It also reduces DRAM system energy by 15, 13, and 16 percent as compared to these systems. [ABSTRACT FROM AUTHOR]

Objective: Subtraction-based techniques are known for being theoretically rigorous and accurate methods for solving the forward problem in electroencephalography (EEG-FP) by means of the finite-element method. Within them, the projected subtraction (PS) approach is generally adopted because of its computational efficiency. Although this technique received the attention of the community, its sensitivity to degenerated elements is still poorly understood. In this paper, we investigate the impact of low-quality tetrahedra on the results computed with the PS approach. Methods: We derived upper bounds on the relative error of the element source vector as a function of geometrical features describing the tetrahedral discretization of the domain. These error bounds were then utilized for showing the instability of the PS method with regards to the mesh quality. To overcome this issue, we proposed an alternative technique, coined projected gradient subtraction (PGS) approach, that exploits the stability of the corresponding bounds. Results: Computer simulations showed that the PS method is extremely sensitive to the mesh shape and size, leading to unacceptable solutions of the EEG-FP in case of using suboptimal tessellations. This was not the case of the PGS approach, which led to stable and accurate results in a comparable amount of time. Conclusion: Solutions of the EEG-FP computed with the PS method are highly sensitive to degenerated elements. Such errors can be mitigated by the PGS approach, which showed better performance than the PS technique. Significance: The PGS is an efficient method for computing high-quality lead field matrices even in the presence of degenerated elements. [ABSTRACT FROM AUTHOR]

$\sf{ NTRUEncrypt}$  is one of the most promising candidates for quantum-safe cryptography. In this paper, we focus on the $\sf{ NTRU743}$  parameter set. We give a report on all known attacks against this parameter set and show that it delivers 256 bits of security against classical attackers and 128 bits of security against quantum attackers. We then present a parameter-dependent optimization using a tailored hierarchy of multiplication algorithms as well as the Intel AVX2 instructions, and show that this optimization is constant-time. Our implementation is two to three times faster than the reference implementation of $\sf{ NTRUEncrypt}$ . [ABSTRACT FROM AUTHOR]

Distributed storage systems (DSSs) in the presence of an external wiretapper are considered. A DSS is parameterized by $(n, k, d)$ , in which the data are stored across $n$ nodes (each with storage capacity $\alpha $ ), and must be recoverable by accessing the contents stored on any $k$ out of $n$ nodes. If a node fails, any $d \geq k$ out of $(n-1)$ nodes help in the repair (regeneration) of the failed node (by sending $d\beta $ units of repair data, where $\beta \leq \alpha $ ), so that the data can still be recovered from the DSS. For such a $(n, k, d)$ -DSS, security from the two types of wiretappers is investigated: 1) Type-I (node data) wiretapper, which can read the data stored on any $\ell

In this paper, we study the cycle structure of quasi-cyclic (QC) low-density parity-check (LDPC) codes with the goal of obtaining the shortest code with a given degree distribution and girth. We focus on QC-LDPC codes, whose Tanner graphs are cyclic liftings of fully connected base graphs of size $3 \times n, n \geq 4$ , and obtain minimal lifting degrees that result in girths 6 and 8. This is performed through an efficient exhaustive search, and as a result, we also find all the possible non-isomorphic codes with the same minimum block length, girth, and degree distribution. The exhaustive search, which is ordinarily a formidable task, is made possible by pruning the search space of many codes that are isomorphic to those previously examined in the search process. Many of the pruning techniques proposed in this paper are also applicable to QC-LDPC codes with base graphs other than the $3 \times n$ fully connected ones discussed here, as well as to codes with a larger girth. To further demonstrate the effectiveness of the pruning techniques, we use them to search for QC-LDPC codes with girths 10 and 12, and find a number of such codes that have a shorter block length compared with the best known similar codes in the literature. In addition, motivated by the exhaustive search results, we tighten the lower bound on the block length of QC-LDPC codes of girth 6 constructed from fully connected $3 \times n$ base graphs, and construct codes that achieve the lower bound for an arbitrary value of $n \geq 4$ . [ABSTRACT FROM AUTHOR]

Numerous papers dealing with the analysis of electromagnetic attacks against critical electronic devices have been made publicly available. In this paper, we exploit the principle of front-door coupling on smartphones headphone cables with specific electromagnetic waveforms. We present a smart use of intentional electromagnetic interference, resulting in finer impacts on an information system than a classical denial of service effect. As an outcome, we introduce a new silent remote voice command injection technique on modern smartphones. [ABSTRACT FROM AUTHOR]

In recent years, embedded dynamic random-access memory (eDRAM) technology has been implemented in last-level caches due to its low leakage energy consumption and high density. However, the fact that eDRAM presents slower access time than static RAM (SRAM) technology has prevented its inclusion in higher levels of the cache hierarchy. This paper proposes to mingle SRAM and eDRAM banks within the data array of second-level (L2) caches. The main goal is to achieve the best trade-off among performance, energy, and area. To this end, two main directions have been followed. First, this paper explores the optimal percentage of banks for each technology. Second, the cache controller is redesigned to deal with performance and energy. Performance is addressed by keeping the most likely accessed blocks in fast SRAM banks. In addition, energy savings are further enhanced by avoiding unnecessary destructive reads of eDRAM blocks. Experimental results show that, compared to a conventional SRAM L2 cache, a hybrid approach requiring similar or even lower area speedups the performance on average by 5.9 percent, while the total energy savings are by 32 percent. For a 45 nm technology node, the energy-delay-area product confirms that a hybrid cache is a better design than the conventional SRAM cache regardless of the number of eDRAM banks, and also better than a conventional eDRAM cache when the number of SRAM banks is an eighth of the total number of cache banks. [ABSTRACT FROM AUTHOR]

This paper presents an analysis of introducing active methodologies in the Computer Architecture course taught in the second year of the Computer Engineering Bachelor's degree program at the University of the Basque Country (UPV/EHU), Spain. The paper reports the experience from three academic years, 2011–2012, 2012–2013, and 2013–2014, in which three types of data were considered for analysis: students' dedication, as measured by time spent on the project, their marks, and their level of satisfaction. The study shows that about 86% of students are satisfied with the teaching methodology and are willing to continue using it in future courses. The study also shows that the active methodologies used contribute to the students' cross-curricular training and do not generate any great increase in student workload. Finally, a statistical analysis of the evolution of student performance showed that marks improved to a statistically significant extent after introducing active methodologies. [ABSTRACT FROM AUTHOR]

Heterogeneous systems on a single chip composed of a central processing unit, graphics processing unit (GPU), and field-programmable gate array (FPGA) are expected to emerge in the near future. In this context, the system on chip can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation (ME) is one such task that can be accelerated using FPGA and GPU for high-performance H.264/Advanced Video Coding encoder implementation. This paper presents an inherent parallel low-complexity rate-distortion (RD) optimized fast ME algorithm well suited for parallel implementations, eliminating various data dependencies caused by a reliance on spatial predictions. In addition, this paper provides details of the GPU and FPGA implementations of the parallel algorithm by using OpenCL and Very High Speed Integrated Circuits (VHSIC) Hardware Descriptive Language (VHDL), respectively, and presents a practical performance comparison between the two implementations. The experimental results show that the proposed scheme achieves significant speedup on GPU and FPGA, and has comparable RD performance with respect to sequential fast ME algorithm. [ABSTRACT FROM AUTHOR]

For practical use of microwave simulations in industry applications such as high frequency product design, this paper presents a conceptual design of 3-D finite difference time domain (FDTD) dedicated computer with dataflow architecture as one of the portable high performance computing technologies. A basic concept of the dataflow architecture for the FDTD dedicated computer itself was presented already in 2003 for 2-D microwave simulations. Detail design of 3-D FDTD dataflow machine is considered in this paper. [ABSTRACT FROM PUBLISHER]

Huang and Wu in [IEEE Transactions on Computers 46 (1997) 484-490] introduced the balanced hypercube BH_n as an interconnection network topology for computing systems, and they proved that BH_n is vertex-transitive. However, some other symmetric properties, say edge-transitivity and arc-transitivity, of BH_n remained unknown. In this paper, we solve this problem and prove that BH_n is an arc-transitive Cayley graph. Using this, we also investigate some reliability measures, including super-connectivity, cyclic connectivity, etc., in BH_n. First, we prove that every minimum edge-cut of BH_n (n\ge 2) isolates a vertex, and every minimum vertex-cut of BH_n (n\ge 3) isolates a vertex. This is stronger than that obtained by Wu and Huang which shows the connectivity and edge-connectivity of BH_n are 2n. Second, Yang [Applied Mathematics and Computation 219 (2012) 970-975.] proved that for n\ge 2, the super-connectivity of BH_n is 4n-4 and the super edge-connectivity of BH_n is 4n-2. In this paper, we proved that BH_n (n\ge 2) is super-\lambda^\prime but not super-\kappa^\prime . That is, every minimum super edge-cut of BH_n (n\ge 2) isolates an edge, but the minimum super vertex-cut of BH_n (n\ge 2) does not isolate an edge. Third, we also obtain that for n\ge 2, the cyclic connectivity of BH_n is 4n-4 and the cyclic edge-connectivity of BH_n is 4(2n-2). That is, to become a disconnected graph which has at least two components containing cycles, we need to remove at least 4n-4 vertices (resp. 4(4n-2) edges) from BH_n (n\ge 2). [ABSTRACT FROM AUTHOR]

With the increasing call for green cloud, reducing energy consumption has been an important requirement for cloud resource providers not only to reduce operating costs, but also to improve system reliability. Dynamic voltage scaling (DVS) has been a key technique in exploiting the hardware characteristics of cloud datacenters to save energy by lowering the supply voltage and operating frequency. This paper presents a novel stochastic framework for energy efficiency and performance analysis of DVS-enabled cloud. This framework uses virtual machine request arrival rate, failure rate, repair rate, and service rate of datacenter servers as model inputs. Based on a queuing-network-based analysis, this paper gives analytic solutions of three metrics. The proposed framework can be used to help the design and optimization of energy-aware high performance cloud systems. [ABSTRACT FROM AUTHOR]

Compared to robotic injection of suspended cells (e.g., embryos and oocytes), fewer attempts were made to automate the injection of adherent cells (e.g., cancer cells and cardiomyocytes) due to their smaller size, highly irregular morphology, small thickness (a few micrometers thick), and large variations in thickness across cells. This paper presents a robotic system for automated microinjection of adherent cells. The system is embedded with several new capabilities: automatically locating micropipette tips; robustly detecting the contact of micropipette tip with cell culturing surface and directly with cell membrane; and precisely compensating for accumulative positioning errors. These new capabilities make it practical to perform adherent cell microinjection truly via computer mouse clicking in front of a computer monitor, on hundreds and thousands of cells per experiment (versus a few to tens of cells as state of the art). System operation speed, success rate, and cell viability rate were quantitatively evaluated based on robotic microinjection of over 4000 cells. This paper also reports the use of the new robotic system to perform cell–cell communication studies using large sample sizes. The gap junction function in a cardiac muscle cell line (HL-1 cells), for the first time, was quantified with the system. [ABSTRACT FROM PUBLISHER]

Threshold and ambiguity phenomena are studied in Part I of this paper where approximations for the mean-squared error (MSE) of the maximum-likelihood estimator are proposed using the method of interval estimation (MIE), and where approximate upper and lower bounds are derived. In this part, we consider time-of-arrival estimation and we employ the MIE to derive closed-form expressions of the begin-ambiguity, end-ambiguity and asymptotic signal-to-noise ratio (SNR) thresholds with respect to some features of the transmitted signal. Both baseband and passband pulses are considered. We prove that the begin-ambiguity threshold depends only on the shape of the envelope of the ACR, whereas the end-ambiguity and asymptotic thresholds only on the shape of the ACR. We exploit the results on the begin-ambiguity and asymptotic thresholds to optimize, with respect to the available SNR, the pulse that achieves the minimum attainable MSE. The results of this paper are valid for various estimation problems. [ABSTRACT FROM PUBLISHER]

In this paper, we study the graphical structure of elementary trapping sets (ETSs) of variable-regular low-density parity-check (LDPC) codes. ETSs are known to be the main cause of error floor in LDPC coding schemes. For the set of LDPC codes with a given variable node degree \(d_{l}\) and girth \(g\) , we identify all the nonisomorphic structures of an arbitrary class of \((a,b)\) ETSs, where \(a\) is the number of variable nodes and \(b\) is the number of odd-degree check nodes in the induced subgraph of the ETS. This paper leads to a simple characterization of dominant classes of ETSs (those with relatively small values of \(a\) and \(b\) ) based on short cycles in the Tanner graph of the code. For such classes of ETSs, we prove that any set \({\cal S}\) in the class is a layered superset (LSS) of a short cycle, where the term layered is used to indicate that there is a nested sequence of ETSs that starts from the cycle and grows, one variable node at a time, to generate \({\cal S}\) . This characterization corresponds to a simple search algorithm that starts from the short cycles of the graph and finds all the ETSs with LSS property in a guaranteed fashion. Specific results on the structure of ETSs are presented for \(d_{l} = 3, 4, 5, 6\) , \(g = 6, 8\) , and \(a, b \leq 10\) in this paper. The results of this paper can be used for the error floor analysis and for the design of LDPC codes with low error floors. [ABSTRACT FROM AUTHOR]

Attackers target many different types of computer systems in use today, exploiting software vulnerabilities to take over the device and make it act maliciously. Reports of numerous attacks have been published, against the constrained embedded devices of the Internet of Things, mobile devices like smartphones and tablets, high-performance desktop and server environments, as well as complex industrial control systems. Trusted computing architectures give users and remote parties like software vendors guarantees about the behaviour of the software they run, protecting them against software-level attackers. This paper defines the security properties offered by them, and presents detailed descriptions of twelve hardware-based attestation and isolation architectures from academia and industry. We compare all twelve designs with respect to the security properties and architectural features they offer. The presented architectures have been designed for a wide range of devices, supporting different security properties. [ABSTRACT FROM PUBLISHER]

This paper proposes a comprehensive methodology for the design of a controllable electric vehicle charger capable of making the most of the interaction with an autonomous smart energy management system (EMS) in a residential setting. Autonomous EMSs aim achieving the potential benefits associated with energy exchanges between consumers and the grid, using bidirectional and power-controllable electric vehicle chargers. A suitable design for a controllable charger is presented, including the sizing of passive elements and controllers. This charger has been implemented using an experimental setup with a digital signal processor to validate its operation. The experimental results obtained foresee an adequate interaction between the proposed charger and a compatible autonomous EMS in a typical residential setting. [ABSTRACT FROM PUBLISHER]

Ultrahigh definition (UHD), such as 4K/8K, is becoming the mainstream of video resolution nowadays. High Efficiency Video Coding (HEVC) is the emerging video coding standard to process the encoding and decoding of UHD video. This paper first develops multiple techniques that allow the proposed hardware architecture for intra prediction of HEVC working in full pipeline. The proposed techniques include: 1) a novel buffer structure for reference samples; 2) a mode-dependent scanning order; and 3) an inverse method for reference sample extension. The size of the buffer is 3K b for luma component and 3K b for chroma components, providing sufficient accessing to the reference samples. Since the data dependency between two neighboring blocks is addressed by the mode-dependent scanning order, the proposed fully pipelined design can produce 4 pixels/clock cycle. As a result, the throughput of the proposed architecture is capable to support $3840 \times 2160$ videos at 30 frames/s. [ABSTRACT FROM PUBLISHER]

This paper focuses on the compromising video emanations from a desktop computer with a liquid-crystal display (LCD). Near-field tests are performed in a common unshielded office environment to investigate the video information leakage, and the tests show that the video graphics adapter (VGA) connector is a leaking source. To illustrate the mechanism of the video leakage, a wire antenna model is developed according to the physical dimensions of the connector. The radiated fields of the connector are calculated in the time domain from this model, the results are verified by the tests. Combining the expressions of the radiated fields and the transfer function of the test probe, the function relationship between the original red/green/blue signal and the intercepted signal is established. Finally, a readable text is reconstructed from the intercepted signal when a Chinese document is displayed on the LCD. [ABSTRACT FROM PUBLISHER]

The 2008 revision of the IEEE-754 standard, which governs floating-point arithmetic, recommends that a certain set of elementary functions should be correctly rounded. Successful attempts for solving the Table Maker's Dilemma in binary64 made it possible to design CRlibm, a library which offers correctly rounded evaluation in binary64 of some functions of the usual libm. It evaluates functions using a two step strategy, which relies on a folklore heuristic that is well spread in the community of mathematical functions designers. Under this heuristic, one can compute the distribution of the lengths of runs of zeros/ones after the rounding bit of the value of the function at a given floating-point number. The goal of this paper is to change, whenever possible, this heuristic into a rigorous statement. The underlying mathematical problem amounts to counting integer points in the neighborhood of a curve, which we tackle using so-called exponential sums techniques, a tool from analytic number theory. [ABSTRACT FROM AUTHOR]

Video object segmentation can be considered as one of the most challenging computer vision problems. Indeed, so far, no existing solution is able to effectively deal with the peculiarities of real-world videos, especially in cases of articulated motion and object occlusions; limitations that appear more evident when we compare the performance of automated methods with the human one. However, manually segmenting objects in videos is largely impractical as it requires a lot of time and concentration. To address this problem, in this paper we propose an interactive video object segmentation method, which exploits, on one hand, the capability of humans to identify correctly objects in visual scenes, and on the other hand, the collective human brainpower to solve challenging and large-scale tasks. In particular, our method relies on a game with a purpose to collect human inputs on object locations, followed by an accurate segmentation phase achieved by optimizing an energy function encoding spatial and temporal constraints between object regions as well as human-provided location priors. Performance analysis carried out on complex video benchmarks, and exploiting data provided by over 60 users, demonstrated that our method shows a better trade-off between annotation times and segmentation accuracy than interactive video annotation and automated video object segmentation approaches. [ABSTRACT FROM PUBLISHER]

This paper presents the feasibility study of variable inductor (VI)-based bidirectional dc–dc converter for applications with a wide range of load variations such as electric vehicles. An additional winding is introduced to the conventional power inductor to inject a control current for adjusting the permeability of magnetic cores. This has significant merits in controlling the current ripple and enhancing the current handling capability of power inductors, thereby reducing the size of magnetic components and improving the performance. For current values, twice and three times the rated current, the current ripple is reduced by 40.90 % and 36.10 %, respectively. Nonetheless, this device requires a precisely controlled dc-current. As such, a small current controlled, low-power and low-cost buck converter is built to power up the auxiliary winding. To improve the reliability and robustness of the VI, an integrated closed loop control that enables the control of the main converter and the auxiliary converter is also implemented and tested in real time to test the viability of the VI. [ABSTRACT FROM PUBLISHER]

Fault diagnosis, including fault detection and isolation, is a critical task for computer networks. Among the various techniques used for online system-level diagnosis, we are interested in the approach based on temporal information processing. The delays of the computer networks are inevitable, and the fault localization process has to take into account bounded delays or the temporal constraints. Temporal information is fundamental in model-based diagnosis. There can be cycles or loops in a computer network, but the fault reasoning methods for such cases are seldom considered in the literature. This paper provides an analytic model based on the cyclic temporal constraint network (CTCN), which aims at the fault diagnosis of cyclic computer networks using temporal information. The goal of the proposed framework is twofold: given the network structures and the predetermined candidate fault causes, the CTCN model corresponding the computer network under test is formulated; based on the CTCN model, given the alarms sequences with timestamps, the fault diagnosis process is executed to determine the most likely fault cause(s) with its/their time interval(s) of occurrence(s). The reasoning method is dependent on time point and time distance information, with which the fault motivators (i.e., actors) and fault responders (i.e., victims) can be identified. The calculation process consists of three steps: 1) establishment of the objective function; 2) determination of the fault propagation paths; and 3) determination of the expected states with a given fault hypothesis. Finally, the proposed method is demonstrated via an application study, and the effectiveness of our proposed method is verified. [ABSTRACT FROM PUBLISHER]

This paper models 1-out-of-N standby computing systems with a dynamic checkpointing policy. The system performs a real-time mission task that has to be accomplished within an allowed mission time. During the mission, to facilitate an effective failure recovery the system undergoes checkpointing procedures according to a policy that dynamically determines a checkpointing frequency based on the activated element and remaining work for completing the mission. System elements are heterogeneous; they can follow different, arbitrary types of time-to-failure distributions, have different performance and wait in different standby modes before their activation. A new numerical algorithm based on state space event transitions is first proposed to evaluate mission success probability of the real-time standby systems considered in this work. Additional new contributions are made by formulating and solving optimal dynamic checkpointing policy problems, as well as an integrated optimization problem that finds the optimal combination of checkpointing policy and element activation sequence maximizing mission success probability. Advantages of using the dynamic checkpointing policy over fixed even checkpoints are demonstrated through examples. Examples and results are also provided to illustrate effects of different mission and element parameters on mission success probability as well as on the optimal dynamic checkpointing policy. [ABSTRACT FROM AUTHOR]

Data transfers happen frequently in server clusters for software and application deployment, and in parallel computing clusters to transmit intermediate results in batches among servers between computation stages. This paper presents Cooper, an optimized prototype system to speedup multi-batch data transfers among a cluster of servers, leveraging a theoretically proven optimal algorithm called “coded permutation gossip,” which employs a simple random topology control scheme to best utilize bandwidth and decentralized random linear network coding to maximize the useful information transmitted. On a process-level coding-transfer pipeline, we investigate the best block division, batch division and inter-batch scheduling strategies to minimize the broadcast finish time in a realistic setting. For batch-based transfers, we propose a scheduling algorithm with low overhead that overlaps the transfers of consecutive batches and temporarily prioritizes later batches, to further reduce the broadcast finish time. We describe an asynchronous and distributed implementation of Cooper and have deployed it on Amazon EC2 for evaluation. Based on results from real experiments, we show that Cooper can almost double the speed of data transfers in computing clusters, as compared to state-of-the-art content distribution tools like BitTorrent, at a low CPU overhead. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of online to traditional face-to-face delivery of undergraduate digital systems material. Two specific components of digital content were compared and evaluated: a sophomore logic circuits course with no laboratory, and a microprocessor laboratory component of a junior-level computer systems course. For each of these, a baseline level of student understanding was evaluated when they were being taught using traditional, face-to-face delivery. The course and lab component were then converted to being fully online, and the level of student understanding was again measured. In both cases, the same purpose-developed assessment tools were used to carry out the measurement of understanding. This paper presents the details of how the course components were converted to online delivery, including a discussion of the technology used to accomplish remote access of the electronic test equipment used in the laboratory. A comparison is then presented between the control and the experimental groups, including a statistical analysis of whether the delivery approach impacted student learning. Finally, student satisfaction is discussed, and instructor observations are given for the successful remote delivery of this type of class and laboratory. [ABSTRACT FROM PUBLISHER]

For advanced features of next generation vehicles, the real-time programs in automotive embedded systems are dramatically increasing. For such large volume program codes, this paper proposes a novel framework to use high-density and low-cost nonvolatile memory, i.e., NAND flash memory, as a low-cost means of storing and executing hard real-time programs. Regarding this, one challenge is that NAND flash memory allows only 2 KB page-based read operations not per-byte random accesses, which requires RAM as working storage for code executions. This paper proposes two solutions, i.e., partitioned RAM solution and shared RAM solution, that minimize the RAM size required to deterministically guarantee the deadlines of all the hard real-time tasks. The proposed solutions are verified with the actual real-time programs for unmanned autonomous driving. To the best of our knowledge, this is the first work that allows us to use NAND flash memory for hard real-time program executions with the minimal usage of RAM. [ABSTRACT FROM PUBLISHER]

This paper proposes a new class of multisine excitations that allows efficient characterization of nonlinear circuits. By offsetting the frequency of tones, one can distinguish between different intermodulation products in a multisine response. This property leads to many applications for nonlinear circuit characterization, such as in-band distortion measurements, memory effects characterization, and model performance assessment. Some applications are highlighted in this paper, focusing especially on the characterization of memory effects. The effectiveness of the approach is demonstrated with a series of measurement results. [ABSTRACT FROM AUTHOR]

Recovering a sparse signal from an undersampled set of random linear measurements is the main problem of interest in compressed sensing. In this paper, we consider the case where both the signal and the measurements are complex-valued. We study the popular recovery method of \ell 1-regularized least squares or LASSO. While several studies have shown that LASSO provides desirable solutions under certain conditions, the precise asymptotic performance of this algorithm in the complex setting is not yet known. In this paper, we extend the approximate message passing (AMP) algorithm to solve the complex-valued LASSO problem and obtain the complex approximate message passing algorithm (CAMP). We then generalize the state evolution framework recently introduced for the analysis of AMP to the complex setting. Using the state evolution, we derive accurate formulas for the phase transition and noise sensitivity of both LASSO and CAMP. Our theoretical results are concerned with the case of i.i.d. Gaussian sensing matrices. Simulations confirm that our results hold for a larger class of random matrices. [ABSTRACT FROM AUTHOR]

This paper presents the basic features of a software system developed to support the teaching of digital logic, as well as the experience of using it in the Digital Logic course taught at the School of Electrical Engineering, University of Belgrade, Serbia. The system has been used for several years, both by students for self-learning and laboratory work, and by teachers to automate the assessment and verification of students' work. The system allows users to design and simulate a switching circuit. It also collects data on all student activities and transfers these to the school's information system. Finally, the paper gives figures demonstrating the overall benefits of the system. [ABSTRACT FROM AUTHOR]

Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software. This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. The envisioned underdesigned and opportunistic computing (UnO) machines face a number of challenges related to the sensing infrastructure and software interfaces that can effectively utilize the sensory data. In this paper, we outline specific sensing mechanisms that we have developed and their potential use in building UnO machines. [ABSTRACT FROM AUTHOR]

High-performance heterogeneous computers that employ field programmable gate arrays (FPGAs) as computational elements are known as high-performance reconfigurable computers (HPRCs). For floating-point applications, these FPGA-based processors must satisfy a variety of heuristics and rules of thumb to achieve a speedup compared with their software counterparts. By way of a simple sparse matrix Jacobi iterative solver, this paper illustrates some of the issues associated with mapping floating-point kernels onto HPRCs. The Jacobi method was chosen based on heuristics developed from earlier research. Furthermore, Jacobi is relatively easy to understand, yet is complex enough to illustrate the mapping issues. This paper is not trying to demonstrate the speedup of a particular application nor is it suggesting that Jacobi is the best way to solve equations. The results demonstrate a nearly threefold wall clock runtime speedup when compared with a software implementation. A formal analysis shows that these results are reasonable. The purpose of this paper is to illuminate the challenging floating-point mapping process while simultaneously showing that such mappings can result in significant speedups. The ideas revealed by research such as this have already been and should continue to be used to facilitate a more automated mapping process. [ABSTRACT FROM AUTHOR]

This paper first analyzes the symbol error rate (SER) performance of the space-time network coding (STNC) over independent but not necessarily identically distributed (i.n.i.d) Nakagami- $m$ fading channels, where multiple sources transmit information symbols to a destination through multiple helping amplify-and-forward (AF) relays. The exact expressions of the overall end-to-end received signal-to-noise ratio (SNR) via multiple STNC-AF relays and its moment generating function (MGF) are derived. Based on these results, the closed-form expression of STNC-AF for the SER with $M$ -ary phase-shift keying and $M$ -ary quadrature-amplitude modulation (QAM) modulations are then presented by adopting the unified MGF method. Furthermore, an approximate SER expression with low computational complexity is also given. In order to observe the performance limit, the diversity order and the nonorthogonality of STNC codes are discussed. Simulation results demonstrate our analytical results and it is illustrated that the diversity order of the STNC with multiple AF relay nodes is a sum function of the fading index of the direct link and the minimal fading indices of the multiple two-hop links. [ABSTRACT FROM PUBLISHER]

Caching is often used in content delivery networks as a mechanism for reducing network traffic. Recently, the technique of coded caching was introduced whereby coding in the caches and coded transmission signals from the central server were considered. Prior results in this area demonstrate that carefully designing the placement of content in the caches and designing appropriate coded delivery signals from the server allow for a system where the delivery rates can be significantly smaller than conventional schemes. However, matching upper and lower bounds on the transmission rate have not yet been obtained. In this paper, we derive tighter lower bounds on the coded caching rate than were known previously. We demonstrate that this problem can equivalently be posed as a combinatorial problem of optimally labeling the leaves of a directed tree. Our proposed labeling algorithm allows for significantly improved lower bounds on the coded caching rate. Furthermore, we study certain structural properties of our algorithm that allow us to analytically quantify improvements on the rate lower bound for general values of the problem parameters. This allows us to obtain a multiplicative gap of at most four between the achievable rate and our lower bound. [ABSTRACT FROM PUBLISHER]

Multi-tiered Parallel I/O systems that combine traditional HDDs with emerging SSDs mitigate the cost burden of SSDs while benefiting from their superior I/O performance. While a multi-tiered parallel I/O system is promising for data-intensive applications in high-performance (HPC) domains, placing data on each tier of the system to achieve high I/O performance remains a challenge. In this paper, we propose a cost-aware region-level (CARL) data placement scheme in multi-tiered parallel I/O systems. CARL divides a large file into several small regions, and then places regions on different types of servers based on region access costs. CARL includes a static policy S-CARL and a dynamic policy D-CARL. For applications whose I/O access patterns are completely known, S-CARL calculates the region costs within the entire workload duration, and uses a static data placement scheme to selectively place regions on the proper servers. To adapt to applications whose access patterns are unknown in advance, D-CARL uses a dynamic data placement scheme which migrates data among different servers within each time window. We have implemented CARL under MPI-IO library and OrangeFS parallel file system environment. Our evaluation with representative benchmarks and an application shows that CARL is both feasible and able to improve I/O performance significantly. [ABSTRACT FROM PUBLISHER]

In this paper, we deal with the problem of efficiently assessing the higher order vulnerability of a hardware cryptographic circuit. Our main concern is to provide methods that allow a circuit designer to detect early in the design cycle if the implementation of a Boolean-additive masking countermeasure does not hold up to the required protection order. To achieve this goal, we promote the search for vulnerabilities from a statistical problem to a purely symbolical one and then provide a method for reasoning about this new symbolical interpretation. Eventually we show, with a synthetic example, how the proposed conceptual tool can be used for exploring the vulnerability space of a cryptographic primitive. [ABSTRACT FROM AUTHOR]

The ephemeral content popularity seen with many content delivery applications can make indiscriminate on-demand caching in edge networks highly inefficient, since many of the content items that are added to the cache will not be requested again from that network. In this paper, we address the problem of designing and evaluating more selective edge-network caching policies. The need for such policies is demonstrated through an analysis of a dataset recording YouTube video requests from users on an edge network over a 20-month period. We then develop a novel workload modelling approach for such applications and apply it to study the performance of alternative edge caching policies, including indiscriminate caching and cache on $k$ th request for different $k$ . The latter policies are found able to greatly reduce the fraction of the requested items that are inserted into the cache, at the cost of only modest increases in cache miss rate. Finally, we quantify and explore the potential room for improvement from use of other possible predictors of further requests. We find that although room for substantial improvement exists when comparing performance to that of a perfect “oracle” policy, such improvements are unlikely to be achievable in practice. [ABSTRACT FROM AUTHOR]

In the past, computer programming was perceived as a task only carried out by computer scientists; in the 21st century, however, computer programming is viewed as a critical and necessary skill that everyone should learn. In order to improve teaching of problem-solving abilities in a computing environment, extensive research is being done on teaching–learning methods, types of teaching software, the educational environment, and related tools. This paper, based on diverse experimental results, proposes an environment where elementary students can easily learn and practice computer programming. The proposed robot game environment used a tangible programming tool with which students can easily create robot programs, without learning syntax, and then validate their programming results; it can also provide various game activities to incite students’ interest. Observation of elementary school students placed in the robot game environment confirmed the tool’s usability and entertainment aspects, and students’ attitudes toward programming and their understanding of programming concepts improved. [ABSTRACT FROM PUBLISHER]

Cost computation, cost aggregation, disparity optimization, and disparity refinement are the four main steps for stereo matching. While the first three steps have been widely investigated, few efforts have been taken on disparity refinement. In this paper, we propose a color image-guided disparity refinement method to further remove the boundary-inconsistent regions on disparity map. First, the origins of boundary-inconsistent regions are analyzed. Then, these regions are detected with the proposed hybrid-superpixel-based strategy. Finally, the detected boundary-inconsistent regions are refined by a modified weighted median filtering method. Experimental results on various stereo matching conditions validate the effectiveness of the proposed method. Furthermore, depth maps obtained by active depth acquisition devices like Kinect can also be well refined with our proposed method. [ABSTRACT FROM PUBLISHER]