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This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper focuses on the common dc-link voltage between a three-phase diode rectifier and a modular multilevel cascade inverter based on double-star chopper cells (MMCI-DSCC) for a medium-voltage motor drive. This motor drive can be operated even when no capacitor exists on the dc link. However, a nonnegligible, but predictable, amount of switching-ripple voltage occurs on the dc link. This paper achieves modeling and analysis of the switching-ripple voltage, thus making it possible to design a small-sized dc passive filter consisting of series connection of a film capacitor and a damping resistor. A 400-V, 15-kW down scaled system is used to confirm the effectiveness of the analysis and the dc filter. Experimental results show that the switching-ripple voltage can be attenuated satisfactorily by the dc filter, and that the power loss dissipated in the damping resistor is negligible, compared to the rated power of 15 kW. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) in voltage-source inverters (VSIs) has been well defined and is frequently referred to in the literature. While often referred to, there is no real consistency with respect to how the CMV properties of an individual modulation scheme are evaluated, lacking tools to assess the relative merits or disadvantages of a certain topology or modification of a control scheme. The way that it is analyzed is still mostly a matter of the different authors' foci. In this paper, we propose a metric for the analysis of the CMV, aiming to fill the aforementioned gap. Thereby, the CMV in VSIs is quantified by the number of possible levels and the step sizes between different levels, as well as the respective frequencies of occurrence. The first two are given by the number of levels and the number of phases of the inverter. Depending on the modulation (control) schemes, all possibly available levels or a few of these levels are present in the CMV. We illustrate the use of the tool by applying it to thoroughly study the CMV properties intrinsic to the topologies of multilevel multiphase single- as well as double-ended diode-clamped VSI drive systems. As part of this analysis, we uncover new relationships concerning the existence of zero CMV level. Furthermore, we exemplarily apply the developed tool to the assessment of the CMV properties of selected pulse width modulation (PWM) control schemes and translate the findings into an interpretation of the endangerment of a given drive to suffer damage from inverter-induced bearing currents. The theoretical findings are supported by measurements. This paper also reviews the literature on CMV in multilevel multiphase VSI systems. With the proposed metric in mind, the CMV being mostly discussed as an element of different foci becomes even clearer, confirming again the need for the development of such a tool. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

A family of isolated buck–boost dc/dc converter for wide input-voltage range is proposed in this paper, and the full-bridge (FB) boost converter, being one of the typical topologies, is analyzed. Due to the existence of the resonant inductor (including the leakage inductor), the FB-boost converter can only adopt the two-edge-modulation (TEM) scheme with the FB cell being leading-edge modulated and the boost cell being trailing-edge modulated to minimize the inductor current ripple over the input-voltage range, and a phase-shift-control-scheme-based TEM with the use of the market available controller IC such as UC3895 is proposed, which realizes phase-shifted control for the FB cell to achieve zero-voltage switching. In order to improve the reliability and efficiency of the FB-boost converter, a three-mode dual-frequency control scheme is proposed, in which the FB-boost converter operates in boost, FB-boost and FB modes in low, medium and high input voltage regions, respectively, and for which the expression of the inductor current ripple is derived in this paper. As the input voltage in the FB-boost mode is close to the output voltage, the inductor current ripple in this mode is much smaller than that in the other modes, and the switching frequency of the boost cell in this mode can be lowered to one-(2N+1)th of the preset switching frequency to reduce the switching loss, and hence, to improve the efficiency. A 250–500 V input, 360 V output, and 6 kW rated power prototype is fabricated to verify the effectiveness of the design and control method. The average efficiency over the input-voltage range is 96.5%, and the highest efficiency attained is 97.2%. [ABSTRACT FROM AUTHOR]

In this paper, two new optimized common-mode voltage reduction PWM (CMVRPWM) strategies based on solving the established constrained nonlinear programming models in the time domain are proposed and analyzed. The proposed current ripple losses-optimized CMVRPWM (CRLO-CMVRPWM) minimizes the mean-square values of the three-phase current ripples by calculating the optimized special solutions of the voltage–second balance equations under the designed switching sequences. CRLO-CMVRPWM can achieve better output waveform quality than the existing methods. The proposed switching losses-optimized CMVRPWM (SLO-CMVRPWM) online optimizes the bus-clamping styles according to the phase currents to minimize the switching losses under different load power factors. Compared to the near-state PWM with fixed bus-clamping styles, SLO-CMVRPWM can reduce more switching losses in broader range of the modulation index. Simulation and experimental results verify the superiority of the proposed strategies to the conventional ones. [ABSTRACT FROM PUBLISHER]

Pulse width modulation schemes are aimed at adjusting the fundamental component while reducing the harmonic content of an inverter output voltage or current. This paper addresses the topic of optimal inverter operation in reference to a given objective function. The objective function could embody either a single performance criterion, such as voltage or current total harmonic distortion (THD), or a weighted sum of multiple criteria. The proposed method ensures primacy of the chosen solution while imposing no restriction over its modulation index. In particular, operating the inverter by the chosen solution would result in performances superior to any other modulation scheme commutating in an equal number of switching angles per fundamental cycle. The proposed method allows for the consideration of practical inverter constraints and prevents the possibility of impractical switching sequence. A detailed investigation of the method is given, accompanied by two practical cases minimizing, respectively, phase-voltage THD and line-current THD of a three-level inverter. Selected simulation and experimental results are presented to validate the theoretical part. [ABSTRACT FROM AUTHOR]

The advancement in power electronics has made the use of any number of phases in ac machines possible since with the inverter, any number of phase voltages can be realized as long as the corresponding inverter exists. To supply multiphase drives requires multiphase voltage source inverters (VSIs) whose output voltages depend very much on the methods of generating the pulses to turn on and turn off the inverter devices appropriately. This paper presents an analytical technique for the determination of the expressions for the modulation signals used in the carrier-based sinusoidal and generalized discontinuous pulse width modulation schemes for two-level, five-phase voltage source converters. These expressions can be used for both balanced and unbalanced phase voltages generated by any two-level multiphase inverter, in generating the required reference signals appropriately. An example of a five-phase VSI is presented to illustrate the strategy. Simulation and experimental results are presented in which a close examination shows that both results are similar for the balanced and unbalanced load voltage cases. [ABSTRACT FROM AUTHOR]

The inherent low switching frequency in medium-voltage alternating-current industrial drives presents power-quality and filter-design challenges. In this paper, four multilevel pulsewidth-modulation methods; phase disposition (PD), switching-loss minimization (SLM), and selective harmonic elimination (SHE) up to the 17th and 29th harmonics, respectively, are considered. The characteristics of long-cable effects on common-mode voltage (CMV) and differential-mode voltage (DMV), inverter losses and efficiency, induction machine voltage, and current harmonics are analyzed. Very little has been published in these quantitative comparisons. It is shown that the SHE method has reduced CMV as compared with the PD and SLM algorithms. Elimination of up to the 29th harmonic achieves the best harmonic performance without needing an output filter, at the expense that the losses are higher with a lower efficiency. Analytical and simulation results using the Piecewise Linear Electrical Circuit Simulation for the power-electronic circuits and MATLAB/Simulink for control systems are experimentally verified with a 1000-hp 4160-V neutral-point-clamped adjustable-speed-drive system that includes a 24-pulse front-end voltage source converter. [ABSTRACT FROM AUTHOR]

In this paper, two space-vector-based pulsewidth modulation (PWM) (SVPWM) strategies named equal- and proportional-duty SVPWMs are described, which are used to synthesize a four-level waveform from an open-end winding configuration of an induction motor. Two isolated dc-link voltages, which are in the ratio of 2 : 1, are employed to achieve this objective. Both of these PWM strategies achieve the avoidance of overcharging of the dc-link capacitor of an inverter operating with lower dc-link voltage by its counterpart with higher dc-link voltage. Implementation of these PWM strategies requires only the instantaneous three-phase reference voltages, eliminating the need of sector identification or lookup tables. The numbers of samples per cycle for individual inverters are selected in such a way that the quarter-wave, half-wave, and three-phase symmetries are achieved for the dual-inverter drive despite unequal dc-link voltages for the constituent inverters. It is also shown that one of the two PWM techniques, called the proportional-duty SVPWM, results in a better spectral performance and lower switching power loss in the overall dual-inverter system compared to the equal-duty SVPWM. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive analytical investigation of the four-switch three-phase (B4) voltage source inverter. The double Fourier integral analysis is used as an analytical approach to determine the phase-leg switched voltage spectrum under condition of natural sampling. The performance of two proposed switching sequences are subsequently evaluated when the harmonic copper losses are chosen as performance criterion. For a clear identification of dc-link voltage, the spectrum of dc-link current is characterized by convolution of switching function spectrum and corresponding phase current spectrum, in which fundamental component appears causing offset and fluctuation in dc-link two-capacitor voltages. The offset can be suppressed by certain switching states, whereas the effect of fluctuation must be neutralized through analytical compensation for modulating waveforms. Otherwise, symmetry of three-phase output currents and reliable operation of the system will not be retained. Finally, the analytically calculated spectrum of output voltage and dc-link current are demonstrated by comparing with those obtained by fast Fourier transform (FFT) analysis of simulated waveforms in MATLAB/SIMULINK. The capacitor voltage offset suppression and fluctuation effect neutralization are carried out by simulations and experiments, in which the results confirm the validity of the analytical investigation. [ABSTRACT FROM AUTHOR]

In medium-/high-power inverters, optimal pulse-width modulation (OPWM) is often used to reduce the switching frequency and at the same time, realize selective harmonic elimination (SHE). For both two-level and multilevel inverters, most selective harmonic elimination (SHE) studies are based on solving multiple variable high-order nonlinear equations. Furthermore, for multilevel inverters, SHE has been often studied based on the assumption of balanced dc levels and single switching per level. In this paper, the authors further developed harmonics injection and equal area criteria-based four-equation method to realize OPWM for two-level inverters and multilevel inverters with unbalanced dc sources. For the cases, where only small number of voltage levels are available, weight oriented junction point distribution is utilized to enhance the performance of the four-equation method. A case study of multilevel inverter at low-modulation index is used as an example. Compared with existing methods, the proposed method does not involve complex equation groups and is much easier to be utilized in the case of large number of switching angles, or multiple switching angles per voltage level in multilevel inverters. [ABSTRACT FROM AUTHOR]

With regard to a five-level inverter comprising flying-capacitor asymmetric H-bridge, the impact on the capacitor voltage under conventional modulation approach is analyzed. Since it is sensitive to the fundamental period and the load current, it may introduce undesired low-order harmonics into the output voltage and may even break down the power switches due to the considerable fluctuation of the flying-capacitor voltage. Thus, this paper proposes a novel pulsewidth-modulation scheme with the positive and negative cross carriers, which controls the flying-capacitor voltage by utilizing the redundant switching states of the output voltages. Three modes of precharging the flying capacitor without extra equipments are presented. Moreover, the capacitance of the flying capacitor and the switching frequency of the power switches can be chosen according to the allowable fluctuation of the flying-capacitor voltage and the load current. In order to remove the overlapping of the level layers, the optimization of the line-to-line voltage waveform is proposed to synthesize the reference vector with the “nearest three-vector” approach. The theory is supported by the experimental results from the prototype. [ABSTRACT FROM AUTHOR]

AC-fed railway traction drives suffer from pulsating input power because of the single-phase pulse width modulation rectifier at the front end. An LC filter is often needed at the dc link to absorb the pulsating power. However, this greatly reduces the power density. An effective way to get rid of this clumsy filter is to compensate pulse width calculation of the traction inverter so that it does not produce harmful subharmonics (beat components) in the output voltage/current even with a fluctuating dc link. For limited switching frequency at high power level, it is difficult for conventional feed-forward compensation methods to achieve good results. A repetitive dc link voltage predictor is proposed in this paper to improve the compensation performance. It capitalizes on the repetitiveness of the dc link ripple and can predict the average value of the dc link voltage in the next switching period. An area-equalization-based algorithm is then used to calculate the required pulse width. Experiments show that compared with conventional methods, the proposed one can reduce the steady-state beat current by six to seven times. The dynamic beat current during load transients is also negligible when dynamic drop of the dc link voltage is kept below 10%. [ABSTRACT FROM AUTHOR]

The novel multilevel circuit topologies are proposed in this paper. They are called multilevel circuit topologies based on switched-capacitor and diode-clamped converters (MCT-BSD). The topology structure and the operation principle, including the working states’ transitions of the diode-clamped part, the voltages balancing mechanism of the dc link capacitors, and the pulse width modulated carrier control strategy are given. The switched-capacitor circuits contribute not only to balancing the voltages of capacitors but also to boosting the output voltage with a certain input dc voltage. The validity of the MCT-BSD is verified by simulations and experiments. The results show that balancing the voltages of capacitors, boosting the output voltages, and operating under the three-phase condition are all realized effectively in the MCT-BSD. The simulations also show the generalization of the MCT-BSD for n-level topologies. [ABSTRACT FROM AUTHOR]

This paper demonstrates improved performance of a three-phase voltage source inverter (VSI) when digital multisampled space vector modulation is used. The modulator and the inverter controller are implemented entirely using a field-programmable gate array platform, thus achieving increased bandwidth with respect to a typical digital signal processor or microprocessor-based controller. Increased controller bandwidth results in lower output voltage harmonic distortion in the frequency range above the fundamental and below the switching frequency. Experimental validation is presented together with the analysis carried out using a state space model of a VSI with an output LC filter. [ABSTRACT FROM AUTHOR]

Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]

This paper presents a three-stage 18-level inverter design with a novel control method. The inverter consists of a series-connected main high-voltage, medium-voltage, and low-voltage stages. The high-voltage stage is made of a three-phase, six-switch conventional inverter. The medium- and low-voltage stages are made of three-level inverters constructed by H-bridge units. The proposed control strategy assumes a reference-input voltage vector and aims to operate the inverter in one state per sampling time to produce the nearest vector to that reference. The control concept is based on representing the reference voltage in 60^\circ-spaced two-axis coordinate system. In this system, the inverter vectors’ dimensions are integer multiples of the inverter's dc voltage, and the expression of the inverter's vectors in terms of its switching variables is straightforward. Consequently, the switching signals can be obtained by simple fixed-point calculations. The approach of the proposed control strategy has been presented, the transformed inverter vectors and their relation to the switching variables have been defined, and the implementation process has been described. The test results verify the effectiveness of the proposed strategy in terms of computational efficiency as well as the capability of the inverter to produce very low distorted voltage with low-switching losses. [ABSTRACT FROM PUBLISHER]