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The series configuration of fast semiconductor switches seems to be the key component in the high-voltage and fast rising time pulse generation. In this approach, two important issues must be considered. The first is to provide a safe operating condition for the switches in transient intervals. The second is to design a gate drive system with the capability of driving a large number of discrete devices simultaneously. The aim of this paper is to obviate these two requirements. First, different factors affecting the unbalanced voltage sharing between the series switches are discussed. In this investigation, the switch-to-ground parasitic capacitance effect has been recognized as the major effect on the unbalanced voltage sharing in the transient interval. Two schemes for abating this effect are proposed. To solve the unbalanced voltage distribution, the structure with a snubber circuit in the clamp mode operation is suggested. This scheme can be used for any number of switches without destructively affecting their behavior. In addition, the output pulse with a fast rising time could be obtained by the proposed gate drive system. In order to evaluate the operation of the proposed structure, a stacked switch with the voltage capability of 36 kV is tested experimentally. The characteristics of the obtained pulse are the fast rising time (69.5 ns) with the dV/dt of 460 kv/ \mu \texts and the wide range of the pulsewidth adjusting to 0.5–15 \mu \texts . In addition, the voltage variance of the switches level in the series structure is about 10%. [ABSTRACT FROM AUTHOR]

This paper details the experimental evaluation and simulation of a 4-kV n-type gate turn-OFF thyristor (GTO) designed for pulsed power applications. The primary criteria of evaluation are rate of current rise ( dI/dt ), turn-ON delay time ( T_{D}) , and resistance of the device during turn-ON transients [ R_{\mathrm{\scriptscriptstyle ON}}(t)$ ]. The device under test (DuT) is an n-type asymmetric-blocking GTO manufactured by Silicon Power (Part No. 14N40A10) with a rated dc blocking voltage of 4 kV. A test circuit was specifically designed to minimize stray inductance in order to capitalize on the dI/dt$ capabilities of the DuT. Experimental data collected from resistance measurements are used to develop a single-switch approximate model for use in simulation. The results of dI/dt$ experiments provide a profile of DuT dI/dt$ operation beyond rated values; specifically dI/dt were readily achieved. The turn-ON delay time of the DuT is also characterized and determined to be $\sim 225$ ns on average. [ABSTRACT FROM AUTHOR]

It is difficult to design a standard gate driver for optimal switching control of a static induction thyristor (SI-Thy) because of its unique internal structure and the direct commutation switching characteristic between the gate and cathode terminals during the transient turn-on and turn-off switching phases. Therefore, it is important to develop a simple and effective gate driver for achieving optimal fast turn-on and stable switching operations in an SI-Thy under hard-switching conditions. To achieve faster turn-on switching time with shorter gate delay time, impedance matching between the SI-Thy and the turn-on driving circuit component in the gate driver can be realized with additional circuit modification through this paper. To ensure higher stabilities in the turn-off switching phase, forced commutation techniques and additional auxiliary circuits in the gate driver have been devised to suppress the latchup and to eliminate potential ringing possibility. We have demonstrated that our designed and tested gate driver for realizing optimal switching characteristics of an SI-Thy is effective, particularly in the gate driving circuits for various pulsed-power switching applications. [ABSTRACT FROM PUBLISHER]