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This paper presents a pulse width modulation strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15-kW motor drive prototype to validate the method effectiveness. Taking into account deadtime compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range. [ABSTRACT FROM AUTHOR]

A nonlinear pulse width modulation-controlled single-phase boost mode photovoltaic grid-connected inverter with limited storage inductance current is proposed in this paper. The circuit topology, control strategy, steady-state principle characteristic, and design criterion for the key circuit parameters of this kind of inverter are investigated in depth, and important conclusions are obtained. The inverter's regenerating energy duty ratio 1–D which decreases with the decline of the grid-connected voltage is real time adapted by sampling and feeding back the inverting bridge modulation current, and the average value of the modulation current in each switching cycle tracks the reference sinusoidal signal to get high-quality grid-connected current. The active control of the energy storage inductance current and the balance of the voltage step-up ratio are realized by adding a bypass switch connected in parallel with the energy storage inductance and using two kinds of switching pattern namely boost pattern and freewheeling pattern. The theoretical analysis and experimental results of the 1 kVA 110 VDC/220 V50 Hz photovoltaic grid-connected inverter prototype show that it has the advantages such as single-stage boost conversion, high conversion efficiency, high quality of grid-connected current waveform, low value of energy storage inductance, simple control, etc. [ABSTRACT FROM AUTHOR]

This paper investigates a control method to significantly reduce the low-frequency current oscillation for six-step operation of a three-phase inverter. The six-step operation of an ac electric machine drive system under high speeds has a few advantages compared with pulse width modulation (PWM) operation including reduced switching losses, a better utilization of the dc bus voltage, and an enhanced speed capability. In digital implementation of the six-step control, power electronics may not be able to switch on and off exactly at the zero crossing points of reference voltages, which will result in a dc offset in phase voltages and cause a low-frequency oscillation in phase currents. The low-frequency oscillation will create issues such as higher power losses, lower efficiency, and excessive heat that may demagnetize magnets on the rotor for a permanent magnet synchronous machine. This research presents a control algorithm using asymmetric PWM to ensure that power electronics switch on and off exactly at the reference voltage zero crossing points. Both simulation and experimental results demonstrate the algorithm can reduce the low-frequency oscillation in phase currents by more than 90%. [ABSTRACT FROM AUTHOR]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

This paper presents a new high-frequency modulation method for multilevel converters. The proposed method provides a broad linear operating range and can be digitally implemented with minimal computational effort. This modulation method creates a phase voltage composed of a rectangular component superimposed on the top of a quasi-square-shaped reference function. The reference functions are defined such that the utilization of the dc-link voltage is maximized in any modulation index, while the dv/dt of the switches is always the minimum possible value. In order to implement the proposed method, an update time that is much shorter than the fundamental period is defined in the algorithm for updating the rectangular components of the reference voltage. The high-frequency rectangular component can then be imposed on the reference function to generate the final switching function by switching between two voltage levels during the time between two update instances. Several experimental results are provided to evaluate the performance of the proposed method and to compare its operation to conventional methods. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

Parallel three-level T-type inverters (3LT2Is) can effectively increase the power rating. However, when multiple 3LT2Is are connected to a single dc bus, the zero-sequence circulating current (ZSCC) will occur. The ZSCC will distort the output currents and increase the system loss. To overcome this drawback, this paper proposes a novel deadbeat control scheme for the ZSCC suppression. A generalized model for analyzing ZSCC in parallel 3LT2 Is is developed for designing the deadbeat control method. The proposed deadbeat control scheme is realized by real time adjusting the dwell time of small vectors in each space vector modulation. Compared to the conventional PI control method, the influence of different sector is eliminated, thus, improving the output current waveform and reducing the ZSCC. The effectiveness of the proposed method is verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

In grid-connected inverters, a feedforward controller accurately compensates for a large number of the harmonic components of the injected current. This controller is fast and directly tackles the grid dynamic voltage disturbances without doing any further harmonic analysis. A feedforward controller was introduced to a three-phase grid connection with a wye configuration; however, for the widespread delta connections, such a scheme is less established. Moreover, the nonsinusoidal profile of the grid voltage waveform makes the online conversion of line-to-line values into phase values impossible. In this paper, implicit zero-sequence discontinuous pulse width modulation (IZDPWM) based feedforward control is implemented on the two-level grid-connected inverter. Regardless of the grid topology, the IZDPWM-based controller ensures sinusoidal current injection to the grid under balanced, unbalanced, and distorted conditions. [ABSTRACT FROM PUBLISHER]

Common-mode voltage (CMV) in voltage-source inverters (VSIs) has been well defined and is frequently referred to in the literature. While often referred to, there is no real consistency with respect to how the CMV properties of an individual modulation scheme are evaluated, lacking tools to assess the relative merits or disadvantages of a certain topology or modification of a control scheme. The way that it is analyzed is still mostly a matter of the different authors' foci. In this paper, we propose a metric for the analysis of the CMV, aiming to fill the aforementioned gap. Thereby, the CMV in VSIs is quantified by the number of possible levels and the step sizes between different levels, as well as the respective frequencies of occurrence. The first two are given by the number of levels and the number of phases of the inverter. Depending on the modulation (control) schemes, all possibly available levels or a few of these levels are present in the CMV. We illustrate the use of the tool by applying it to thoroughly study the CMV properties intrinsic to the topologies of multilevel multiphase single- as well as double-ended diode-clamped VSI drive systems. As part of this analysis, we uncover new relationships concerning the existence of zero CMV level. Furthermore, we exemplarily apply the developed tool to the assessment of the CMV properties of selected pulse width modulation (PWM) control schemes and translate the findings into an interpretation of the endangerment of a given drive to suffer damage from inverter-induced bearing currents. The theoretical findings are supported by measurements. This paper also reviews the literature on CMV in multilevel multiphase VSI systems. With the proposed metric in mind, the CMV being mostly discussed as an element of different foci becomes even clearer, confirming again the need for the development of such a tool. [ABSTRACT FROM AUTHOR]

Cascaded converters are adopted in many power systems to manage sources and loads at different voltage levels simultaneously. DC bus capacitor is one of the key components in these converters due to its energy storage and fast response capabilities. However, the ripple current through the capacitor will influence its lifetime and the overall efficiency of the converter. Previous studies showed that the capacitor current of ac systems is optimized when the duty cycles are synchronized under in phase or antiphase condition. In this paper, the bus capacitor ripple current of cascaded two-stage converters for dc systems with different combinations of duty cycles is analyzed. It is found that the optimum capacitor current ripple varies depending on the values of individual duty cycles and the phase-shift angle between them. By properly adjusting the phase shift, the capacitor RMS current value can be reduced without affecting the converter normal operation or the need for extra sensing circuits, hence improving the energy conversion efficiency and prolonging the capacitor lifetime with relatively simple implementation. To illustrate, a case study of a two-stage dc/dc converter is carried out. A laboratory prototype converter confirmed a maximum efficiency improvement of 2.8% if the phase shift is adjusted properly when compared to the same converter with the worst case phase-shift angle. [ABSTRACT FROM AUTHOR]

Multilevel active neutral-point-clamped (ANPC) converter is popularly known for its higher medium voltage drives up to 6.9 kV. However, common-mode voltages (CMV) are generated when using the well-established carrier-based pulse width modulation (PWM) modulation technique. As a result, CMV will become the major cause of the premature bearing failures and the conducted electromagnetic interferences. In this paper, a reduced CMV strategy is proposed for the ANPC which employs an alternatively new hybrid carrier-based modulation named as interleaved sawtooth carrier phase-disposition PWM (ISC-PD-PWM). By doing so, enhanced harmonic profile is achieved as compared to the typically used classical phase-shifted carrier PWM (PSC-PWM). Therefore, a comparative evaluation of the seven-level (7L) ANPC performance using the proposed reduced CMV approach is made between the novel hybrid ISC-PD-PWM and the conventional PSC-PWM in terms of harmonic analysis. The experimental results have proven the feasibility of the proposed concepts with the CMV effectively reduced. Such perceived merits make ANPC be more attractive for its motor drives. [ABSTRACT FROM AUTHOR]

This paper introduces a combination of two proposed efficiency improvement techniques for a microinverter with current mode control zero-voltage switching output stages. The first technique is dynamic dead-time optimization wherein pulse width modulation dead times are dynamically adjusted as a function of load current. The second method is advanced phase skipping control which maximizes inverter efficiency by controlling power on individual phases depending on the available input power from the photovoltaic source. Neither of the techniques requires any additional circuit components and both can be easily implemented in digital controller firmware. The two techniques were designed and implemented in a 400-W three-phase microinverter prototype. The experimental results validate the theoretical analysis of these techniques and demonstrate that a significant efficiency improvement can be achieved by combining the two proposed control techniques. [ABSTRACT FROM AUTHOR]

This paper proposes a new three-phase modular multilevel inverter (MMLI). The proposed inverter consists of repeated modular primary cells that are connected in series configuration. Therefore, the proposed topology can be extended to get more output voltage levels by adding additional cells without increasing voltage stresses across power switches. Both sinusoidal pulsewidth modulation (SPWM) and staircase modulation are successfully applied to the proposed inverter. The proposed inverter features many advantages such as reduced number of semiconductor power switches, driver circuits, dc-voltage sources, simplified control algorithm, and reduced voltage stresses across the switches independent of output voltage level. Furthermore, the performance of the proposed inverter is studied under both open-loop and closed-loop operations for highly inductive load. Beside the obtained simulation results, a laboratory prototype has been carried out and tested to verify the control techniques and performances of the topology. Simulation and experimental results are compared together to highlight the similarity and consistence of them. [ABSTRACT FROM AUTHOR]

Compensation of nonlinear effects generated by dead-time and semiconductors voltage drop has been widely studied in the literature about two-level converters. This paper takes a closer look at those analyses for multilevel converters, specifically for a cascaded H-bridge (CHB) converter modulated with phase-shifted pulse width modulation. The interaction between the cells is analyzed for a generic $n$ -cell converter, from which a general expression for the distortion generated by the nonlinearities has been obtained. Based on this expression, a compensation signal for the overall converter is calculated on each sample time, which is a fraction of the triangular carrier used to modulate each cell, thus significantly improving the quality of the output voltage signals. Experimental validation of the proposed compensation method is presented using a three-phase four-cell CHB converter prototype of 5.5 kW. [ABSTRACT FROM AUTHOR]

This paper identifies the characteristics of a current source inverter operating in discontinuous conduction mode, and proposes a new multiobjective pulse-width modulation (PWM) method to mitigate voltage boosting and harmonic distortion effects. The method takes into account load impedance effects. Controls are also developed to enable transition between the multiobjective PWM method and conventional PWM as the current source inverter operates in discontinuous and continuous modes of operation. The concept is verified experimentally on a 3 kW test bed. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) control of multilevel inverters (MLIs) is very popular. However, it gets extremely challenging with the increase in the number of output voltage levels due to the emergence of subtriangles in the various sectors of the hexagon, which results in increased computational complexity and storage requirements of switching states and corresponding pulse durations. Currently, this is handled through laborios offline computations in conjunction with the visual inspection of the space vector hexagon and its various sectors. This paper aims to simplify the implementation of the SVM scheme for an n-level MLI by proposing generalized equations that not only facilitate direct online computation of control pulses and obviate the requirement of lookup tables but also result in optimized switching. Yet, the on-time computations of the various MLI switches are still based on simple two-dimensional Cartesian co-ordinate system combined with the basic two-level inverter implementation. The proposed scheme makes use of a unique l-factor approach, which directly identifies the location of the various subtriangles in the space vector hexagon and leads to direct online computations of the control pulses. The proposed scheme is validated by simulations and experimental results for three- and five-level diode clamped MLI. [ABSTRACT FROM AUTHOR]

In high-power traction drive systems, the switching frequency of the inverter is strictly limited owing to the restrictions on switching losses and cooling conditions. In this case, the multimode modulation strategy is usually adopted. Based on the analysis of a modified 24-sector space vector pulse width modulation (SVPWM) technique, several synchronous modulation strategies with different pulse numbers are proposed in this paper, which can be applied to the two-level six-phase voltage-inverter-fed asymmetrical dual-stator induction machines. By comparing the harmonic performance of the synchronized modulations, the authors present a set of multimode SVPWM strategy, which is suitable for the high-power traction drive systems under low switching frequency. At the same time, the switching strategy for transitions between different modulation modes is proposed as well. Simulation and experimental results verify the validity and effectiveness of the proposed synchronized modulation strategies and the switching strategy between different modulation modes. [ABSTRACT FROM AUTHOR]

A new single-phase \uppi-\texttype 5-level inverter using 3-terminal switch-network (3TSN) is proposed in this paper. The topology is considered as a variant of T-type 3-level structure or dual-buck inverter with coupled inductors. This new inverter is suitable for multilevel power inversion with low dc-bus voltage. The merit of the proposed topology is to apply only four active power switches to achieve 5-level operation. Other benefits include double frequency operation of output inductor and equal division of the current that flows through power switches and filter inductor. Hence, it leads to high efficiency and low harmonics. These characteristics allow improvement of losses distribution and volume reduction of output filter inductor. The operation scenario with sinusoidal pulsewidth modulation (SPWM) is described in details. Meanwhile, the magnetic analysis and design are studied and discussed. Finally, a prototype is built to verify the theoretical analysis and demonstrate the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents the design process of a 6-kVA quasi-Z-source inverter built with SiC power devices, in particular, employing SiC MOSFETs and SiC Schottky diodes. The main design target is to find the optimal parameters and a good agreement between the efficiency and power density of the converter. The performance of the system may be influenced not only by the switching frequency but also from the specific pulsewidth modulated (PWM) method or type of SiC MOSFET, and, therefore, various design cases are analyzed. At a final step, the 6 kVA/3 × 400 VAC inverter employing the 80 mΩ SiC MOSFETs and operating at 100 kHz with the minimum switching number method is chosen for investigation and a laboratory prototype is built. From experiments, the high performance of the designed system is confirmed. More specifically, it is shown that an efficiency above 95.6% (at 400 VDC, B = 1.9) and a power density higher than 2 kW/dm3 have been reached. Last but not least, the obtained results, which can be recognized as leading in the area of impedance source converters, show the great benefits gained by employing the new power semiconductor devices. [ABSTRACT FROM PUBLISHER]

Two new configurations of static ground power unit based on 5L active neutral point clamped (ANPC) and novel modular 9L-ANPC converter are proposed. First, a new level shifted phase-shifted carrier pulse-width modulation (LS-PSC-PWM) switching method for the 5L-ANPC converter is defined. By utilizing the proposed method, total harmonic distortion of output voltage is reduced in comparison with traditional PSC-PWM switching method. Then, a novel modular 9L-ANPC multilevel converter and its suggested modulation method is proposed in this paper. In comparison with traditional 9L-ANPC converter, the main advantages of proposed modular 9L-ANPC converter are halving the applied voltages on flying capacitors (FC), reduced number of FCs, and self-balancing of FCs, which is provided by suggested switching method. This results in reduction of the size and cost of converter, and makes it more feasible and reliable. Furthermore, inductance reduction of output LC filter enhances static ground power unit dynamic performances. The simulation and experimental results verified the feasibility and performance of proposed converters. [ABSTRACT FROM PUBLISHER]

Pulse-width modulation (PWM) of a motor drive at a fixed switching frequency leads to harmonic currents in narrow bands around integral multiples of the switching frequency resulting in tonal frequency acoustic noise components, which are irritating to the human ear. Random variation of carrier frequency to spread the spectrum poses challenges in device loss calculation, thermal design, and closed-loop controller design. Random pulse positioning is not quite effective at high speeds of the drive, where the problem of acoustic noise is most pronounced. This paper proposes a simple variable-frequency PWM and evaluates the performance of the same experimentally on a 6-kW induction motor drive. The experimental results show that the acoustic noise is spread uniformly over a range of frequencies without introducing low-frequency current harmonics. Compared with fixed-frequency PWM, the dominant acoustic noise is reduced significantly over a wide range of speeds. The variable-frequency PWM is further shown to reduce line current total harmonic distortion at high speeds of the drive. The computational effort required by the variable-frequency PWM is only marginally higher than that required by fixed-frequency PWM. [ABSTRACT FROM PUBLISHER]

The device switching frequency of current source converters (CSCs) in high-power medium-voltage (MV) drive applications is normally around 500 Hz. Conventional space vector modulation (SVM) features fast dynamic response but its output contains low-order harmonics with high magnitudes. In this paper, a natural-sampling-based SVM (NS-SVM) scheme is proposed to substantially suppress the low-order harmonics in practical CSC-based drives. This study proposes an equivalent discretization of NS-SVM wherein natural sampling pulse width modulation performance can be achieved with regular sampling frequency (same as a conventional SVM) instead of a high or even infinite sampling frequency. Equations for natural-sampling-based dwell time calculations for each selected vector are developed. The corresponding simplified but precise enough equations are derived on the basis of the Newton–Raphson algorithm to achieve fast online digital implementation. The proposed NS-SVM features superior low-order harmonic performance and inherits the high dynamic response and low sampling frequency of conventional SVM. Simulations and experiments are provided to verify the proposed NS-SVM scheme. [ABSTRACT FROM AUTHOR]

This paper presents a generalized algorithm to eliminate spikes of common-mode voltages (CMV) caused by dead-time effect for common-mode voltage reduction pulse width modulation (CMVRPWM). The characteristics of the CMV spikes for the popular CMVRPWM strategies (AZSPWM1, NSPWM, CRLO-CMVRPWM, and SLO-CMVRPWM) are studied and compared by analyzing the extreme switch pulse patterns. The proposed CMV spikes elimination method directly adjusts the injected zero-sequence voltages instead of the durations of the adopted voltage space vectors to avoid the overlaps of the adjacent dead time periods. The CMV spikes can be eliminated regardless of the output voltages in the dead time periods; thus, the signs of phase currents are not needed to detect and overcome the problem caused by the resolution of the current sensors when the phase currents approach to zero. In addition, an effective method by online selecting low or high active pulses for the three legs is proposed to ensure that at most one leg switches between adjacent carrier periods. The proposed method is generalized and effective for all the CMVRPWM with symmetrical switch pulse patterns and no simultaneous switching problem. The simulation and experimental results validate the effectiveness. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped (4L-HC) inverter is a newly proposed topology which is suitable for high-performance medium-voltage drives. Each phase of this topology consists of eight switches and a flying capacitor and the dc-link is split into three parts by two neutral points. In order to ensure the topology operating properly, the voltages across the flying capacitors and three dc-link capacitors should be controlled and maintain balanced at their nominal values. This paper presents a decoupled voltage balancing method for this 4L-HC inverter, including the voltage balancing of dc-link capacitors and flying capacitors. A modified phase-shifted pulse-width modulation method is used to regulate the voltages of flying capacitors and the central dc-link capacitor. The relationship between the neutral-point currents and the output voltage is studied and the upper and lower dc-link capacitor voltages are balanced by injecting an optimum zero-sequence voltage. Simulation and experimental results are presented to verify the validity of this method. [ABSTRACT FROM AUTHOR]

The paper presents an analysis on the output current ripple in zero common-mode voltage (ZCMV) PWM control of multilevel inverters. The modulation strategy for common-mode voltage (CMV) elimination in multilevel inverters is based on the “three zero common-mode vectors” principle. The space vector diagram, which consists of vectors of ZCMV, is fully explored by properly depicting the base voltage vectors and their corresponding active switching vectors. The switching patterns are limited to those of three switching states each of which is symmetrically distributed. Based on the PWM process simplified to that of a two-level inverter with three allowable switching states and the degree of freedom existing in the switching states arrangement, a novel carrier-based pulsewidth-modulated (PWM) method with optimized output current ripple is proposed. Compared to the existing PWM methods which utilize the same kind of switching patterns, the proposed PWM method has reduced considerably the rms current ripple and total harmonic distortion (THD) of the output current in a wide region of the modulation index. The effectiveness of the proposed method is validated by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents the Bee optimization method for harmonic elimination in a cascaded multilevel inverter. The main objective in selective harmonic elimination pulsewidth modulation strategy is eliminating low-order harmonics by solving nonlinear equations, while the fundamental component is satisfied. In this paper, the Bee algorithm (BA) is applied to a 7-level inverter for solving the equations. The algorithm is based on the food foraging behavior of a swarm of a honeybees and it performs a neighborhood search combined with a random search. This method has higher precision and probability of convergence than the genetic algorithm (GA). MATLAB software is used for optimization and comparison of GA and BA. Simulation results show superiority of BA over GA in attaining accurate global minima and higher convergence rate. Also, its performance in 10 times run is the same as in 1 time run. Finally, for verifying purposes, an experimental study is performed. [ABSTRACT FROM AUTHOR]

Variable-speed multiphase (more than three phases) drive systems are seen as serious contenders to the existing three-phase drives due to their distinct advantages. Supply to the multiphase drives is invariably given from a voltage source inverter. However, this paper proposes an alternative solution for supplying multiphase drive system using a direct ac–ac converter called a matrix converter. This paper proposes the pulsewidth modulation (PWM) algorithm for the matrix converter topology with three-phase grid input and five-phase variable-voltage and variable-frequency output. The PWM control technique developed and presented in this paper is based on space vector approach. This paper presents the complete space vector model of the three-to-five-phase matrix converter topology. The space vector model yield 2^15 total switching combinations which reduce to 243 states considering the imposed constraints, out of which 240 are active and 3 are zero vectors. However, for space vector PWM (SVPWM) implementation, only 90 active and 3 zero vectors can be used. The SVPWM algorithm is presented in this paper. The viability of the proposed solution is proved using analytical, simulation, and experimental approaches. [ABSTRACT FROM AUTHOR]

This paper proposes a unified PWM method for matrix converters so as to establish a common platform which can generate various types of PWM methods in real time by adjusting the free parameters in the modulation algorithm. As a foundation for unification, the general form of the modulation functions for matrix converters is derived using geometric transformation approach. All eligible direct modulation matrices are shown to be of indirect form and are expressed in terms of instantaneous phase quantities. This paper also presents a new viewpoint to consider a matrix converter as a generalized three-level inverter and to apply the double-carrier-based dipolar modulation technique of the three-level inverter to the matrix converter. Several concepts of the two-level PWM inverters are then generalized to the matrix converters for better visualization and understanding of the modulation process. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents the experimental results of the independent drive characteristics of two three-phase induction motors (IMs) fed by a four-leg inverter (FLI). The FLI is a single inverter that can drive two three-phase ac motors independently. The inverter consists of four legs and two capacitors connected in a series. The U and V phases of both motors are connected in each leg, respectively, whereas the W phase of both motors is connected in the neutral point of two-sprit capacitors. The pulsewidth modulation technique in three-phase voltage source inverter is not directly applicable for the FLI because only two phases must be modulated. Then, this paper also analyzes about the neutral point potential of two-sprit capacitors and inverter output voltage. Next, the modulation technique in the FLI is also shown. The experimental results demonstrate the characteristics of two IM independent drives and the validity of those analytic results. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

A family of isolated buck–boost dc/dc converter for wide input-voltage range is proposed in this paper, and the full-bridge (FB) boost converter, being one of the typical topologies, is analyzed. Due to the existence of the resonant inductor (including the leakage inductor), the FB-boost converter can only adopt the two-edge-modulation (TEM) scheme with the FB cell being leading-edge modulated and the boost cell being trailing-edge modulated to minimize the inductor current ripple over the input-voltage range, and a phase-shift-control-scheme-based TEM with the use of the market available controller IC such as UC3895 is proposed, which realizes phase-shifted control for the FB cell to achieve zero-voltage switching. In order to improve the reliability and efficiency of the FB-boost converter, a three-mode dual-frequency control scheme is proposed, in which the FB-boost converter operates in boost, FB-boost and FB modes in low, medium and high input voltage regions, respectively, and for which the expression of the inductor current ripple is derived in this paper. As the input voltage in the FB-boost mode is close to the output voltage, the inductor current ripple in this mode is much smaller than that in the other modes, and the switching frequency of the boost cell in this mode can be lowered to one-(2N+1)th of the preset switching frequency to reduce the switching loss, and hence, to improve the efficiency. A 250–500 V input, 360 V output, and 6 kW rated power prototype is fabricated to verify the effectiveness of the design and control method. The average efficiency over the input-voltage range is 96.5%, and the highest efficiency attained is 97.2%. [ABSTRACT FROM AUTHOR]

This paper presents theoretical, simulation, and experimental investigations of input current interharmonics in modern variable-speed drives based on voltage source inverters and diode input rectifiers that are caused by motor current imbalance. It investigates how a disturbance in the inverter dc side current created by unbalanced motor currents propagates from the inverter to the rectifier stage and appears as variable frequency interharmonic distortion in the rectifier input currents. Particular emphasis is given to theoretical analysis of the frequency transformations created by the inverter and rectifier stages and the magnification of the disturbance current caused by parallel resonance in the drive dc bus circuit. The theoretical results are confirmed by simulation and experimental results. They demonstrate that motor current imbalance can be responsible for high non-characteristic inter-harmonic distortion in the drive input currents. A calculation example outlines a procedure for estimation of the drive input current interharmonic distortion based on measurements of the motor currents. The paper should be helpful for people investigating the origin of problems caused by variable frequency interharmonic currents. [ABSTRACT FROM PUBLISHER]

AC–DC–AC converter-fed induction motor (IM) drive is mainly realized by back-to-back three-phase converters. However, fault in a single semiconductor switch will make it inoperative. To enable continued controllable operation in case of the faults occurring in the converter, the five-leg converter with a shared leg between the grid and load sides is a possible solution. However, this topology poses an inherent two-objective control problem, because its grid and load sides should be controlled simultaneously. More importantly, the potential increase of the shared-leg current may destroy the converters. In this paper, a new control scheme based on the FCS-MPC combined with intrinsic characteristic of the five-leg converter is proposed for independent control of the rectifier and inverter subsystem with the shared-leg overcurrent constraint. The condition for independent control is analyzed. In order to give a complete evaluation of the proposed control scheme, the conventional pulsewidth modulation (PWM) control scheme is conducted for comparison. Experimental results are provided to validate the effectiveness of the proposed scheme. [ABSTRACT FROM PUBLISHER]

This paper addresses theoretical calculation of a single-phase multilevel pulsewidth modulation (PWM) inverter current total harmonic distortion (THD). Analytical approach introduced in late 1980s for a two-level inverter is generalized for an arbitrary level count for a single-phase inverter. Although the obtained closed-form piecewise analytical solutions assume (infinitely) large ratio of switching and fundamental frequencies and pure inductive load, they are practically very accurate for the ratios of (apparent) switching and fundamental frequencies larger than 25–30 and inductance-dominated loads. Along with strict mathematical solutions, simple accurate Bessel function approximation and hyperbolic average trend one are suggested. The formulas clearly reveal a single-phase PWM inverter current THD dependence on modulation index for an arbitrary voltage level count and are easily modified to cover grid-connected cases. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

A four-level open-end winding induction motor (OEWIM) drive is known to suffer from two perennial problems. One is the problem of zero-sequence currentin the motor phases, which is caused by the existence of zero-sequence voltage in them. The other is the overcharging of the dc-link capacitor of theinverter operated with lower dc-link voltage by its counterpart operated with a higher dc-link voltage. This paper investigates the applicability of aspecial variant of space vector pulse width modulation (SVPWM) scheme for a recently proposed power circuit configuration, in which arectifier–inverter combination is nested within the conventional two-level inverter configuration to achieve four-level inversion. This PWM schemeis named as the sample-averaged zero-sequence elimination (SAZE) SVPWM scheme, wherein the zero sequence voltage is suppressed in each sampling timeperiod in the average sense. Both of the aforementioned problems encountered in this drive are successfully overcome for this power circuit configurationby resorting to the proposed SVPWM strategy. [ABSTRACT FROM PUBLISHER]

The converter with a single-phase rectifier, a dc-link circuit and a three-phase inverter is widely applied in high-speed railway electrical traction drive system. The fault frequency of single-phase rectifier is higher than that of three-phase inverter. Thus, this paper presents a new and fast model-based approach for open-switch fault diagnosis of the single-phase pulse width modulation rectifier, based on the mixed logical dynamic model and residual generation. It requires no additional hardware but only some measurements and command signals which are available in control system. This diagnosis method is quite suitable for electrical traction application due to the fast diagnosis time, simple structure and high reliability. Experimental results confirm the effectiveness and accuracy of the proposed algorithm. It is shown that such diagnosis method can locate the faulty switch in a few milliseconds which is important to avoid catastrophic consequences. [ABSTRACT FROM AUTHOR]

A zero-voltage switching (ZVS) grid-connected full-bridge inverter and its modulation schemes are investigated. A novel sinusoidal pulse width modulation scheme for the ZVS full-bridge inverter (ZVS SPWM) is proposed in this paper. The ZVS SPWM is evolved from the double-frequency SPWM by adding gate drive to the auxiliary switch. The ZVS condition is analyzed and the circulation loss of the resonant branch is optimized by adjusting the energy storage in the resonant inductor. The reverse recovery of the body-diode of MOSFET is relieved and ZVS is realized for both main and auxiliary switches. The filter inductors are significantly reduced with higher switching frequency. The design guideline of resonant parameters and the implementation of ZVS SPWM in DSP controller are introduced. The ZVS SPWM scheme is verified on a 3-kW inverter prototype. According to the experimental result, peak efficiency as 98.8% is achieved. [ABSTRACT FROM AUTHOR]

In this paper, two new optimized common-mode voltage reduction PWM (CMVRPWM) strategies based on solving the established constrained nonlinear programming models in the time domain are proposed and analyzed. The proposed current ripple losses-optimized CMVRPWM (CRLO-CMVRPWM) minimizes the mean-square values of the three-phase current ripples by calculating the optimized special solutions of the voltage–second balance equations under the designed switching sequences. CRLO-CMVRPWM can achieve better output waveform quality than the existing methods. The proposed switching losses-optimized CMVRPWM (SLO-CMVRPWM) online optimizes the bus-clamping styles according to the phase currents to minimize the switching losses under different load power factors. Compared to the near-state PWM with fixed bus-clamping styles, SLO-CMVRPWM can reduce more switching losses in broader range of the modulation index. Simulation and experimental results verify the superiority of the proposed strategies to the conventional ones. [ABSTRACT FROM PUBLISHER]

This paper proposes three dynamic voltage restorer (DVR) topologies. Such configurations are able to compensate voltage sags/swells in three-phase four-wire (3P4W) systems under balanced and unbalanced conditions. The proposed systems use two independent dc links. Proposed configurations present advantages in terms of switch blocking voltages and consequently lower dc-link voltage rating. The complete control system, including the pulsewidth modulation (PWM) technique, is developed, and comparisons between the proposed configurations and a conventional one are performed. Simulation and experimental results are provided to validate the theoretical approach. [ABSTRACT FROM AUTHOR]

Constant-volts-per-hertz induction motor drives and vector-controlled induction motor drives utilize pulsewidth modulation (PWM) to control the voltage applied on the motor. The method of PWM influences the pulsations in the torque developed by the motor. A space-vector-based approach to PWM facilitates special switching sequences involving the division of active state time. This paper proposes a space-vector-based hybrid PWM technique, which is a combination of the conventional and special switching sequences. The proposed hybrid PWM technique results in a lower peak-to-peak torque ripple than conventional space vector PWM (CSVPWM) at high speeds of an induction motor drive. Furthermore, the magnitude of the dominant torque harmonic due to the proposed hybrid PWM is significantly lower than that due to CSVPWM at high speeds of the drive. Experimental results from a 3.75-kW sensorless vector-controlled induction motor drive under various load conditions are presented to support analytical and simulation results. [ABSTRACT FROM AUTHOR]

In an electric drive vehicle (EDV), the available voltage on a dc-link is limited, and so the inverter output voltage and, consequently, the line motor maximum speed are limited. The fundamental voltage of the inverter output is increased approximately 27% using a square wave (SW) switching pattern instead of a sine wave switching pattern. However, this pattern can only be used at high speeds, and at lower speeds a pulsewidth modulation (PWM) pattern should be used. In order to achieve proper control, the switching pattern should be changed seamlessly. In the present paper, a new PWM scheme for single-mode seamless control of Vernier motors is proposed. In the proposed scheme, the reference voltage is modified to change the switching pattern continuously so that the voltage changes smoothly from a high-frequency pattern to an SW and voltage discontinuity does not occur. Experimental results reveal that the inverter-switching pattern changes smoothly from a sinusoidal PWM pattern to an SW pattern, and so seamless control from the constant-torque region to the constant-power region, and vice versa, is achieved. Since the proposed scheme is a single-mode control, it is much simpler than current technologies, which are based on multimode controllers. Also the proposed method has a lower total harmonic disturbance (THD) as well as a lower harmonic distortion factor (HDF) compared to some existing methods. [ABSTRACT FROM PUBLISHER]

Multilevel inverters are gaining more attention in ac drive application due to their many attractive features. In the case of conventional neutral-point-clamped (NPC) or flying capacitor multilevel inverter configurations, active switches are connected in series to produce multilevel output voltage waveform. Therefore, if any one switch fails, the entire configuration has to be shut down; this will reduce the reliability of the system. A dual three-level inverter configuration for induction motor drive is proposed in this paper to improve reliability of the system. This topology is developed by feeding four-pole induction motor stator winding with four conventional two-level inverter modules. A level-shifted carrier-based third harmonic injection pulsewidth-modulation technique is used to produce the gating signals for the proposed configuration. By providing proper phase shift between carrier waves, multilevel voltage waveform is produced across the total motor phase winding, and first center band harmonics are also canceled. Thereby, the torque ripple will be considerably reduced compared with conventional NPC five-level inverter-driven induction motor drive. Finite-element analysis (FEA) is used to estimate the torque ripple when induction motor is supplied by the proposed configuration and conventional five-level NPC inverter configuration to show the effectiveness of the proposed converter. The proposed configuration is simulated using MATLAB/Simulink and experimentally verified using a laboratory prototype with a 5-hp four-pole induction motor drive. [ABSTRACT FROM PUBLISHER]

This paper proposes a new five-level voltage source inverter for medium-voltage high-power applications. The proposed inverter is based on the upgrade of a four-level nested neutral-point clamped converter. This inverter can operate over a wide range of voltages without the need for connecting power semiconductor in series, has high-quality output voltage and fewer components compared to other classic five-level topologies. The features and operation of the proposed converter are studied and a simple sinusoidal PWM scheme is developed to control and balance the flying capacitors to their desired values. The performance of the proposed converter is evaluated by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, three control schemes with variable switching frequencies are proposed and analyzed for the paralleled voltage source inverters (VSIs) fed permanent magnet synchronous motor (PMSM) drive. The proposed schemes could be applied in the low-speed operation region of high-power drive system, where the frequency modulation index is high. First, the field-oriented control (FOC) with phase-shifted chaotic space vector modulation (SVM) under synchronous frame and the FOC with phase-shifted chaotic sinusoidal pulse width modulation under stationary frame is proposed for the paralleled VSIs fed PMSM drive. The proposed phase-shifted chaotic PWM schemes not only eliminate specific switching harmonics completely but also suppress all remaining switching harmonic peaks in the spectrum. The avoidance of inherent circulating current is also considered in designing these two schemes. Second, the direct torque control (DTC) for the paralleled VSIs fed PMSM drive is proposed with circulating current suppression. Besides inheriting the advantages of DTC, the output currents of paralleled VSIs are kept balanced. The working principles of these three methods are presented in detail. Experimental results on a laboratory prototype are given to verify the validity of the three proposed control schemes for the paralleled VSIs fed PMSM with variable switching frequencies. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]