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This paper proposes a two-stage energy management scheme (EMS) for AC–DC hybrid smart distribution systems (DSs). The proposed EMS is formulated as a multi-objective optimization problem to minimize the DS operation costs and energy losses. The proposed EMS is achieved in two stages. In the first stage, a network reconfiguration algorithm determines the optimal day-ahead reconfiguration schedule for a hybrid DS. In the second stage, a real-time optimal power flow algorithm determines the real-time operational schedule of the energy resources. This paper also introduces a new linearized power flow model for AC–DC hybrid DSs. This new model facilitates the formulation of the first-stage algorithm as a mixed-integer linear programming problem and the formulation of the second-stage algorithm as a linear programming problem. The proposed two-stage EMS was tested on a case study of a hybrid DS that included different types of loads and distributed generators. The results demonstrate the efficacy of the proposed EMS: the optimal day-ahead reconfiguration schedule was successfully obtained in the first stage, and the proper and optimal real-time operation was achieved in the second stage. [ABSTRACT FROM AUTHOR]

The measurement of fast voltage and current transients of Silicon Carbide (SiC) devices requires high bandwidth (BW) probes. Commercially available voltage and current probes can be expensive, and, in addition, the delay introduced by them must be compensated to achieve a proper time alignment (de-skew). Determining this de-skewing value is not a trivial task. In this paper, a simple and affordable measurement method is presented for the simultaneous measurement of the voltage and current transients of SiC devices. The voltage is measured by means of a high BW RC attenuator, while the current is estimated from the voltage drop in the stray inductance of the switching loop. Since both voltages are measured with two equal and matched high BW passive voltage probes, there is no need to apply any de-skew. This is one of the most important advantages of the method. The presented method is experimentally evaluated and used for the estimation of energy switching losses in the tested SiC-mosfet. [ABSTRACT FROM AUTHOR]

High power pseudospark switches (PSSs) can control pulsed high voltage, high peak current discharges. In this paper, a PSS in series with a saturable inductor at the anode is investigated. The commutation process is analyzed with a time-resolved method. And the effects of the number of magnetic cores and anode voltages on discharge characteristics are studied experimentally. At the beginning of commutation process, when the anode voltage is 10.4 kV with four magnetic cores, the inductor is unsaturated, and there is a flat plateau of the forward voltage drop after the anode voltage drops rapidly to about 200 V, at the same time the current rise rate is 2.8 kA/ $\mu \text{s}$. When the inductor is saturated, there is a voltage spike that occurs at the end of the flat plateau, and the current simultaneously rises rapidly at the rate of 6.4 kA/ $\mu \text{s}$. The current sharp rise lags behind the voltage drop of the pseudospark gap, and the electrode erosion and energy dissipation reduce significantly. When the anode voltage is 15.6 kV, the commutation losses reduce by about 30% with seven cores in series at the anode. As a result, it is evident that the discharge process will speed up if the anode voltage is higher. And the trigger delay decreases by up to 8% when the anode voltage varies from 5.2 to 15.6 kV. Finally, in order to obtain a reproducible pseudospark discharge by the use of a saturable inductor, the number of magnetic cores has to be optimized for different anode voltages. [ABSTRACT FROM AUTHOR]

To reduce current stress and improve efficiency of dual active bridge (DAB) dc–dc converters, various control schemes have been proposed in recent decades. Most control schemes for directly minimizing power losses from power loss modeling analysis and optimization aspect of the adopted converter are too difficult and complicated to implement in real-time digital microcontrollers. Thus, this paper focuses on a simple solution to reduce current stress and improve the efficiency of the adopted DAB converter. However, traditional current-stress-optimized (CSO) schemes have some drawbacks, such as inductance dependency and an additional load-current sensor. In this paper, a simple CSO scheme with a unified phase-shift (UPS) control, which can be equivalent to the existing conventional phase-shift controls, is proposed for DAB dc–dc converters to realize current stress optimization. The simple CSO scheme can overcome those drawbacks of traditional CSO schemes, gain the minimum current stress, and improve efficiency. Then, a comparison of single-phase-shift (SPS) control, simple CSO scheme with dual-phase-shift (CSO-DPS) control, simple CSO scheme with extended-phase-shift (CSO-EPS) control, and simple CSO scheme with UPS (CSO-UPS) control is analyzed in detail. Finally, experimental results verify the excellent performance of the proposed CSO-UPS control scheme and the correctness of theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

In this paper, a nonisolated two-channel light-emitting diode (LED) driver with automatic current balance and zero-voltage switching (ZVS) is presented. In this LED driver, a dc-blocking capacitor is connected with one side of the coupled inductor. Therefore, based on the ampere–second balance, a current source is generated with the average value of the positive current identical to the absolute average value of the negative current. Accordingly, the LED currents can be balanced naturally without extra active components or current sharing transformer. Consequently, the circuit components can keep at a low count. In addition, the proposed LED driver can achieve ZVS turn-on. Thus, the switching loss can be decreased. Above all, the proposed two-channel LED driver can be extended to a multichannel LED driver. In this paper, detailed theoretical analyses and experimental results are provided to verify the feasibility and effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are being developed for the grid connection of offshore wind or tidal farms. In order to reduce the construction and maintenance costs, it is desirable to reduce the weight and volume of the system. In current MMC submodule designs, the reservoir capacitor usually accounts for over 50% of the total volume and 80% of weight. This paper presents a new design concept and control principle for a submodule using the stacked switched capacitor (SSC) architecture that can significantly reduce the capacitor size in an MMC. Practical considerations for a high-voltage high-power SSC-based MMC submodule are presented in this paper, through the design of a 21-level, 40-kV (pole-pole dc), 19.1-MW, grid-connected system, and the concept is demonstrated experimenttally on a scaled-down 400-V, 12.3-Apeak laboratory prototype submodule. It is shown that with the proposed SSC architecture, the total volume of capacitors in each submodule can be reduced by more than 40% without significantly increasing the power loss. [ABSTRACT FROM AUTHOR]

Hybrid dc switches have become increasingly prominent due to their low ON-state energy loss and less arc erosion in comparison with conventional semiconductor and mechanical switches. Zero-voltage switching (ZVS) is a common method for realizing a hybrid dc switch. However, a certain amount of contact voltage rather than zero voltage is necessary for commutating the current into the semiconductor devices from the mechanical contacts, which may cause arc generation if the contact voltage exceeds the boiling voltage of the contact material. It has been found that current commutation can be accomplished without arc generation if the current is below a threshold value. It is important to determine and improve the threshold current of arc-less current commutation for suppressing arcing even under the condition of a high current load. In this paper, the effect of some parameters, including the contact diameter (10, 15, and 20 mm), separation speed (0.05–0.3 m/s), and cable inductance in the current commutation path (0.1 and $0.25~\mu \text{H}$) on the threshold current of the arc-less commutation, is investigated by using copper contacts. The results show that a larger contact diameter, slow separation speed, and small commutation cable inductance are good for the improvement of the threshold current of the arc-less commutation. A 200-A current commutation is realized without arc generation, particularly by applying a 20-mm-diameter contact, 0.05-m/s separation speed, and 0.1- $\mu \text{H}$ commutation cable inductance. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts. [ABSTRACT FROM AUTHOR]

Superconducting inductive pulsed power supplies have attracted a lot of attention due to its lower electrical loss and higher energy storage density than traditional inductors. To effectively improve charging rate and output continuous current pulses, a repetitive inductive pulsed power supply circuit topology based on high-temperature superconducting (HTS) pulsed power transformer was proposed and simulated in our previous studies. This paper aims to further study the feasibility of the repetitive inductive pulsed power supply circuit topology through experiments. A small air-core HTS pulsed power transformer and a bridge-type capacitor switching circuit were used to build the experimental platform. The experimental results show that the bridge-type capacitor switching circuit can shorten the charging time of each new cycle and the repetitive inductive pulsed power supply circuit is feasible for continuous current pulse output. [ABSTRACT FROM AUTHOR]

Hardware search engines are widely used in network routers for high-speed look up and parallel data processing. Content addressable memory (CAM) is such an engine that performs high-speed search at the expense of large energy dissipation. Match-line (ML) power dissipation is one of the critical concerns in designing low-power CAM architectures. NOR-MLs make this issue more severe due to the higher number of short-circuit discharge paths during search. In this paper, an ML control scheme is presented that enables dynamic evaluation of a match-line by effectively activating or deactivating ML sections to improve the energy efficiency. $128{\boldsymbol \times }32$ -bit memory arrays have been designed using 45-nm CMOS technology and verified at different process-voltage-temperature and frequency variations to test the improvements of performance. A search frequency of 100 MHz under 1-V supply, at 27 °C applied on the proposed CAM results 48.25%, 52.55%, and 54.80% reduction in energy per search compared to a conventional CAM, an early predict and terminate ML precharge CAM (EPTP-CAM) and an ML selective charging scheme CAM, respectively. ML partition also minimizes precharge activities between subsequent searches to reduce total precharge power in the proposed scheme. An approximate reduction of 2.5 times from conventional and EPTP schemes is observed in the precharge dissipation. Besides low search power, proposed design improves the energy-delay by 42% to 88% from compared designs. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient and robust design of content addressable memory (CAM) system. Design metrics, such as search time, power dissipation, power-delay product (PDP), and energy-delay product (EDP), of the proposed design are compared with those of previously reported CAM cell found in the literature. CAM cell presented in this paper offers $2.589\times $ improvement in search time, $2.725\times $ improvement in PDP, and $2.729\times $ improvement in EDP for mismatch 1 at 700 mV. It exhibits $2.257\times $ improvement in search time, $2.38\times $ improvement in PDP, and $2.389\times $ improvement in EDP for mismatch 0 at 700 mV. The proposed CAM cell also proves its efficiency in terms of power consumption, which is one of the most concerned design issues. It offers $1.0526\times $ improvement in power consumption for mismatch 1 and $1.054\times $ improvement in power consumption for mismatch 0. The proposed CAM cell is also analyzed to investigate the impact of tunneling magnetoresistance variations on power consumption, PDP, EDP, search time, and search-time variability. In addition, this paper also proposes an efficient match line sensing scheme for the proposed CAM cell. [ABSTRACT FROM PUBLISHER]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

Copper losses in low voltage distribution circuits are a significant proportion of total energy losses and contribute to higher customer costs and carbon emissions. These losses can be evaluated using network models with customer demand data. This paper considers the under-estimation of copper losses when the spiky characteristics of real customer demands are smoothed by arithmetic mean averaging. This is investigated through simulation and by analysis of measured data. The mean losses in cables and equipment supplying a single dwelling estimated from half-hourly data were found to have significant errors of 40%, compared to calculations using high resolution data. Similar errors were found in estimates of peak thermal loading over a half-hour period, with significant variation between results for each customer. The errors reduce as the demand is aggregated, with mean losses for a group of 22 dwellings under-estimated by 7% using half-hourly data. This paper investigates the relationship between the demand data time resolution and errors in the estimated losses. Recommendations are then provided for the time resolution to be used in future measurements and simulation studies. A linear extrapolation technique is also presented whereby errors due to the use of averaged demand data can be reduced. [ABSTRACT FROM PUBLISHER]

In this paper, various types of discontinuous space vector pulse-width modulation techniques for a three-leg voltage source inverter supplying balanced two-phase loads are proposed. The main objectives of the paper are to analyze switching loss characteristics associated with semiconductor devices and to reduce output current ripple by dealing with various types of zero space vector time in each switching sequence. Capabilities of reductions in switching losses and current ripple for both balanced and unbalanced output phase voltages at high modulation index and load power factor angle of 30° lagging are focused. The validity of the proposed techniques is verified by simulation and experimental results in terms of voltage spectrum, current waveforms, reductions in switching losses, and output current ripple at high modulation index when compared to a continuous space vector pulse-width modulation technique. [ABSTRACT FROM AUTHOR]

In this paper, a new T-type inverter topology based on multistate switching cell is proposed. The topology presents five-level voltage before the output $LC$ filter, providing high-order harmonics that are easily filtered. In this topology, the output filter ripple frequency is twice the switching frequency, therefore reducing the magnetic weight and volume. Other characteristics of the inverter are current sharing through the devices, facilitating its losses' dissipation, due to increased contact area and few involved components in the current flow path. In order to verify its feasibility, a design example, as well as experimental results, for a 5-kW prototype is presented in this paper. [ABSTRACT FROM AUTHOR]

Soft switching pulse-width modulation (PWM) dc–dc full-bridge converter with controlled rectifier on the secondary side of the high-frequency power transformer is presented in this paper. An active secondary switch, including new nondissipative passive energy recovery turn-off snubber on the secondary side and modified PWM control algorithm, provide conditions for zero-voltage and zero-current turn-on and zero-current turn-off of IGBT transistors on the primary side of the high-frequency dc–dc converter. The simple passive energy recovery snubber ensures also zero-voltage turn-off of the transistor on the secondary side of the power transformer. The principle of operation is explained and analyzed and consequently verified on a 2 kW, 50 kHz laboratory model of the converter. [ABSTRACT FROM PUBLISHER]

Switch-mode hydraulic control is a compact and theoretically efficient alternative to throttling valve control or variable displacement pump control. However, a significant source of energy loss in switch-mode circuits is due to throttling during valve transitions. Hydraulic soft switching was previously proposed as a method of reducing the throttling energy loss, by absorbing, in a small variable volume chamber, the flow that would normally be throttled across the transitioning high-speed valve. An active locking mechanism was previously proposed that overcomes the main challenge with soft switching, which is a lock mechanism that releases quickly and with precise timing. This prior work demonstrated a reduction in energy losses by 66% compared to a control circuit. In this paper, a numerical model is developed for a switch-mode virtually variable displacement pump (VVDP) circuit, utilizing the proposed soft switch. The model is then used as a means of designing a proof of concept prototype to validate the model. The prototype design includes methods for controlling the soft switch spring preload, travel distance, piston displacement required to unlock the soft switch, valve command duty cycle, switching cycle period, and load pressure. Testing demonstrated that the soft switch circuit performed as expected in a baseline condition. The operating region for this prototype was found to be quite narrow. However, the model does a good job of predicting the displacement of the soft switch. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the performance of the three-phase ac–ac matrix converter (MC) utilizing the novel superjunction (SJ) reverse-blocking (RB)-insulated gate bipolar transistor (IGBT) as switch elements for the first time. The SJ RB-IGBT offers bidirectional blocking capability >1200 V by introducing a shorted-collector trench and n2-layer. The SJ RB-IGBT exhibits bipolar conducting mode in the on-state and the unipolar mode during turn-off. Therefore, both a low on-state voltage (Von) and a low turnoff energy loss ( Eoff) can be obtained. The SJ RB-IGBT delivers the Eoff 80% lower than state-of-the-art RB-IGBTs without penalty in the Von. These merits make the SJ RB-IGBT an attractive candidate for the MC. To address the short circuit arising in commutation of the MC, the split gate is adopted for a low Miller capacitance. The power loss, efficiency, and loss distribution of the three-phase MC with the SJ RB-IGBT and other RB-IGBTs are compared by simulation and calculation. Compared with the MC using conventional nonpunch-through RB-IGBT, the MC with SJ RB-IGBT achieves 85%, 87%, and 56% reductions in the turnoff, reverse recovery, and conduction losses, respectively, yielding 56% reduction in the total loss. The low-power loss and superior dynamic performance of the SJ RB-IGBT enables the MC to operate at higher frequency and higher power density. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new capacitor degradation evaluation method aimed at failure prediction and suitable for digitally controlled switching mode power supply (SMPS) for servers. Electrolytic capacitors have one of the highest component failure rates in SMPS; therefore, we attempt to detect an equivalent series resistance degradation of the electrolytic capacitor directly from the data fetched to a digital controller of the SMPS. With a SPICE simulation and a rapid control prototyping evaluation, we confirm the degradation can be detected by the data at a transient response under a normal operation without additional circuits. Even only 10% of a load step change, which commonly occurs in SMPS for servers, causes detectable transient response degradation. [ABSTRACT FROM PUBLISHER]

This paper investigates the use of multilevel conversion in dc–dc applications that require a large voltage conversion ratio. A quantitative method that can serve as a guide to compare and design multilevel topologies for large conversion ratio applications is presented. The proposed method keeps the conduction loss and switching loss constant across the different converters and employs the passive component volume as the single performance metric. As examples, flying capacitor multilevel converters and hybrid switched-capacitor (SC) converters are compared to conventional two-level buck converters, and are shown analytically to have significantly reduced passive component size. Three converter prototypes are implemented, based on the presented methodology to experimentally validate the method as well as demonstrate the advantages of multilevel and hybrid SC converters. [ABSTRACT FROM PUBLISHER]

An isolated converter such as SEPIC has high voltage stress on the main switch due to transformer leakage inductance. To solve this issue, active or passive clamp action is necessary. The common passive solution based on an RCD snubber is simple but impractical when the value of the leakage inductance is significant. On the other hand, passive regenerative solutions generally compromise the isolation, making the search for a suitable snubber a challenge. In this paper, an effective passive regenerative snubber cell for isolated SEPIC converters operating in DCM or CCM is presented. It is intended to improve the converter efficiency by transferring the energy stored in the transformer leakage inductance to the output. The analysis is presented in detail for DCM and extended to CCM together with a practical design procedure. In order to compare with the RCD, the analysis and design of a conventional cell are presented as well. To validate the proposal and quantify its feasibility, experimental results are performed for both dissipative and regenerative snubbers on a 100 W, 100 V, input and 50 V output voltage converter operating first in DCM and later in CCM. [ABSTRACT FROM PUBLISHER]

The role of universal memory can be successfully satisfied by magnetic tunnel junctions (MTJs) where the writing mechanism is based on spin-transfer torque (STT). An improvement in the switching properties (lower switching current density maintaining the thermal stability) has been achieved in MTJs with interfacial perpendicular anisotropy (IPA) at the interface between CoFeB and MgO. In this paper, micromagnetic simulations point out the influence of IPA and saturation magnetization (M \(_{\mathbf {S}}\) ) on the properties of fast magnetization reversal achieved in 5, 10, and 20 ns. Both cases of in-plane and out-of-plane free layer are considered. In addition, the thermal effect is included for the in-plane switching at 20 ns and a complete analysis of energy dissipation during the switching is illustrated. This paper can provide useful information for the design of STT-based memories. [ABSTRACT FROM PUBLISHER]

Existing low-power test generation procedures use a single number to represent the power dissipation in a circuit or subcircuit. As a result, the specific signal transitions they create may deviate substantially from those possible during functional operation (and those the circuit is designed for). Functional broadside tests create functional operation conditions during their two functional capture cycles. Therefore, the specific signal transitions that occur during their second, fast functional capture cycles can occur during functional operation. This paper defines and studies the patterns of signal transitions under the second, fast functional capture cycles of functional broadside tests. These patterns can be used for evaluating the deviations from functional power dissipation created by low-power test sets that consist of arbitrary (functional and nonfunctional) broadside tests. They can also be used for guiding the generation of low-power test sets. The paper presents experimental results for both applications. [ABSTRACT FROM AUTHOR]

This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level. [ABSTRACT FROM PUBLISHER]

This paper proposes an active current source gate drive (ACSD) method based on voltage controlled current source(VCCS) feedback control strategy for high-power IGBTs. Unlike the common voltage source gate drive, the proposed ACSD method provides constant drive current to charge and discharge an IGBT. With a large gate drive current, high switching speed and low switching losses can be achieved in a power converter. However, a high-current/voltage overshoot occurs. To solve this problem, a feedback current proportional to the \rmdi/ \rmdt or \rmdv/ \rmdt signal is generated to the IGBT gate. Thus, direct control of the net gate drive current is produced. Then, the current/voltage overshoot is controlled with little sacrifice in switching time, and the switching losses are lower than that with the conventional gate drive method operating simply by gate resistance switchover. The operation principle and circuit implementation of the proposed ACSD method are presented. The experimental results from a 1200 V/800 A IGBT module verify the performance of the proposed method. [ABSTRACT FROM AUTHOR]

It is well known that multilevel converters can offer significant benefits in terms of harmonic performance and reduced switching losses compared to their two-level counterparts. However, for lower voltage applications the neutral-point-clamped inverter suffers from relatively large semiconductor conduction losses because the output current always flows through two switching devices. In contrast, the T-type multilevel inverter has less conduction losses because only a single outer loop switching device is required to connect the converter output to the upper and lower dc buses, albeit at the expense of increased switching losses since these outer switches must now block the full dc link voltage. Silicon carbide (SiC) mosfet devices potentially offer substantial advantage in this context with their lower switching losses, but the benefit of replacing all switching devices in a T-type inverter with SiC mosfets is not so clear-cut. This paper now explores this issue by presenting a detailed comparison of the use of Si and SiC devices for a three-level T-type inverter operating in grid-tie applications. The study uses datasheet values, switching loss measurements, and calibrated heat sink thermal measurements to precisely compare semiconductor losses for these two alternatives for a T-type inverter operating at or near unity power factor. The results show that replacing only the dc bus connection switches with SiC devices significantly reduces the semiconductor losses, allowing either the converter power level or the switching frequency to be significantly increased for the same device losses. Hence, the use of SiC mosfets for T-type inverters can be seen to be an attractive and potentially cost-effective alternative, since only two switching devices per phase leg need to be upgraded. [ABSTRACT FROM AUTHOR]

Steady-state models of the hybrid power flow controller (HPFC) for power flow and optimal power flow (OPF) studies are presented in this paper, considering the multiple control modes of the device. A strategy for control mode switching and limit handling in power flow calculations is proposed. The OPF model of the HPFC represents all the device control and physical limits as constraints in the mathematical formulation, so that the HPFC can be optimally dispatched as a part of the transmission system control assets. The power flow model is demonstrated and validated through loadability studies on a two-area benchmark test system, where the OPF model is used to determine the optimal ratings of the device based on a cost-benefit analysis. A study is also presented of the HPFC application to Ontario-Canada's grid, to address particular congestion problems in this network; an HPFC cost analysis is also shown for this system. The presented studies demonstrate the application of the proposed models for planning and operation studies, illustrating the performance, effectiveness, and feasibility of the controller to solve congestion issues in a real grid. [ABSTRACT FROM AUTHOR]

Because of the forward recovery, the performance of the diodes degrades seriously at multimegahertz, causing extremely high power loss. So, the synchronous rectification (SR) is strongly desired in the multimegahertz resonant converters. This paper proposes a self-driven level-shifted resonant gate driver (RGD) for the SR FET in a 10-MHz isolated class-Φ2 resonant converter. The proposed RGD provides precise switching timing for the SR so that the body diode conduction loss can be minimized. A control stage is introduced to the proposed RGD to block the circulating current and the low-impedance path in the driver to realize ON–OFF control of the converter with high efficiency. The proposed RGD also generates a tunable dc bias to increase the peak gate voltage and extend the conduction time with the optimal $R_{{\rm DS}({\rm on})}$ so that the average $R_{{\rm DS}({\rm on})}$ and the associated conduction loss can be reduced significantly. A 10-MHz prototype with 18-V input and 5-V/2-A output was built. At full load of 2 A, the proposed RGD improves the efficiency from 80.2% using the conventional RGD to 82% (an improvement of 1.8%). Compared to the efficiency of 77.3% using the diode rectification, the efficiency improvement is 4.7% at full load. [ABSTRACT FROM AUTHOR]

Modern multifunction systems on chip often require a high-efficiency buck converter over a wide load current range as the main power source, for which complex multimode operation with mode detection/change is a frequent compromise between efficiency and transient response. This paper proposes a novel power-loss-aware switch-on-demand modulation (PLASOM) technique based on accurate power loss modeling to switch critical components/parameters of power loss on demand: the ON/OFF status and the size of the power transistor, the dead time, and the ON/OFF status of power-hungry subcircuits. The proposed PLASOM-based converter can work as either an adaptive on-time mechanism with constant frequency or a cycle-extended adaptive ON/OFF-time mechanism with variable frequency without mode detection/change, so that the conversion efficiency and transient response can be improved. A proposed buck converter with the PLASOM technique was implemented using the TSMC 90-nm 1/3.3-V CMOS process. Experimental results show that a conversion efficiency higher than 90% was achieved over the 1–500 mA load current range, whereas the voltage variation/recovery time during the 0.1–500 mA load transient were less than 50 mV/25 μs. Performance evaluations indicate that the proposed PLASOM technique is favorable for wide load current range buck converters in terms of conversion efficiency, transient response, and voltage ripples. [ABSTRACT FROM AUTHOR]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

Multilevel converters are mainly used in medium-voltage high-power applications. Active neutral-point-clamped (ANPC) flying capacitor multicell (FCM) converter is a well-known type of multilevel converters which is commercially available in high-power medium-voltage motor drive market. Since power loss investigation can be very advantageous in the design phase of multilevel converters, this paper presents an analytical approach to calculate and investigate the conduction and switching power loss in ANPC-FCM converter. First, the RMS and average currents of insulated-gate bipolar transistors (IGBTs) and antiparallel diodes are analytically calculated by considering the associated duty cycle of each IGBT and diode, converter modulation index, load current, and load power factor. Numerical results of the derived closed-form equations to calculate the RMS and average currents of IGBTs/diodes are compared with simulation results and experimental measurements. Numerical results match the simulation results and experimental measurements which validates the derived closed-form equations. Afterward, the obtained equations for RMS and average current computations are utilized to calculate the conduction power losses in a 12.1-MVA 6.6-kV nine-level (line-to-line) ANPC-FCM multilevel converter. For this purpose, a 4.5-kV 1.2-kA IGBT module from ABB is considered as a power switch and its parameters are employed in analytical computations and simulation of the ANPC-FCM multilevel converter for conduction power loss determination. Moreover, closed-form equations are derived for analytical determination of switching power losses for ANPC-FCM converter using Kapteyn (Fourier-Bessel) series. Based on the derived closed-form equations for conduction loss and switching loss calculation, a method is presented to determine the junction temperature in IGBTs and diodes for ANPC-FCM converter. [ABSTRACT FROM AUTHOR]

High-performance buck converters are often required in modern power electronic applications. An augmented buck converter (a main buck converter with augmentation circuits) can achieve fast transient recovery and small output voltage deviation. Compared with other augmentation circuits, a resonant augmentation circuit offers potential electromagnetic interference reduction due to the relatively low $di/dt$ value and compacts the circuit through a reduced inductance for resonance. In this paper, the performance analysis of an augmented buck converter constructed with the resonant circuit are described in detail in terms of voltage-deviation band and power loss. A circuit design and control principle is also proposed for achieving the required voltage deviation for a given transient-detection delay. A 12-to-5-V converter prototype is built to verify the analysis and effectiveness of the proposed methodology. It is demonstrated that the voltage deviation is reduced from 360 to 200 mV using the proposed resonant augmentation circuits and control scheme. The efficiency study shows that the power loss varies from 0.02 to 0.72 W, when the repetition frequency of 5-to-10-A transients changes from 100 to 5 kHz. [ABSTRACT FROM AUTHOR]

A family of modulation schemes based on mathematical construction for the multimodular matrix converter (MC) with ordinary multiwindings transformer is proposed in this paper. The key to the schemes are the calculation of offset signals. A geometric method is introduced to determine the range of the offset signals. The modulation schemes could be divided in two categories based on the geometric positions of the offset signals: continuous modulation (Method I) and discontinuous modulation (Method II). The former has the advantages of ease of use and good power quality. While the later has the advantage in power losses. Additionally, both methods can achieve the maximum linear voltage transfer ratio. To obtain better output current quality, a switching pattern with specific sequence is provided. Finally, a scaled-down prototype is built to verify the correctness and effectiveness of the proposed modulation strategies. [ABSTRACT FROM AUTHOR]

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/\2)(Seff/Soff) - \0.56(Son/Soff) - \0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology. [ABSTRACT FROM AUTHOR]

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper investigates the temperature and current dependence of the dynamic performance of five types of SiC power MOSFETs at 77 K. The turn-on and turn-off lasting time and the corresponding switching energy loss are extracted from a series of double-pulse tests. The transient peak voltage of cryogenic MOSFETs is lower, but the switching time is higher than the room-temperature ones. Moreover, power-exponential functional relations with the operating currents are found in the experiments. These results obtained lay some technical bases for exploring superconducting power electronics. [ABSTRACT FROM AUTHOR]

Photovoltaic systems technological development is driven by the request for higher efficiency and safety. These concerns influence also the choice of the power converter stage. Several topologies have been proposed and many of them are available commercially. Among them, the neutral point clamped (NPC) and derived topologies offers high efficiency, low leakage current, and low EMI. However, one main disadvantage of the NPC inverter is given by an unequal distribution of the losses in the semiconductor devices, which leads to an unequal distribution of temperature that can affect lifetime. By using the active NPC (ANPC) topology, where the clamping diodes are replaced by bidirectional switches, the power losses distribution problem is alleviated. The modulation strategy is a key issue for losses distribution in this topology. In this paper, two known strategies are discussed and a new PWM strategy, namely the adjustable losses distribution is proposed for better losses distribution in the ANPC topology. Simulations and experimental results help in evaluating the modulation strategies. [ABSTRACT FROM AUTHOR]

In this paper, a new discontinuous modulation technique is presented for the operation of the modular multilevel converter (MMC). The modulation technique is based on adding a zero sequence to the original modulation signals so that the MMC arms are clamped to the upper or lower terminals of the dc-link bus. The clamping intervals are controlled according to the absolute value of the output current to minimize the switching losses of the MMC. A significant reduction in the capacitor voltage ripples is achieved, especially when operating with low modulation indices. Furthermore, a circulating current control strategy suitable for this modulation technique is also proposed. Simulation and experimental results under various operating points are reported along with evaluation and comparison results against a conventional carrier-based pulse width modulation method. [ABSTRACT FROM AUTHOR]

This paper proposes a voltage balancing method for stacked multicell converters (SMCs) based on phase-disposition pulse-width modulation (PD-PWM). In order to reduce the switching transitions of the power devices, only optimal transitions between consecutive voltage levels are used. Selection of the optimal transition sequence is performed by evaluating a cost function. Significant reductions in the switching transitions and power losses of the power devices are achieved as compared to the optimal-state voltage balancing method where nonoptimal transitions are allowed. Simulation and experimental results from a seven-level $3\times 2$ SMC verifies that the proposed PD-PWM voltage balancing method is robust under linear/nonlinear loads and transients. [ABSTRACT FROM AUTHOR]

In this paper, a new formulation for distribution system reconfiguration (DSR) is proposed for minimizing the annual energy losses considering the variability in active and reactive power demand and distributed generation (DG) profiles. A fuzzy C-means clustering algorithm is used to obtain representative centroids from annual DG and power demand profiles. The DSR study is formulated as a mixed-integer nonlinear programming optimization problem and tested on a 33-bus and an 84-bus system. The minimization is subject to the power balance, bus voltage, and distribution system radiality constraints. Using this formulation, a single optimum configuration that minimizes annual energy losses is found and shown to be different from the optimum configuration, found in previous literature, which focuses on minimizing power losses at peak or average loads. In addition, the prospective advantages of grid automation on DSR are demonstrated to provide further energy loss reduction by including the possibility of interchanging a predefined number of configurations that minimize annual energy losses. [ABSTRACT FROM AUTHOR]

Unique pitfalls in parallel three-level T-type inverters (3LT2 Is) are potential zero-sequence circulating currents (ZSCCs) which are more complex than parallel two-level inverters and can cause current discrepancy, current waveform distortion, power losses, etc. In this paper, the ZSCC paths in the parallel 3LT2Is are first presented, and an equivalent model of the ZSCCs is developed. It is seen from this model that the ZSCCs consist of conduction, switching, and hybrid components. Based on the aforementioned analysis, an original sharing neutral bus structure is proposed to eliminate the conduction ZSCCs. With regard to the switching ZSCCs composed of high-frequency and low-frequency harmonics, modified LCL filters are proposed to eliminate the former, and zero-sequence control loops are put forward to suppress the latter. Furthermore, the proposed schemes are also proven to be effective to elimination of the hybrid ZSCCs. Experimental results validate the developed models and the proposed ZSCC elimination schemes. [ABSTRACT FROM AUTHOR]

An ideal switch with hysteresis-free \(S_{\rm ideal}=0~{\rm mV/decade}\) switching is desired to keep Moore’s law alive, but has never been achieved. Classical field-effect transistors (FETs) have supported Moore’s law for 50 years, albeit with a thermodynamically limited value of subthreshold swing \(S\ge 60\) mV/decade. Alternatives, such as, tunnel FETs, impact ionization FETs, and negative capacitance FETs promise \(S <60\) mV/decade, but ideal switching is not expected, even in theory. In this paper, we propose a zero subthreshold swing FET (ZSubFET), which is similar to a classical FET with a suspended-gate and a ferroelectric gate insulator. ZSubFET exhibits ideal switching through integration of two negative capacitors (namely, a ferroelectric and an air-gap) in the gate-stack, in series with the channel capacitance. We believe that the proposed device concept should not only lower the power dissipation in an IC, but also open up new research directions for the alternative of classical-FET. [ABSTRACT FROM AUTHOR]

Programmable reversible logic is emerging as a prospective logic design style for implementation in low power, low frequency applications where minimal impact on circuit heat generation is desirable, such as mitigation of differential power analysis attacks. Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in dual-rail adiabatic logic show reduction in average and differential power, making this design methodology advantageous in applications where security is the primary design metric and operating frequency is slower, such as Smart Cards. In this paper, we present an algorithm for synthesis of adiabatic circuits in CMOS. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node, we reduce the size of the synthesized circuit. Our approach correlates the horizontal offsets in the permutation matrix with the necessary switches required for synthesis instead of using a library of equivalent functions. The synthesis results show that, on average, the proposed algorithm represents an improvement of 36% over the best known reversible designs with the optimized dual-rail cell libraries. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse. [ABSTRACT FROM PUBLISHER]

This paper presents theoretical and experimental results on the energy loss characteristics of reversely switched dynistor (RSD) under high-current conditions. Theoretical analysis was performed based on a 1-D modified model by taking account into the carrier-carrier scattering effect and auger recombination effect during the conducting process. The experimental results of energy losses in RSD at various amplitudes of high pulse current were accurately obtained using the direct current injection method. The typical experimental results show that a single RSD has a voltage drop of approximately 9 V with a pulse current of 150 kA, transferred charge of 26.5 C. The theoretical calculated voltage drop based on 1-D modified model is approximately 7.7 V under the same conditions. The theoretical results based on the 1-D modified model almost agree well with the experimental results. [ABSTRACT FROM AUTHOR]

A conventional phase-shift full-bridge (PSFB) converter with two clamp diodes and an additional resonant inductor is widely used for front-end dc/dc stage in the distributed power system. However, the hold-up-time requirement limits its operating duty ratio at normal operation. It results in conduction loss caused by circulating current. Therefore, a wide-range zero-voltage switching (ZVS) PSFB converter with reduced conduction loss caused by circulating current is proposed in this paper. The proposed converter adopts the large resonant inductance and replaces clamp diodes in the conventional PSFB converter with MOSFET switches. With these modifications, the proposed converter can achieve the ZVS operation over wide load range as well as can reduce the conduction loss caused by the circulating current. These advantages result in the improvement of whole load efficiency. The operational principle and analysis of the proposed converter are presented and verified by the 1.2-kW prototype. [ABSTRACT FROM PUBLISHER]

Compared to the traditional single-phase-shift control, dual-phase-shift (DPS) control can greatly improve the performance of the isolated bidirectional dc–dc converter (IBDC). This paper gives a detailed switching characteristic analysis of IBDC under DPS control, establishes a power loss model to predict the dissipated power for each power component, and analyzes the efficiency-optimized characteristic across the whole range. On this basis, an efficiency-optimized switching strategy is proposed and the corresponding control scheme is designed and implemented. At last, an experimental prototype was implemented to verify the feasibility of the proposed switching strategy and correctness of the theoretical analysis. The experimental results show that the proposed method can minimize the power loss and maximize the system efficiency, and these performances are particularly effective for operation conditions with high voltage conversion ratio. [ABSTRACT FROM AUTHOR]