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CRUE-CSIC (Acuerdos Transformativos 2022), This paper provides an experimental study of the single-event upset (SEU) susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) Xilinx Artix-7 FPGA under different angles of incidence. Experimental results indicating SEUs on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are presented and discussed. Shapes of multiple events (ranging from 2 to 12-bit) are also analyzed, and their dependency on the incident angle of the particle beam against the device’s surface. Possible shapes of 128 and 384-bit multiple events are also investigated, revealing a trend to follow word lines. The results of the front incident angle are compared with 14.2-MeV neutrons, demonstrating a considerable difference in the device’s sensitivity against both irradiation sources. Finally, a modeling tool called MUSCA-SEP3 is used to predict the device’s sensitivity under the same environmental conditions. The obtained experimental results will show a good agreement with the predicted ones in a very accurate way., Ministerio de Ciencia e Innovación (MICINN), Agence Nationale De La Recherche (ANR) – France, Depto. de Arquitectura de Computadores y Automática, Fac. de Informática, TRUE, pub

As part of this effort, the CC14T, cross-coupled memory cell with 14 transistor architecture has been proposed, with defence against soft errors such as single event upsets (SEUs). The CC14T cell is presented, which consists of 4 cross-coupled input-split inverters and four access transistors. The cell achieves optimum SEU tolerance owing to a feedback structure among its internal nodes. It has been implemented and analyzed under 40nm regime, and the findings demonstrate that it consumes 43.01 nW of power with supply voltage of 0.8V and takes 6.64 percent and 15.5 percent less time to write and read than a typical 6T SRAM cell. As compared to the other cell considered, the CC14T cell has a faster write access time and higher stability due to its soft error resistance.

Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic continuous signature monitoring (DCSM) technique for high reliable computer systems. The DCSM technique dynamically generates reference signatures as well as runtime ones during executing a program. The DCSM technique stores the generated signatures in a signature table, which is a small storage circuit in a microprocessor, unlike the conventional static continuous signature monitoring techniques and contributes to saving program or data memory space that stores the signatures. Our experiments showed that our DCSM technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.

© IEEE-Inst Electrical Electronics Engineers. This work was supported in part by the Spanish MCINN project TIN2013-40968-P, by the Secretaría de Educación Superior Ciencia Tecnología e Innovación del Ecuador (SENESCYT), and by the “José Castillejo” mobility grant for professors and researchers., This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported., Ministerio de Economía y Competitividad (MINECO), Secretaría de Educación Superior Ciencia Tecnología e Innovación del Ecuador (SENESCYT), Programa "José Castillejo" para movilidad de profesores, Ministerio de Educación, Cultura y Deporte (MECD), España, Depto. de Estructura de la Materia, Física Térmica y Electrónica, Depto. de Arquitectura de Computadores y Automática, Fac. de Ciencias Físicas, Fac. de Informática, TRUE, pub

This abstract presents an experimental study of the impact of using a high flux in radiation ground tests on the measured cross-section of SRAMs. Experimental results obtained with 15 MeV protons will show that using a high particle flux makes the measured cross-section increase by almost 1 order of magnitude., Ministerio de Economía y Competitividad, Depto. de Estructura de la Materia, Física Térmica y Electrónica, Depto. de Arquitectura de Computadores y Automática, Fac. de Ciencias Físicas, Fac. de Informática, TRUE, pub

“© © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”, The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used., Ministerio de Ciencia e Innovación (MICINN), Depto. de Arquitectura de Computadores y Automática, Fac. de Informática, TRUE, inpress

As part of this effort, the CC14T, cross-coupled memory cell with 14 transistor architecture has been proposed, with defence against soft errors such as single event upsets (SEUs). The CC14T cell is presented, which consists of 4 cross-coupled input-split inverters and four access transistors. The cell achieves optimum SEU tolerance owing to a feedback structure among its internal nodes. It has been implemented and analyzed under 40nm regime, and the findings demonstrate that it consumes 43.01 nW of power with supply voltage of 0.8V and takes 6.64 percent and 15.5 percent less time to write and read than a typical 6T SRAM cell. As compared to the other cell considered, the CC14T cell has a faster write access time and higher stability due to its soft error resistance.

Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic continuous signature monitoring (DCSM) technique for high reliable computer systems. The DCSM technique dynamically generates reference signatures as well as runtime ones during executing a program. The DCSM technique stores the generated signatures in a signature table, which is a small storage circuit in a microprocessor, unlike the conventional static continuous signature monitoring techniques and contributes to saving program or data memory space that stores the signatures. Our experiments showed that our DCSM technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.

Residue number system (RNS) speeds up digital signal processing systems involving dominant addition and multiplication. Addition and multiplication are accelerated further and performed with a balanced performance on one-hot coded (OHC) residue digits. However, the high complexity of the RNS reverse converter (RC) may kill the performance gain. This paper proposes a high-speed and scalable RNS-RC for both regular and one-hot RNS. For redundant RNS (RRNS), an RRNS-RC is proposed, which based on majority-voting between OHC residue digits, corrects multibit soft errors occurring in a single residue channel. With pass-transistor logic and low-power FinFETs, the proposed RCs are optimized. The simulated RRNS-RC corrected 98.5% of soft errors, while consuming 7, 6.2 and 0.4% of the system's area, leakage power and dynamic power, respectively. As compared to the leading lookup table RC in the literature, RNS-RC exhibited 10.3X, 4.4X and 1.8X savings in area, average power, and delay, respectively. © 2023 The Author(s)

Radiation hardening by design (RHBD) is traditionally performed using triple modular redundancy (TMR), a very effective technique that introduces high overheads in terms of resources and power. The reduced resolution redundancy (RRR) technique presented in this work is a new approximate error mitigation technique that uses redundant circuits with lower resolution to perform computations. In this work, we evaluate this technique under radiation using two different benchmarks implemented in field-programmable gate array (FPGA), namely, a fast Fourier transform (FFT) and an image processing algorithm for a near-infrared (NIR) detector. Experimental results from proton and neutron irradiation, and fault injection campaigns, show that the RRR hardening technique can effectively mitigate errors with reduced overheads.

In aerospace industry, Commercial-Off-The-Shelf (COTS) Static Random Access Memories (SRAMs) are a cost-effective solution for obtaining high performance at the system level, which is difficult to obtain using space qualified components. Additionally, the usage of Dynamic Voltage Scaling (DVS) is commonly used in space environments, where low power consumption is a critical issue. This paper presents an analysis of the sensitivity against Single Event Upsets (SEUs) of various COTS bulk SRAMs and Advanced Low-Power SRAMs against proton radiation when using DVS to save power. Experimental results will show a clear evidence that the sensitivity to SEUs increases when the power is lowered. 2 sets of successive technologies (130-nm, 90-nm and 65-nm bulk SRAMs; and 150-nm and 110-nm A-LPSRAMs) are evaluated against 15~MeV protons and compared with results of 14~MeV neutrons presented in a previous work. Experimental data are finally compared with analytical simulations obtained by using the MUSCA-SEP3 Monte-Carlo tool to predict the effect of DVS on the SEE sensitivity on more modern technologies in the ITRS/IRDS roadmap., Ministerio de Economía, Comercio y Empresa (España), Depto. de Estructura de la Materia, Física Térmica y Electrónica, Depto. de Arquitectura de Computadores y Automática, Fac. de Ciencias Físicas, Fac. de Informática, TRUE, pub

The paper discusses the impact of single-event effects (SEEs) induced by radiation in an advanced extensible interface (AXI) central direct memory access (CDMA) core based on 28 nm Xilinx ZYNQ-7000 FPGA. Soft errors of CDMA have been tested with an 241Am source using data transmitting between the block random-access memory (BRAM) and external memory (DDR3). Test results show that various kinds of failure emerge in CDMA in different work modes, such as polling and interrupting driven modes. The radiation-induced multi-cell upsets, up to 8-bit, have been observed and the SEEs cross-sections have been calculated. All experimental results demonstrate that CDMA is a key component leading to increasing sensitivity of resulting soft errors in the FPGA. The test methods and results can provide a reference for SEEs evaluation and protection of CDMA IP Core.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge., Peer Reviewed, Postprint (published version)

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06x/ 1.08x/ 1.36x shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03x/ 1.09x/ 1.12x/ 1.15x/ 1.17x shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33x/ 1.6x/ 2.4x higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13x/ 1.32x/ 1.37x/ 1.42x/ 1.5x higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31x/ 2.42x/ 2.55x/ 3.04x lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead. IEEE

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06x/ 1.08x/ 1.36x shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03x/ 1.09x/ 1.12x/ 1.15x/ 1.17x shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33x/ 1.6x/ 2.4x higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13x/ 1.32x/ 1.37x/ 1.42x/ 1.5x higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31x/ 2.42x/ 2.55x/ 3.04x lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead. IEEE

Register renaming is a widely used technique to remove false dependencies in contemporary superscalar microprocessors. A register alias table (RAT) is formed to hold current locations of the values that correspond to the architectural registers. Some recently designed processors take a copy of the rename table at each branch instruction, in order to recover its contents when a misspeculation occurs. In this paper first we investigate the RAT vulnerability against transient errors. Then we analyze the vulnerability of RAT checkpoints and propose two techniques for soft error detection and correction utilizing redundantly taken copies of the entries whose content is the same with the previous and/or next checkpoints. Simulation results of the spec 2006 benchmarks reveal that on the average RAT vulnerability is 25% and checkpoint vulnerability is 6%. Results also reveal that redundancy exists at sequential checkpoint copies and can be used for error detection and correction purposes. We propose techniques that exploit this redundancy and show that faults in 41% of all checkpoints and 44% of rolled-back checkpoints can be detected and errors in 33% of the rolled-back checkpoints can be corrected. Since we exploit the already available storage, proposed error detection and correction techniques can be implemented with minimal hardware overhead., This work was supported in part by the Scientific and Technological Research Council of Turkey (TUBITAK) under Grant 112E004 and in framework of COST ICT Action 1103., Scientific and Technological Research Council of Turkey (TUBITAK)Turkiye Bilimsel ve Teknolojik Arastirma Kurumu (TUBITAK) [112E004]; COST ICT Action [1103], ACM Special Interest Grp Design Automat, RAS, EDA Consortium, IEEE Council Elect Design Automat, ECSI, European Design ; Automat Assoc

Soft errors caused by cosmic rays or alpha particles emitted from the packaging material around the chips are becoming an increasingly important challenge in reliable microprocessor design. Transistor density, and die size trends show that soft errors will gain even more importance in the future. Due to their significant overheads, most redundancy schemes are employed where the penalty incurred can be hidden in the pipeline. Most contemporary processors employ a large physical register file to hold the produced results which may reside there for a long time. The register file is a critical element of a microprocessor and is needed to be protected against soft errors. In this paper we propose an SRAM bitcell design with ability to hold a redundant copy of the data and compare the copies with built-in comparators to detect a possible mismatch. Our experimental results show that the proposed design has 34% area, 7.9% power 2% delay overheads which are further reducible and can protect the register file against Silent Data Corruption (SDC). © 2012 IEEE., ASELSAN A.S.;Turkish Aerospace Industries, Inc. (TAI);The Scientific and Technological Research Council of Turkey

Register renaming is a widely used technique to remove false dependencies in contemporary superscalar microprocessors. A register alias table (RAT) is formed to hold current locations of the values that correspond to the architectural registers. Some recently designed processors take a copy of the rename table at each branch instruction, in order to recover its contents when a misspeculation occurs. In this paper first we investigate the RAT vulnerability against transient errors. Then we analyze the vulnerability of RAT checkpoints and propose two techniques for soft error detection and correction utilizing redundantly taken copies of the entries whose content is the same with the previous and/or next checkpoints. Simulation results of the spec 2006 benchmarks reveal that on the average RAT vulnerability is 25% and checkpoint vulnerability is 6%. Results also reveal that redundancy exists at sequential checkpoint copies and can be used for error detection and correction purposes. We propose techniques that exploit this redundancy and show that faults in 41% of all checkpoints and 44% of rolled-back checkpoints can be detected and errors in 33% of the rolled-back checkpoints can be corrected. Since we exploit the already available storage, proposed error detection and correction techniques can be implemented with minimal hardware overhead., This work was supported in part by the Scientific and Technological Research Council of Turkey (TUBITAK) under Grant 112E004 and in framework of COST ICT Action 1103., Scientific and Technological Research Council of Turkey (TUBITAK)Turkiye Bilimsel ve Teknolojik Arastirma Kurumu (TUBITAK) [112E004]; COST ICT Action [1103], ACM Special Interest Grp Design Automat, RAS, EDA Consortium, IEEE Council Elect Design Automat, ECSI, European Design ; Automat Assoc

Soft errors caused by cosmic rays or alpha particles emitted from the packaging material around the chips are becoming an increasingly important challenge in reliable microprocessor design. Transistor density, and die size trends show that soft errors will gain even more importance in the future. Due to their significant overheads, most redundancy schemes are employed where the penalty incurred can be hidden in the pipeline. Most contemporary processors employ a large physical register file to hold the produced results which may reside there for a long time. The register file is a critical element of a microprocessor and is needed to be protected against soft errors. In this paper we propose an SRAM bitcell design with ability to hold a redundant copy of the data and compare the copies with built-in comparators to detect a possible mismatch. Our experimental results show that the proposed design has 34% area, 7.9% power 2% delay overheads which are further reducible and can protect the register file against Silent Data Corruption (SDC). © 2012 IEEE., ASELSAN A.S.;Turkish Aerospace Industries, Inc. (TAI);The Scientific and Technological Research Council of Turkey

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06x/ 1.08x/ 1.36x shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03x/ 1.09x/ 1.12x/ 1.15x/ 1.17x shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33x/ 1.6x/ 2.4x higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13x/ 1.32x/ 1.37x/ 1.42x/ 1.5x higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31x/ 2.42x/ 2.55x/ 3.04x lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead. IEEE

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits 1.65×/3.03×/1.08×/1.38×shorter write delay (TWA) and 3.81×/1.20×/1.90×/2.13×higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and 1.36×/1.54×/1.22× shorter read delay (TRA) and 6.63× higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes 1.05×/1.21×/1.10×/1.81× lower static power (HPWR) than that of FD8T/SEDF9T/D12T/WWL12T while showing 3.44× higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes 1.01×/1.02×/1.04×smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of 1.37×/1.13× penalty in TWA/TRA and 6.23× penalty in HPWR when compared to FD8T and BI11T, respectively, at VDD = 0.7 V. © 1963-2012 IEEE.

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits 1.65×/3.03×/1.08×/1.38×shorter write delay (TWA) and 3.81×/1.20×/1.90×/2.13×higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and 1.36×/1.54×/1.22× shorter read delay (TRA) and 6.63× higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes 1.05×/1.21×/1.10×/1.81× lower static power (HPWR) than that of FD8T/SEDF9T/D12T/WWL12T while showing 3.44× higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes 1.01×/1.02×/1.04×smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of 1.37×/1.13× penalty in TWA/TRA and 6.23× penalty in HPWR when compared to FD8T and BI11T, respectively, at VDD = 0.7 V. © 1963-2012 IEEE.

type:Journal Article, As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulnerability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode., 24th IEEE European Test Symposium (ETS'19), May 27-31, 2019, Baden-Baden, Germany

In this paper, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that drives the charge generated by the ion track out of the sensitive device terminals. This electrical field is generated with the insertion of complementary doped regions near the active region of the device. We analyze the influence of the distance of those regions to the device, their depth into the substrate and their doping concentration to determine the optimal implementation which minimizes the collected charge. The impact on the device performance in terms of leakage current, threshold voltage, maximum transconductance and subthreshold voltage swing has also been investigated. Our results show that the added structures introduce negligible effects in performance degradation and total leakage current, at the cost of a small increase in area. The simulations performed with technology computer-aided design numerical (TCAD) tools in 22nm bulk FinFET technology show that the amount of charge collected by the device terminals can be reduced up to 50% for a linear energy transfer (LET) of 60 MeV-cm2/mg., Peer Reviewed, Postprint (published version)

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits 1.65×/3.03×/1.08×/1.38×shorter write delay (TWA) and 3.81×/1.20×/1.90×/2.13×higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and 1.36×/1.54×/1.22× shorter read delay (TRA) and 6.63× higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes 1.05×/1.21×/1.10×/1.81× lower static power (HPWR) than that of FD8T/SEDF9T/D12T/WWL12T while showing 3.44× higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes 1.01×/1.02×/1.04×smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of 1.37×/1.13× penalty in TWA/TRA and 6.23× penalty in HPWR when compared to FD8T and BI11T, respectively, at VDD = 0.7 V. © 1963-2012 IEEE.

This paper presents a comprehensive software-based technique that is capable of detecting soft errors in embedded systems. Soft errors can be categorized into Control Flow Errors (CFEs) and data errors. The CFEs change the flow of the program erroneously and data errors also change the results. In this paper, a new comprehensive method is presented to detect both (based on combination of authors’ previous works). In order to evaluate the proposed method, a new factor is defined that considers three main parameters simultaneously; namely fault coverage, memory overhead, and performance overhead. Since these parameters are very important in safety critical applications, they should be improved concurrently. The experimental results on SPEC2000 benchmarks show that the Evaluation Factor of the proposed method is 50% better than the Relationship Signatures for Control Flow Checking with Data Validation (RSCFCDV) methods, which are suggested in the literature.

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (2015 : Univ Massachusetts Amherst, Amherst, MA), Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. We start with the observation that many of the stored values inside the register file have very small Hamming distances when compared to each other. After showing this analysis results we propose a soft error correction scheme that makes use of the presence of multiple register values that have zero Hamming distance from each other. We use this already available redundancy along with parity protection to achieve error correction for many of the stored values. Our results show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0% of the errors with an additional power consumption of 18.9%.

Soft errors are an increasingly important problem in contemporary digital systems. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. In this paper we build on the previously proposed schemes and start with the observation that many register values already have a replica inside the storage space. We use this already available redundancy inside the register file in combination with a previously proposed value replication scheme for soft error detection and correction. We show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0 percent of the errors with an additional power consumption of 18.9 percent.

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (2015 : Univ Massachusetts Amherst, Amherst, MA), Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. We start with the observation that many of the stored values inside the register file have very small Hamming distances when compared to each other. After showing this analysis results we propose a soft error correction scheme that makes use of the presence of multiple register values that have zero Hamming distance from each other. We use this already available redundancy along with parity protection to achieve error correction for many of the stored values. Our results show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0% of the errors with an additional power consumption of 18.9%.

Soft errors are an increasingly important problem in contemporary digital systems. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. In this paper we build on the previously proposed schemes and start with the observation that many register values already have a replica inside the storage space. We use this already available redundancy inside the register file in combination with a previously proposed value replication scheme for soft error detection and correction. We show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0 percent of the errors with an additional power consumption of 18.9 percent.

“© © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”, This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP3). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed., MINECO, Universidad Complutense de Madrid, Depto. de Arquitectura de Computadores y Automática, Fac. de Informática, TRUE, inpress

El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales, médicas, nucleares, de defensa, y de transporte. La tolerancia de estos sistemas, o de los componentes que los integran, a fallos de tipo Single Event Effects (SEEs), es un tema de investigación importante y una característica imprescindible de cualquier sistema utilizado, no solo en aplicaciones críticas, sino también en las aplicaciones del día a día. Por esta razón, las aplicaciones de estos sistemas requieren, cada vez más, herramientas, métricas y parámetros específicos que permitan evaluar la tolerancia a fallos; y a su vez, permitan guiar el proceso para aplicar de forma eficiente los mecanismos de protección utilizados para la mitigación de estos fallos. En este contexto, esta tesis doctoral presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de fallos tipo Single Event upset (SEU) en procesadores Commercial Off-The-Shelf (COTS) y a través de plataformas de emulación/simulación. Esta herramienta aprovecha las ventajas que ofrecen las infraestructuras de depuración de hardware tales como On-Chip Debugging (OCD), y el depurador estándar de GNU (GDB) para la ejecución y depuración de los casos de estudio. También, se analiza la posibilidad de utilizar un modelo descrito en HDL (Hardware Description Language) del procesador MSP430 de Texas Instruments para estimar la fiabilidad de las aplicaciones al principio de la fase de desarrollo. Se utilizan diferentes métodos de inyección de fallos que muestran las ventajas que ofrece la emulación FPGA en comparación con las campañas de inyección llevadas a cabo en los dispositivos reales. La vulnerabilidad del banco de registros se compara y analiza por cada uno de sus registros. Por otro lado, esta memoria de tesis presenta una métrica para la aplicación eficiente del endurecimiento sel

El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales, médicas, nucleares, de defensa, y de transporte. La tolerancia de estos sistemas, o de los componentes que los integran, a fallos de tipo Single Event Effects (SEEs), es un tema de investigación importante y una característica imprescindible de cualquier sistema utilizado, no solo en aplicaciones críticas, sino también en las aplicaciones del día a día. Por esta razón, las aplicaciones de estos sistemas requieren, cada vez más, herramientas, métricas y parámetros específicos que permitan evaluar la tolerancia a fallos; y a su vez, permitan guiar el proceso para aplicar de forma eficiente los mecanismos de protección utilizados para la mitigación de estos fallos. En este contexto, esta tesis doctoral presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de fallos tipo Single Event upset (SEU) en procesadores Commercial Off-The-Shelf (COTS) y a través de plataformas de emulación/simulación. Esta herramienta aprovecha las ventajas que ofrecen las infraestructuras de depuración de hardware tales como On-Chip Debugging (OCD), y el depurador estándar de GNU (GDB) para la ejecución y depuración de los casos de estudio. También, se analiza la posibilidad de utilizar un modelo descrito en HDL (Hardware Description Language) del procesador MSP430 de Texas Instruments para estimar la fiabilidad de las aplicaciones al principio de la fase de desarrollo. Se utilizan diferentes métodos de inyección de fallos que muestran las ventajas que ofrece la emulación FPGA en comparación con las campañas de inyección llevadas a cabo en los dispositivos reales. La vulnerabilidad del banco de registros se compara y analiza por cada uno de sus registros. Por otro lado, esta memoria de tesis presenta una métrica para la aplicación eficiente del endurecimiento sel

Semiconductor devices used in outer space will be exposed to cosmic ray, which may lead to degradation of electric characteristics due to the large doses of radiation (total dose effect) and malfunction by heavy ions (single event phenomena). The total dose effect results from protons of solar, flare or electrons and protons captured by the magnetic field of the Earth. This memorandum describes space radiation environment, occurrence of single event in space, analysis of charge yield in a single event, single event caused by high energy heavy ions and high energy protons, countermeasures for single event, and evaluation technique of single event upset. These studies were completed in 1992, and the results were applied to extensive radiation tests. Especially, Cf-262 radiation test has been used for evaluation of integrated circuits developed by NASDA (National Space Development Agency of Japan) as a fundamental data of system design., 宇宙環境で使用する半導体デバイスに対する放射線の影響のうち、シングルイベントに関する1986年度〜1991年度における研究成果をまとめた。各年度毎の委託業務内容を紹介した後、シングルイベントに関連して以下の事項について述べた。(1)宇宙放射線環境:宇宙線環境の概要、銀河宇宙線、太陽フレア粒子、放射線帯粒子、地球磁場の効果、(2)宇宙におけるシングルイベントの発生状況:RSM(RAMソフトエラーモニタ)およびDOM(吸収線量モニタ)の概要、取得データとその解析、将来のシングルイベント観測計画、(3)シングルイベント電荷収集過程の解析:シングルイベント発生および電荷収集機構、電荷収集過程の直接測定法、(4)高エネルギー重粒子によるシングルイベント:予測方法、予測プログラム、(5)高エネルギープロトンによるシングルイベント:概要、Aパラメータを用いたプロトンによるSEU(シングルイベントアップセット)解析手法、高エネルギープロトンとシリコンの核反応、高エネルギープロトンによるシングルイベント予測プログラム、(6)半導体デバイスのシングルイベント対策:システム設計上のアプローチ、エラー検出・訂正機能の有効性の確認、システム設計例、(7)SEU評価試験技術:概要、照射源、SEU断面積の求め方、SEU断面積対LET(線形エネルギー転位)曲線の求め方、SEUの評価、SRAM(スタティックラム)のソフトエラー測定方法の例、SEU評価方法仕様書(案)。

Soft error rates (SERs) in partially depleted (PD) silicon-on-insulator (SOI) static random access memories (SRAMs) with a technology node of 90 nm have been investigated by hydrogen, helium, lithium, beryllium, carbon and oxygen ions, accelerated up to a few tens of MeV using a tandem accelerator. The SERs increased with increasing the amount of the generated charge in the SOI body by a floating body effect, even if the amount of the generated charge was less than the critical charge. The SERs with the generated charge in the SOI body more than the critical charge were almost constant., 形態: 図版あり, 著者人数: 11名, Physical characteristics: Original contains illustrations, Number of authors: 11

Neutron-induced soft errors in NMOSFETs from a 65 nm to a 25 nm technology are analyzed based on a simple sensitive volume (SV) model using the PHITS code, and the results are compared with those obtained by PHITS-HyENEXSS based on event-by-event TCAD simulation. The SERs calculated by PHITS-SV are in good agreement with the SERs obtained by PHITS-HyENEXSS by adjusting the SV size. Validation of the SV size is discussed on the basis of comparisons of the collected charge between TCAD simulation and SV model calculation for each single event., 形態: カラー図版あり, Physical characteristics: Original contains color illustrations

We develop a simple model that computes the probability that a strike at the output of a gate has an impact in any output by traversing the circuits backwards from the outputs and gaining information about the logical masking using signal probabilities. The model is validated with fault injection

Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on/off ratio, excellent scalability, good endurance, and great compatibility with silicon CMOS technology. The most attractive of the characteristics of ReRAM is its cross-point structure, which features a 4F2 cell size. In a cross-point structure, the existence of sneak current and resulting voltage loss due to the wire's resistance might cause read and write failures if not designed properly. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this article, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure types on the reliability of the cross-point array. We also propose an error-resilient architecture, which avoids unnecessary writes in the hard error detection unit. Assuming constant soft error rate, our approach can extend the lifetime of ReRAM up to 75% over a design without hard error detection and up to 12% over the design with a "write-verify" detection mechanism. Our approach yields greater significant lifetime improvement when considering postcycling retention degradation.

(c) 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works., Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section. These tests led to cross-section values two orders of magnitude below those of typical CMOS SRAMs in the same technology node. MUSCA SEP3 simulations complement these results predicting that only high-energy neutrons ( > 30 MeV) can provoke bit flips in the studied SRAMs. MUSCA SEP3 is also used to investigate the sensitivity of the studied SRAM to radioactive contamination and to compare it with the one of standard CMOS SRAMs. Results are useful to make predictions about the operation of this memory in environments such as avionics., Ministerio de Economía y Competitividad (MINECO), Universidad Complutense de Madrid, Banco Santander, Depto. de Estructura de la Materia, Física Térmica y Electrónica, Depto. de Arquitectura de Computadores y Automática, Fac. de Ciencias Físicas, Fac. de Informática, TRUE, pub

This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results.

The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.

As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by the more frequent appearance of soft errors are becoming critical for future embedded multiprocessor systems design. State-of-the-art techniques for soft error protections targeting multiprocessor systems result either high chip cost and area overhead or high performance degradation and energy consumption, and do not fulfill the increasing requirements for high performance and dependability. In this article we present a systematic approach, that is, the Sensor Networks-on-Chip (SENoC), to collaboratively and efficiently manage on-chip applications and overcome reliability threats to Multiprocessor Systems-on-Chip (MPSoC). A hardware-software collaborative approach is proposed to solve soft error problems: a hardware-based on-chip sensor network is built for soft error detection, and a software-based recovery mechanism is applied for soft error correction. A two-step scheduling scheme is presented for reliable application and chip management, combining an off-line static optimization stage for application performance maximization and an online lightweight dynamic adjustment stage to handle runtime variations and exceptions. This strategy introduces only trivial overhead on hardware design and much lower overhead on software control and execution, and hence performance degradation and energy consumption is greatly reduced. We build a cycle-accurate simulator using SystemC, and verify the effectiveness of our technique by comparing performance with related techniques on several real-world applications.

This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results.