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In this work the transport mechanisms and charge trapping of novel dielectric systems based on semiconductor nano-crystals embedded in a dielectric matrix are studied. In particular, stacked films composed of a thin bottom dielectric (2–4 nm thick SiO2or Si3N4), with an embedded two-dimensional (2-D) array of Si nano-crystals (obtained by low pressure chemical vapor deposition or by annealing of silicon rich oxide) and a thick top dielectric (8 nm-thick SiO2) are investigated. Gate leakage currents, at medium/high electric fields, are examined at temperatures varying between 77 and 473 K. Charge trapping phenomena, occurring at low electric fields, are studied as a function of the stressing gate voltage and the stressing time. Experimental results are explained by means of an elastic tunneling model, which takes into account the main structural characteristics of the Si-dots (size dispersion, density, spatial distribution) as well as the effect of trapped charges in the silicon nano-crystals.

In this work we will give a detailed account of the charging/discharging phenomena occurring in semiconductor nano-crystal memories. Memory transfer characteristics and write/ erase transient characteristics are studied for devices with different technological parameters. Experimental results are explained by means of a semi-classical model, based on a modified current continuity approach. This model depicts the effect of the tunnel/top dielectric thickness, dot recovered area and programming voltage on the device performance.

This work deals with the electrical characteristics and physical properties of novel dielectric systems based on silicon nanocrystals embedded in SiO2matrices. In particular, the transport phenomena of 10 nm thick SiO2capacitors with an embedded thin layer (5 nm) of LPCVD Si nanocrystals, located at different tunneling distances from the oxide–substrate interface, are studied. An original model based on an elastic tunneling phenomenon, which allows an efficient evaluation of the main structural characteristics of Si dots, is proposed.

Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGexon SOI substrate, the partial amorphization and crystallization of the Si/Si1-xGexbilayers and the selective removal of the top Si1-xGexfilm. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted-SOI (CMOS FD-SOI) devices, with gate length lower than 15 nm, were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.

The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power, high performance and increased functionalities. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to reduce power consumption and manage low supply voltage. Multigate architectures increase MOSFETs drivability, reduce power, and allow new memory devices opportunities for future applications. By introducing new materials(HiK, Ge, III-V, Carbon based materials like diamond, graphene and CNTs, molecules,...), and new functions such as sensing and actuation allowing to interface the outside world (M/NEMS, filters, Imagers,...), Si based CMOS will be scaled beyond the ITRS as the System-on- Chip/Wafer Platform. The Heterogeneous integration of these devices with CMOS will require new 3D and Packaging schemes leading to the increase of effective packing density, improving systems figures of merit.