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In-memory computing may make it possible to realize non-von Neumann computing because the logic circuits are unified in the memory units. We investigated two types of in-memory logic operations, namely, two-input logic circuits and multifunctional artificial synapses. These were realized in a dual-gate antiambipolar transistor (AAT) with a ReS2/WSe2heterojunction, in which polystyrene with a zinc phthalocyanine core (ZnPc-PS4) was incorporated as a memory layer. Here, reconfigurability is a key concept for both types of device operations and was achieved by merging the Λ-shaped transfer curve of the AAT and the nonvolatile memory effect of ZnPc-PS4. First, we achieved electrically reconfigurable two-input logic circuits. Versatile logic circuits such as AND, OR, NAND, NOR, and XOR circuits were demonstrated by taking advantage of the Λ-shaped transfer curve of the dual-gate AAT. Importantly, the nonvolatile memory function provided the electrical switching of the individual circuits between AND/OR, NAND/NOR, and XOR/NAND circuits with constant input signals. Second, the memory effect was applied to multifunctional artificial synapses. The inhibitory/excitatory and long-term potentiation/depression synaptic operations were electrically reconfigured simply by controlling one parameter (readout voltage), making three distinct responses possible even with the same presynaptic signals. These findings provide hints that may lead to the realization of new in-memory computing architectures beyond the current von Neumann computers.

Graphene/hexagonal boron nitride (hBN) moiré superlattices have attracted interest for use in the study of many-body effects and fractal physics in Dirac fermion systems. Many exotic transport properties have been intensively examined in such superlattices, but previous studies have not focused on single-carrier transport. The investigation of the single-carrier behavior in these superlattices would lead to an understanding of the transition of single-particle/correlated phenomena. Here, we show the single-carrier transport in a high-quality bilayer graphene/hBN superlattice-based quantum dot device. We demonstrate remarkable device controllability in the energy range near the charge neutrality point (CNP) and the hole-side satellite point. Under a perpendicular magnetic field, Coulomb oscillations disappear near the CNP, which could be a signature of the crossover between Coulomb blockade and quantum Hall regimes. Our results pave the way for exploring the relationship of single-electron transport and fractal quantum Hall effects with correlated phenomena in two-dimensional quantum materials.

Bubbles at the interface of two-dimensional layered materials in van der Waals heterostructures cause deterioration in the quality of materials, thereby limiting the size and design of devices. In this paper, we report a simple all-dry transfer technique, with which the bubble formation can be avoided. As a key factor in the technique, a contact angle between a picked-up flake on a viscoelastic polymer stamp and another flake on a substrate was introduced by protrusion at the stamp surface. Using this technique, we demonstrated the fabrication of high-quality devices on the basis of graphene/hexagonal boron nitride heterostructures with a large bubble-free region. Additionally, the technique can be used to remove unnecessary flakes on a substrate under an optical microscopic scale. Most importantly, it improves the yield and throughput for the fabrication process of high-quality van der Waals heterostructure-based devices.

Phase-transition field-effect transistors (FETs) are a class of steep-slope devices that show abrupt on/off switching owing to the metal–insulator transition (MIT) induced in the contacting materials. An important avenue to develop phase-transition FETs is to understand the charge injection mechanism at the junction of the contacting MIT materials and semiconductor channels. Here, toward the realization of high-performance phase-transition FETs, we investigate the contact properties of heterojunctions between semiconducting transition-metal dichalcogenides (TMDCs) and vanadium dioxide (VO2) that undergoes a MIT at a critical temperature (Tc) of approximately 340 K. We fabricated transistors based on molybdenum disulfide (MoS2) and tungsten diselenide (WSe2) in contact with the VO2source/drain electrodes. The VO2-contacted MoS2transistor exhibited n-type transport both below and above Tc. Across the MIT, the on-current was observed to increase only by a factor of 5, in contrast to the order-of-magnitude change in the resistance of the VO2electrodes, suggesting the existence of high contact resistance. The Arrhenius analyses of the gate-dependent drain current confirmed the formation of the interfacial barrier at the VO2/MoS2contacts, irrespective of the phase state of VO2. The VO2-contacted WSe2transistor showed ambipolar transport, indicating that the Fermi level lies near the mid gap of WSe2. These observations provide insights into the contact properties of phase-transition FETs based on VO2and TMDCs and suggest the need for contact engineering for high-performance operations.

Vanadium dioxide (VO2) exhibits an insulator–metal transition (IMT) accompanied with a giant resistance change, which is attractive for the application of devices, such as switching devices. Since the behavior of individual domains determines the total IMT property of the VO2sample, the steep resistance change from a single domain can be identified and utilized in a sample whose size is as small as the individual domain size. Uniquely, micro-structured VO2thin films on hexagonal boron nitride (hBN) exhibit step resistance changes owing to the confined metallic domains. In this study, we demonstrated step electrical switching in the two-terminal VO2sample produced on hBN. Operando structural and electric investigation revealed that the emergence of metallic domains in the micrometer space contributes to the step electric current increase. Our results indicate the use of individual metallic domains in VO2thin films on hBN in the application of novel devices.

The polarity of the charge carriers injected through Schottky junctions of α-phase molybdenum ditelluride (α-MoTe2) and various metals was characterized. We found that the Fermi-level pinning in the metal/α-MoTe2Schottky junction is so weak that the polarity of the carriers (electron or hole) injected from the junction can be controlled by the work function of the metals, in contrast to other transition metal dichalcogenides such as MoS2. From the estimation of the Schottky barrier heights, we obtained p-type carrier (hole) injection from a Pt/α-MoTe2junction with a Schottky barrier height of 40 meV at the valence band edge. n-Type carrier (electron) injection from Ti/α-MoTe2and Ni/α-MoTe2junctions was also observed with Schottky barrier heights of 50 and 100 meV, respectively, at the conduction band edge. In addition, enhanced ambipolarity was demonstrated in a Pt–Ti hybrid contact with a unique structure specially designed for polarity-reversible transistors, in which Pt and Ti electrodes were placed in parallel for injecting both electrons and holes.

A doping-free transistor made of ambipolar α-phase molybdenum ditelluride (α-MoTe2) is proposed in which the transistor polarity (p-type and n-type) is electrostatically controlled by dual top gates. The voltage signal in one of the gates determines the transistor polarity, while the other gate modulates the drain current. We demonstrate the transistor operation experimentally, with electrostatically controlled polarity of both p- and n-type in a single transistor.

The conduction properties of graphene were tuned by tailoring the lattice by using an accelerated helium ion beam to embed low-density defects in the lattice. The density of the embedded defects was estimated to be 2–3 orders of magnitude lower than that of carbon atoms, and they functionalized a graphene sheet in a more stable manner than chemical surface modifications can do. Current modulation through back gate biasing was demonstrated at room temperature with a current on–off ratio of 2 orders of magnitude, and the activation energy of the thermally activated transport regime was evaluated. The exponential dependence of the current on the length of the functionalized region in graphene suggested that conduction tuning is possible through strong localization of carriers at sites induced by a sparsely distributed random potential modulation.

We first describe self-organizing graphene ribbon formation by chemical vapor deposition. Graphene ribbons can be formed only on narrow twin crystal regions with a (001) or high-index surface sandwiched between Cu crystals having (111) surfaces. At a relatively low CH4 pressure in Ar/H2, graphene is preferentially nucleated and formed on twin crystals. The preferential nucleation is probably caused by a difference in surface-dependent adsorption energies of reactants. In the second part, we describe newly developed dual-gated graphene transistors. We found that a transistor with a graphene channel irradiated with He ions can have a transport gap up to 380 meV. We then made dual-gated transistors using such a channel and obtained an on-off ratio of 103 at 200 K. The device has a channel region between the dual gates, and the polarity of the transistor can be electrostatically reversed by flipping the bias polarity of one of the dual gates.

We demonstrate the possibility in quantifying the Raman intensities for both specimen and substrate layers in a common stacked experimental configuration and, consequently, propose a general and rapid thickness identification technique for atomic-scale layers on dielectric substrates. Unprecedentedly wide-range Raman data for atomically flat MoS2flakes are collected to compare with theoretical models. We reveal that all intensity features can be accurately captured when including optical interference effect. Surprisingly, we find that even freely suspended chalcogenide few-layer flakes have a stronger Raman response than that from the bulk phase. Importantly, despite the oscillating intensity of specimen spectrum versusthickness, the substrate weighted spectral intensity becomes monotonic. Combined with its sensitivity to specimen thickness, we suggest this quantity can be used to rapidly determine the accurate thickness for atomic layers.

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on the development of mobility-enhanced CMOS device structures using strained-Si/SiGe/Ge MOS channels and the carrier transport properties in those channels. It is shown, particularly, that uniaxial compressive strain and Ge channels are quite effective in pMOS performance enhancement, while uniaxial tensile strain is effective in nMOS performance.

An effective wet cleaning process, optimized for low temperature Ge epitaxy on thin Ge or SiGe structures with reduced surface roughening, is proposed. It is found that the HF+HCl cleaning is the most effective wet cleaning method that is applicable to the low temperature thermal cleaning. It is also found that temperature of the thermal cleaning appropriate for thin Germanium on Insulator (GOI) substrates is approximately 450oC. Moreover, the successful formation of the strained-GOI structures is demonstrated by applying these wet and thermal cleaning processes to thin Silicon-Germanium on Insulator (SGOI) substrates.

Recent developments in the Ge condensation technique for the fabrication of the SiGe on insulator (SGOI) structures, which are the basic templates for the strained channel MOSFET's, and the further extensions to the SGOI formation on (110) substrates and the Ge on insulator (GOI) formation are reviewed in this paper. The detail analyses of the phenomenon during the initial stage in the Ge condensation process, in which the fragments of the misfit dislocations, that are formed at the SiGe / SOI interface, rise up resulting the generation of the threading dislocations are quite important, and the controlling of the understood phenomenon by the modification of the condensation recipe brings the successful fabrication of the high quality SGOI substrates with low dislocation density.

Ge channel MOSFETs have recently stirred a strong interest as a promising candidate for high speed MOSFETs beyond strained- Si channels. It has been well recognized, however, that there exist a variety of issues to be solved for realizing Ge MOS technologies. Major critical issues include (1) Gate insulator formation with high quality MIS interfaces (2) High quality GOI or Ge substrate formation (3) Formation of low resistivity S/D junctions (4) CMOS structures and integration. In this paper, these technological problems are addressed and possible solutions for these technological challenges are presented on a basis of our recent research progress.

A magneto-oscillation of the susceptibility was observed in the organic superconductor κ-(BEDT-TTF)2Cu[N(CN)2]Br under magnetic field applied parallel to the two-dimensional plane. The oscillation is understood in terms of the successive transition of Josephson vortex ordering.

Using a single-device two-dimensional (2D) rhenium disulfide (ReS2) field-effect transistor (FET) with enhanced gas species selectivity by light illumination, we reported a selective and sensitive detection of volatile organic compound (VOC) gases. 2D materials have the advantage of a high surface-area-to-volume ratio for high sensitivity to molecules attached to the surface and tunable carrier concentration through field-effect control from the back-gate of the channel, while keeping the top surface open to the air for chemical sensing. In addition to these advantages, ReS2has a direct band gap also in multilayer cases, which sets it apart from other transition-metal dichalcogenides (TMDCs). We take advantage of the effective response of ReS2to light illumination to improve the selectivity and gas-sensing efficiency of a ReS2-FET device. We found that light illumination modulates the drain current response in a ReS2-FET to adsorbed molecules, and the sensing activity differs depending on the gas species used, such as acetone, ethanol, and methanol. Furthermore, wavelength and carrier density rely on certain variations in light-modulated sensing behaviors for each chemical. The device will distinguish the gas concentration in a mixture of VOCs using the differences induced by light illumination, enhancing the selectivity of the sensor device. Our results shed new light on the sensing technologies for realizing a large-scale sensor network in the Internet-of-Things era.

Carbon-based superlattices represent a novel class of quantum metamaterials having promising prospects. Here, we show the first fabrication of folded bilayer-bilayer graphene (fBBLG)/hexagonal boron nitride (hBN) superlattices. In the transport properties at low temperatures, satellite peaks are observed due to the crystallographic angle alignment of fBBLG and hBN. The peculiar resistance peaks appear away from the charge neutrality point and the hBN-induced satellites, which may be signatures of possible competing orders. Our results suggest the emergence of a unique electronic band-structure in the fBBLG, providing a way for investigating the correlated electron phenomena by performing energy-band engineering with superlattice structures.

A He+ ion beam is used to induce electronic localization, on a single graphene layer exfoliated on an ultra-flat sapphire substrate, based on crystalline defects and with a lateral irradiation precision of 1 nm. Inducing a 1% carbon defect density by step by step irradiation of a 100-nm-wide band on the supported graphene increases its electrical resistance from 0.90 to 133 kO. The resistance build-up was monitored in situ and in real time by measuring the I(t) current intensity through the graphene monolayer flake during its irradiation. The whole process takes place on an ultra-polished sapphire surface used to retain the planarity of the graphene. We propose that local heating of the graphene by irradiation promotes the migration of the created atomic carbon defects to the edge of the flake. This inherently moderates the increase of resistance with time during He+ irradiation due to the gradual re-opening of low-voltage graphene ballistic channels.

We demonstrate charge and spin current transport in a graphene-based lateral spin valve using yttrium oxide (Y-O) as a tunneling barrier between graphene and a ferromagnetic electrode. A Y-O layer grown on graphene is flat, with a root-mean-square roughness of 0.17 nm, which is much lower than that of conventional barrier materials. This flatness allows the utilization of a very thin but well-defined tunneling barrier, leading to a large spin signal of ?20 ? and a high spin injection efficiency of 15% with a low contact resistance of ?1 k?. These findings represent important progress toward the realization of graphene-based spintronics applications.

We first describe self-organizing graphene ribbon formation by chemical vapor deposition. Graphene ribbons can be formed only on narrow twin crystal regions with a (001) or high-index surface sandwiched between Cu crystals having (111) surfaces. At a relatively low CH4pressure in Ar/H2, graphene is preferentially nucleated and formed on twin crystals. The preferential nucleation is probably caused by a difference in surface-dependent adsorption energies of reactants. In the second part, we describe newly developed dual-gated graphene transistors. We found that a transistor with a graphene channel irradiated with He ions can have a transport gap up to 380 meV. We then made dual-gated transistors using such a channel and obtained an on-off ratio of 103at 200 K. The device has a channel region between the dual gates, and the polarity of the transistor can be electrostatically reversed by flipping the bias polarity of one of the dual gates.

A graphene P-I-N junction switching device with a nanoribbon is proposed, which was aimed at finding an optimized operation scheme for graphene transistors. The device has two bulk graphene regions where the carrier type is electrostatically controlled by a top gate, and these two regions are separated by a nanoribbon that works as an insulator, resulting in a junction configuration of (P or N)-I-(P or N). It is demonstrated that the drain current modulation strongly depends on the junction configuration, while the nanoribbon is not directly top-gated, and that the device with a P-I-N or N-I-P junction can exhibit better switching properties.

A graphene P-I-N junction switching device with a nanoribbon is proposed, which was aimed at finding an optimized operation scheme for graphene transistors. The device has two bulk graphene regions where the carrier type is electrostatically controlled by a top gate, and these two regions are separated by a nanoribbon that works as an insulator, resulting in a junction configuration of (P or N)-I-(P or N). It is demonstrated that the drain current modulation strongly depends on the junction configuration, while the nanoribbon is not directly top-gated, and that the device with a P-I-N or N-I-P junction can exhibit better switching properties.

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on the development of mobility-enhanced CMOS device structures using strained-Si/SiGe/Ge MOS channels and the carrier transport properties in those channels. It is shown, particularly, that uniaxial compressive strain and Ge channels are quite effective in pMOS performance enhancement, while uniaxial tensile strain is effective in nMOS performance.

Ge channel MOSFETs have recently stirred a strong interest as a promising candidate for high speed MOSFETs beyond strained- Si channels. It has been well recognized, however, that there exist a variety of issues to be solved for realizing Ge MOS technologies. Major critical issues include (1) Gate insulator formation with high quality MIS interfaces (2) High quality GOI or Ge substrate formation (3) Formation of low resistivity S/D junctions (4) CMOS structures and integration. In this paper, these technological problems are addressed and possible solutions for these technological challenges are presented on a basis of our recent research progress.

An effective wet cleaning process, optimized for low temperature Ge epitaxy on thin Ge or SiGe structures with reduced surface roughening, is proposed. It is found that the HF+HCl cleaning is the most effective wet cleaning method that is applicable to the low temperature thermal cleaning. It is also found that temperature of the thermal cleaning appropriate for thin Germanium on Insulator (GOI) substrates is approximately 450ºC. Moreover, the successful formation of the strained-GOI structures is demonstrated by applying these wet and thermal cleaning processes to thin Silicon-Germanium on Insulator (SGOI) substrates.

Recent developments in the Ge condensation technique for the fabrication of the SiGe on insulator (SGOI) structures, which are the basic templates for the strained channel MOSFET's, and the further extensions to the SGOI formation on (110) substrates and the Ge on insulator (GOI) formation are reviewed in this paper. The detail analyses of the phenomenon during the initial stage in the Ge condensation process, in which the fragments of the misfit dislocations, that are formed at the SiGe / SOI interface, rise up resulting the generation of the threading dislocations are quite important, and the controlling of the understood phenomenon by the modification of the condensation recipe brings the successful fabrication of the high quality SGOI substrates with low dislocation density.