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This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical sensing transistors. We simulated and fabricated the proposed DIBBSA architecture with various operational modes in 65-nm CMOS technology to analyze body biasing’s effectiveness in mitigating the offset. The standard deviation of offset (σOS) was measured over 5120 SAs in 10 ICs. The iso-gate area reduction in σOS for the proposed DIBBSA-FL and DIBBSA-PD modes resulted in 68.1% and 61.9% compared to conventional Current Latch SA (CLSA) and 24.1% and 18.1% compared to Voltage Latch SA (VLSA) at 0.4 V supply and 25 °C, respectively. Carried out measurements on 512 SAs in an IC show the minimum required differential input voltage across the temperature range of 0 °C to 75 °C at 0.4 V is achieved to be 48% lower compared to CLSA and 28% lower compared to VLSA by both the DIBBSA-FL and DIBBSA-PD modes. [ABSTRACT FROM AUTHOR]

Sense amplifier (SA) input-referred offset often dictates the minimum required differential input ($\Delta V_{\textrm {BL-min}}$) and is an important factor in realizing low-voltage static random access memories. This paper presents a HYbrid latch-type Sense Amplifier (HYSA-QZ), where the bitline signals are supplied to multiple internal nodes to significantly reduce $\Delta V_{\textrm {BL-min}}$. A 65-nm CMOS test chip with arrays of the HYSA-QZ, two intermediate formulations of the HYSA-QZ, conventional current latch SA (CLSA), and conventional voltage latch SA (VLSA) were fabricated. Measurements over 5120 SAs of each type show that the HYSA-QZ implemented with regular- $V_{\mathrm{ T}}$ transistors require 50.0%, and 22.8% lower $\Delta \text{V}_{\textrm {BL-min}}$ with 6.5% (or 4.5%) and 30.7% (or 18.8%) of total gate (or layout) area overhead compared to CLSA and VLSA at 0.4 V, respectively. Iso-gate-area offset improvement was substantiated with Pelgrom’s mismatch model, where the HYSA-QZ with regular- ${\mathrm{ V}}_{\mathrm{ T}}$ transistors showed 46.6% and 7.7% improvements in measured standard deviation of offset distribution compared with CLSA and VLSA, respectively. Measured $\Delta V_{\textrm {BL-min}}$ for the HYSA-QZ remains stable and low over a temperature range from 0 °C to 75 °C at 0.4 V. Moreover, an additional 13.0% reduction in $\Delta V_{\textrm {BL-min}}$ was measured in the HYSA-QZ when using low- $V_{\mathrm{ T}}$ transistors. Finally, the HYSA-QZ operates reliably at $V_{\textrm {DD-min}}$ of 260 mV in 25 °C. [ABSTRACT FROM AUTHOR]