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Energy-efficient and cost-effective wireless connectivity is of paramount importance for Internet-of-Things (IoT) applications and has inspired a lot of research interests lately. Reuse techniques at both the transceiver architecture and functional RF circuit levels are especially attractive as they aim to break the trade-off between power, performance and cost, while retaining compliance with the dedicated IoT communication standard. This tutorial presents a review of the widely adopted “current reuse” and “RF-I/O reuse” techniques in RFIC design and the recent design trends towards “function reuse”, “area reuse” in support for low power IoT.

In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD) to combat the intrinsic non-linearity of an LC-type digitally controlled oscillator (DCO), thus avoiding the complications of frequency-dependent calibrations. The prototype, implemented in 40-nm CMOS, modulates the carrier in the range of 2.7–3.9 GHz from a 40-MHz reference. The measured EVM is −47 dB for a 60-Mb/s 64-PSK modulation under the case that the phase-modulated output is frequency-divided by $K=8$ , i.e., when the DCO exhibits the most significant non-linearity due to the large fractional FM bandwidth. When $K=8$ or 4, the measured EVM remains below −43 dB across the carrier-frequency tuning range and without re-calibrating the DCO non-linearity.

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs—the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges—and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below −59 dBc. Under considerable supply or temperature variations, the worst spur still remains below −51.7 dBc without any background calibration tracking.

In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90° I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140–250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors’ knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

This brief presents a 2-stage, low-power, millimeter-wave (mm-wave) LNA that aims at first to reduce its passive area through a transformer formed with inductors between the gate and source sides of the input transistor in a source-degenerated cascode. While reducing the passive area, the introduced transformer creates a magnetic feedback that further reduces the LNA’s noise figure (NF). We provide a theoretical analysis of this feedback-based noise reduction method and validate it with simulations and experimental results. The LNA has been fabricated in 22-nm FD-SOI CMOS and has a core area of only 0.09 mm2. The measurement results show that this design achieves a minimum 2.1 dB NF and a maximum 23.1 dB gain between 23.7–28.5 GHz at a power dissipation of only 5.6 mW from a 0.6V supply. Furthermore, despite using only a 0.6V supply voltage, IIP3 can still reach −16.5 dBm at 28 GHz. Targeting mm-wave 5G applications, the presented LNA is among the best-in-class with a sub-1V supply voltage.

A frequency-to-digital converter (FDC) performs the role of precise frequency digitization within a voltage-controlled oscillator (VCO)-based ADC. To be compatible with energy-harvesting (EH) Internet-of-Things (IoT) devices, the development of ultra-low-voltage (ULV) FDCs is crucial, where the primary focus must be directed towards the maximization of data throughput under dramatic constraints of reliability and timing variability associated with deep-subthreshold operation. This article investigates the speed maximization of a 0.2V full-custom ULV FDC design, consisting of an array of several parallel XOR-based FDC units, and the multi-rate decimation-filtering digital back-end. At the core of this broad exploration is a high-speed sense-amplify phase sampler (PS) featuring hardware redundancy, capable of sampling the phase of low-voltage-swing inputs. Particular focus is placed on the yield-based reliability-driven design methodology for the sense-amplify phase-sampling circuits running up to 40MS/s and practical variability-mitigation strategies. To overcome the speed bottleneck in the digital back-end, a fully parallel bitstream-processing architectural composition of the computations for summation and decimation are proposed. Experimental verification through measurements of the FDC integrated within a 10-bit 160kHz bandwidth (BW) open-loop VCO-based ADC across clock frequency with supply variations demonstrate robust operation of the first 0.2V multi-phase FDC in the advanced 28nm CMOS process.

This paper presents a simple yet effective $G_{m}$ -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the $1/f$ noise upconversion. A complete $1/f^{3}$ PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shift range is introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm2 and achieves $1/f^{3}$ PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset. [ABSTRACT FROM AUTHOR]

Quantum computing has the potential to create a paradigm shift in computing technology, which can lead to breakthroughs in emerging applications that rely on ultra-high-performance computing, e.g., artificial intelligence. Among several implementation approaches for quantum computers, semiconductor-based quantum computing, especially using CMOS technologies, is promising because it can be used to implement large arrays of qubits with their control and readout circuitry on a single chip.

We present an architecture of a Bluetooth low energy (BLE)-compliant receiver which, for the first time ever, breaks the 1mW barrier of power consumption. It is based on a type-II phase-tracking loop and addresses the mutual magnetic coupling between on-chip inductors of a digitally controller oscillator (DCO) and low-noise transconductance amplifier (LNTA), which causes RX performance degradation in the prior-art implementations. An inverter-based inductor-free LNTA is employed instead. The resulting adjacent channel rejection (ACR) improves by 1.5/2.5dB at 2/3MHz offset. By further leveraging current-reuse and switched-capacitor circuitry, this RX achieves the best-in-class FoM of 183.2dB with sensitivity of −93.2dBm. Thanks to the single-channel topology, the proposed RX occupies tiny area of 0.48mm2 in 28-nm CMOS. [ABSTRACT FROM AUTHOR]

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL’s phase detector (2.7–4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of −232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of −247dB, and normalized TR and area (FOMTA) of −262dB. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband 2.4 GHz 2 × 9-bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts. [ABSTRACT FROM AUTHOR]

In this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors’ transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25- $\mu \text{m}$ GaN-on-SiC process with 28-V supply, provides 35.1–38.9dBm output power, 45–61% drain efficiency (DE), 40–55% power-added efficiency (PAE), and 11.3–13.4dB power gain, across 2.0–4.0GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4GHz, it achieves 2.5% (−32.0dB) rms error vector magnitude (EVM $_{{\mathrm {rms}}}$) and −37.5/−37.6dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1dBm and 20.6/19.5%, without predistortion. EVM $_{{\mathrm {rms}}}$ and ACLR can be improved to 0.5% (−46dB) and −46.4/−46.8dBc by using digital predistortion (DPD). [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. For medium- to high-resolution applications, the size of the DAC is typically determined by random mismatches. As such, an effective mismatch calibration circuit can allow the DAC to be scaled down to a much lower $kT/C$ noise limit, thereby increasing the overall ADC power efficiency. This paper reviews some of the most important reported mismatch calibration techniques and proposes a foreground calibration method based on a deterministic self-calibration and stochastic quantization. This approach is experimentally validated on a prototype 10-bit SAR ADC fabricated in TSMC 28-nm LP CMOS technology, demonstrating an INL and SFDR improvement of respectively 6.4 LSB and 14.9 dB at 85 MS/s. [ABSTRACT FROM AUTHOR]

A 50 MS/s two-step flash-MASH 1-1-1 time-to-digital converter (TDC) employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology. Such an error-feedback unit of 1st-order noise-shaping TDC can be cascaded as a multi-stage noise shaping (MASH) configuration to achieve higher-order noise-shaping and, thereby high resolution. This paper also discusses different noise sources, linearity and noise tradeoffs in noise-shaping TDC and then demonstrates a histogram testing technique to correct the mismatch of 1st stage flash TDC. An on/off-chip delay modulation (DM) measurement technique is presented to characterize the TDC linearity and noise performance. Fabricated in 40-nm CMOS technology, the proposed TDC consumes 1.32 mW from a 1.1 V supply. At frequency below 2.5 MHz, the TDC error integrates to 147fsrms, which is equal to equivalent flash resolution of 1.6 ps. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a new switched-capacitor (SC) passive delta-sigma ($\Delta \Sigma $) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the conventional SC passive $\Delta \Sigma $ modulators. To improve the proposed modulator’s noise suppression and stability, an independent extra feedback path and a zeroing stage are added to the 2nd-stage integrator. Moreover, a pipelining (i.e. interleaving) technique is employed in the passive low-pass filter to relax settling requirements and improve power efficiency. Compared to the $\Delta \Sigma $ modulators with active integrators, the proposed modulator contains only switches, capacitors and one comparator, thus being greatly amenable to nanoscale CMOS process nodes. Implemented in 28-nm CMOS, the proposed ADC occupies a core area of 0.059 mm2. It achieves measured SNDR of 81.1 dB and a measured dynamic range (DR) of 83.6 dB with a signal bandwidth of 80 kHz at 40.96 MS/s, while consuming 101.5 $\mu \text{W}$. SNDR is maintained above 70 dB across a ±20% supply variation. [ABSTRACT FROM AUTHOR]

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm2. [ABSTRACT FROM AUTHOR]

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order $\Delta \Sigma $ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement. [ABSTRACT FROM AUTHOR]

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter’s (DTC’s) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of −109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW. [ABSTRACT FROM AUTHOR]

In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. The tank is forced in common-mode oscillation by two injection locked Colpitts oscillators at the transformer’s primary winding, while a two-port structure provides differential-mode oscillation. An analysis is also presented to compare the phase noise performance of the dual-core oscillator in common-mode and differential-mode excitations. A prototype implemented in digital 40-nm CMOS verifies the dual-mode oscillation and occupies only 0.12 mm2 and measures 56% tuning range. [ABSTRACT FROM AUTHOR]

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dual-core LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07–4.91 GHz, while drawing 39–59 mA from a 2.15 V power supply. The measured PN is $-$146.7 dBc/Hz and $-$163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area. [ABSTRACT FROM AUTHOR]

A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20–100 MHz. The BPF is part of a cellular superheterodyne receiver and completely determines the receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free from any aliasing or replicas in its transfer function. Furthermore, the advantage of CS-BPF over other band-pass filters such as N-path, active-RC, Gm-C, and biquad is described. A mathematical noise analysis of the CS-BPF and the comparison of simulations and calculations are presented. The entire 65 nm CMOS receiver, which does not include a front-end LNTA for test reasons, achieves a total gain of 35 dB, IRN of 1.5\ nV/\sqrtHz, out-of-band IIP3 of +10 dBm. It consumes 24 mA at 1.2 V power supply. [ABSTRACT FROM PUBLISHER]

We propose a time-domain technique that significantly improves resolution of an RF-DAC. As an alternative to resorting to various resolution improvement attempts in the amplitude domain or through quantization noise shaping, pulsewidth modulation (PWM) of a single unit switching device is employed with fine timing accuracy easily afforded by advanced CMOS technology. The PWM is categorized into centered PWM and noncentered PWM depending on the relative pulse position, and their performance and implementation methods are compared. The technique is examined in the context of a commercial EDGE polar transmitter realized in 65 nm CMOS, which employs an amplitude modulator with basic 10-bit amplitude resolution limited by the RF-DAC switching device mismatches. The proposed architectures with centered PWM and noncentered PWM achieve the worst case resolution improvement of 2.2 bits and 2.5 bits, respectively, assuming 20-ps worst case time granularity of the PWM signal controls. [ABSTRACT FROM PUBLISHER]

We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter. [ABSTRACT FROM PUBLISHER]

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers. [ABSTRACT FROM PUBLISHER]

We investigate the recombination of discrete-time envelope and phase/frequency components of a polar transmitter, which is based here on an all-digital phase-locked loop (ADPLL) with wideband modulation capability and a digitally controlled power amplifier (DPA). A unified discrete/continuous-time analysis is introduced for the development of the interpolative transfer characteristics of the envelope and phase paths that allows their recombination to be studied in the continuous-time domain of the DPA radio-frequency output. The nonlinear recombination of the polar components in the DPA is analytically investigated in the context of a proposed characterization technique that utilizes single-tone envelope and phase signals, and conclusions on the optimal architecture of a wideband ADPLL-based polar transmitter are drawn. The harmonic distortion results obtained in the context of the proposed characterization technique effectively highlight the performance of the polar transmitter when it is driven with the wideband baseband envelope and phase-modulating signals of today's high-data-rate digital communication systems, such as wideband code-division multiple access and beyond. [ABSTRACT FROM PUBLISHER]

A polar modulator for wireless RF transmitters nonlinearly transforms complex-valued Cartesian baseband modulating signal into amplitude and phase components of the polar coordinate representation before they are recombined in a power amplifier. The resulting explosion in the bandwidth requirements of the polar components can so far be only tolerated for narrowband transmitters, such as EDGE of the 2G cellular. To enable polar topology for wideband transmitters, we propose a technique that alters the signal trajectory such that it avoids crossing (and proximity) of the constellation origin. The resulting substantial decrease of the polar modulator bandwidth is traded off against slight increase of in-band modulation distortion and adjacent channel leakage. We illustrate effectiveness of this method using wideband CDMA (WCDMA) of the 3G cellular. The technique is first mathematically analyzed for various tradeoffs followed by high-level modeling and simulation results. Since the technique is fully contained in the digital domain, its performance effects on the entire RF transmitter can be accurately simulated. A digital architecture to implement the proposed technique is also presented. [ABSTRACT FROM PUBLISHER]

A novel simulation technique that uses an events driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process. [ABSTRACT FROM AUTHOR]