Search

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

This paper presents a high-voltage emission driver chiplet for inorganic micro-pixelated light-emitting-diode ($\mu $ LED) displays in a standard 0.18- $\mu \text{m}$ CMOS technology. Different from the conventional driving scheme of the active-matrix organic light-emitting-diode display, which places the scan drivers and emission drivers at the panel bezels, the CMOS driver chiplets are proposed to sit on the glass substrate among $\mu $ LEDs. The high-voltage swing buffers in the CMOS chiplet are used to drive the low-temperature poly-silicon thin-film transistors on glass backplane to enable the emission control of 300 $\mu $ LEDs. A single CMOS chiplet has 20 output channels, each offering 16M-color depth with 256 grey levels realized by an 8-bit digital-to-analog converter. The maximum channel current is 247 $\mu \text{A}$ and the TFT-gate-driving voltage is 15 V. [ABSTRACT FROM AUTHOR]

The real-time estimation of the AC power system equivalent parameters enables the grid-connected Voltage Source Converter (VSC) to achieve more effective stability control during a short-circuit fault. In this paper, a novel Thevenin Equivalent (TE) parameter estimation method based on local synchronous Phasor Measurement Units (PMUs) is proposed and applied to the Phase-Locked Loop (PLL) synchronization stability control of VSC. First, the relationship between the variation of the measured voltage and the error of the estimated impedance is strictly derived based on the rules of norm inequality. Then, according to the analysis of the upper bound of the system voltage change, a voltage threshold is proposed to select the PMU measurements to ensure the accuracy of the estimation during the large disturbance. Finally, using the estimated TE parameters, the current control instruction of VSC during the fault is calculated in real-time to ensure a synchronous and stable operation. The simulations reveal that the proposed estimation method can accurately track the TE parameters after a fault. Furthermore, the associated current control actions during a fault can ensure the PLL synchronization stability of VSC. [ABSTRACT FROM AUTHOR]

The installation of a ground energy storage system (ESS) in the substation can improve the recovery and utilization of regenerative braking energy. This paper proposes an energy management strategy (EMS) of adaptive threshold adjustment for ground ESS. In this regard, this paper analyzes the energy flow in traction power supply system (TPSS) with different headways and no-load voltage. According to the influence of charge and discharge threshold on the energy flow in TPSS, the laws of energy flow are formulated. Subsequently, an EMS based on fuzzy logic control (FLC) is designed. The proposed EMS is adaptive to the variation of headway and no-load voltage. By monitoring the charge-discharge effect of ESS and the variation of substation output energy within two adjacent periods, the charge-discharge threshold is adjusted adaptively to guarantee the recovery effect of regenerative braking energy. Finally, the simulation and field experiment of proposed EMS are carried out with ground energy storage device and actual line conditions of Beijing Batong line. The experiment results indicate the good performance of proposed EMS in terms of energy saving. [ABSTRACT FROM AUTHOR]

Prolonged voltage level reduction caused by the fault induced delayed voltage recovery (FIDVR) event may lead to a decrease in distance relays security. Therefore, some distance relays are prone to mal-operation under severely prolonged depressed-voltage conditions, and their security should be considered in the FIDVR event studies. The present paper investigates the possible operation of distance relay during the FIDVR event and proposes an auxiliary protection algorithm to effectively prevent its mal-operation during short-term dynamic voltage transient. The proposed algorithm estimates the critical time and voltage level at which the impedance trajectory arrives in Zone 3 of the critical relays using the rate of change of the impedance trajectory, relay margin index, and time-variant NERC/WECC severity indices. Then, the critical voltage is compared with the expected voltage level at the estimated critical time calculated by piecewise cubic spline interpolation (PCSI) method and three consecutive voltage phasors to decide about the block of relays which entering the impedance trajectory to their Zone 3 is probable during the FIDVR event. The efficacy of the proposed method is demonstrated by simulating some short-term voltage transient scenarios on the IEEE 39-bus test system. [ABSTRACT FROM AUTHOR]

The application of wide-band-gap-semiconductors in the power-electric circuit of future traction drives leads to an increased stress on the insulation system. This can cause partial discharge, which leads to a rapid breakdown of the insulation and must, therefore, be avoided. To enhance the durability of the insulation system and to fill up the air gaps between the enameled wires, impregnation material is applied. This leads to an increased partial discharge inception voltage between neighboring conductors as the discharge process only occurs in the remaining air enclosures. Due to the change of the electric field distribution, which is caused by the impregnation material, also the threshold voltage for partial discharge between the stator and the winding changes. While so-called twisted pairs are commonly applied to study the partial discharge behavior of the inter-turn insulation isolated from other effects, in this article a specimen that considers the phase-to-ground insulation is proposed. [ABSTRACT FROM AUTHOR]

This brief presents an NMOS-only voltage reference with small process variations for ultra-low-power applications. All MOSFETs work in the subthreshold region and are biased by the leakage current of the NMOS transistor manufactured in Deep-N-Well (DNW). By fitting the variations of threshold voltage ($\text{V}_{\mathrm{ TH}}$) from slow/fast corners to typical corners linearly, an optimum body selection (OBS) is proposed to reduce the impact of the process variations from $\text{V}_{\mathrm{ TH}}$ or $\Delta \text{V}_{\mathrm{ TH}}$ with the aid of the body effect. The proposed design was fabricated in a 0.18- $\mu \text{m}$ CMOS process, together with a baseline design without using the OBS. Based on the 25-chip measurement results, the output voltage variation of the proposed design is $0.0035 \sigma /\mu $ , which is 61% smaller than that of the baseline design. Besides, for the proposed design with the OBS, the power consumption is 23pW (27°C), while the die area is 0.003mm2. The temperature coefficient is 52ppm/°C in a temperature range from 0°C to 85°C without trimming. The line sensitivity is 0.03%/V, and the power supply rejection ratio is 47dB at 100Hz. [ABSTRACT FROM AUTHOR]

Mixed-cell-height standard cells are prevailingly used in advanced technologies to achieve better design tradeoffs among timing, power, and routability. As feature size decreases, the placement of cells with multiple threshold voltages may violate the complex minimum-implant-area (MIA) layer rule arising from the limitations of patterning technologies. Existing works consider the mixed-cell-height placement problem only during legalization or handle the MIA constraints during detailed placement. In this article, we address the mixed-cell-height placement problem with MIA constraints in two major stages: 1) post-global placement (Post-GP) and 2) MIA-aware legalization. In the Post-GP stage, we first present a continuous and differentiable cost function to address the Vdd/Vss alignment constraints and add weighted pseudonets to MIA-violation cells dynamically. Then, we propose a proximal optimization method based on the given global placement result to simultaneously consider Vdd/Vss alignment constraints, MIA constraints, cell distribution, cell displacement, and total wirelength. In the MIA-aware legalization stage, we develop a graph-based method to cluster cells of specific threshold voltages and apply a strip-packing-based binary linear programming to reshape cells. Then, we propose a matching-based technique to resolve intrarow MIA violations and reduce filler insertion. Furthermore, we formulate inter-row MIA-aware legalization as a quadratic programming problem, which is efficiently solved by a modulus-based matrix splitting iteration method. Finally, MIA-aware cell allocation and refinement are performed to further improve the result. Experimental results show that without any extra area overhead, our algorithm still can achieve 5.4% shorter final total wirelength than the state-of-the-art work. [ABSTRACT FROM AUTHOR]

A digital clock/data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) and a calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1 mm2. For a channel loss of −10.31dB at 10GHz and a 20Gb/s PRBS of $2^{7}-1$ , the measured bit error rate is less than 10−12. By the proposed calibration circuit, the measured high-frequency jitter tolerance is improved. The measured convergence time of the calibration circuit is less than $5~\mu \text{s}$. The power of this CDR circuit is 55.4mW at 20 Gb/s, and the calculated energy efficiency is 2.77pJ/b. [ABSTRACT FROM AUTHOR]

A challenging problem facing AC-Quasi-Steady-State (AC-QSS) cascading failure models of power system is the divergence issue primarily stemming from voltage collapse phenomena. In reality, there are undervoltage load shedding (UVLS) relays, which aim to prevent such a collapse by shedding a pre-specified fraction of load at buses where the corresponding voltages fall below a threshold. However, capturing the UVLS action in QSS models is very difficult, because most of the time the model cannot generate an equilibrium below the voltage threshold due to divergence. To address this problem, current models have applied different variants of uniform load shedding (ULS) till convergence is achieved, which differ from the ground truth. In order to solve this, we propose a methodology that leverages the post-ULS load flow as a starting point when divergence occurs. In this condition, a sensitivity index coupled with the voltage magnitudes of buses is used to recognize the buses that are most prone to voltage collapse. The UVLS scheme is then applied to these buses. To verify the accuracy of the results, we also present a suitable dynamic cascade model with appropriate limits and protection details that can selectively capture UVLS action, thereby revealing the proximate ground truth. Predictions of the proposed model are validated against those of the dynamic model for representative cases in IEEE 118-bus system. In addition, results of the proposed model are contrasted with two ULS schemes on the 2383-bus Polish system. [ABSTRACT FROM AUTHOR]

This article presents a new micro-light-emitting diode (LED) pixel circuit driven by the digital pulsewidth modulation (PWM) method, in which the threshold voltage compensation of the driving thin-film transistor (TFT) is included. A scan driver integrated by metal oxide (MO) TFTs is also designed to provide the scan signals for pixel circuits array. A micro-LEDs array with $76\,\, \times $ BBB $\times \,\,78$ and a scan driver with 80 stages are simultaneously fabricated by MO TFTs backplane with back-channel etch (BCE) structure. A respective micro-LED display is consequently realized by a peripheral driving system based on a field-programmable gate array (FPGA), which is used as a core control unit to synchronize the scan signals with the data signals. It is shown that the micro-LED in the pixel circuit can operate at a constant current even at the 5- $\mu \text{s}$ pulsewidth of the emission (EM) signal. The micro-LED display can achieve 256 linear grayscales with an approximately 60 Hz flash rate under the minimum pulsewidth of 40 $\mu \text{s}$ of EM signal. [ABSTRACT FROM AUTHOR]

In this research, deposition rate dependence of 5 nm-thick ferroelectric nondoped HfO2 (FeND-HfO2) formed on Si(100) substrate was investigated. The equivalent oxide thickness (EOT) was decreased from 3.2 nm to 2.8 nm by increasing deposition rate of HfO2 from 5.0 nm/min to 6.0 nm/min. The subthreshold swing (SS) of 107 mV/dec. and saturation mobility $(\mu _{\mathrm{ sat}})$ of 150 cm 2/(Vs) were obtained with deposition rate of 6.0 nm/min. Furthermore, the threshold voltage (VTH) was controllable as the number of identical erase pulse of 4 V/ $1~\mu \text{s}$ , which suggested the ${\mathrm{ V}}_{\mathrm{ TH}}$ control of approximately 10 mV. [ABSTRACT FROM AUTHOR]

This brief proposes a digital LDO (Low DropOut regulator) with a built-in non-linear VCO (Voltage Controlled Oscillator) to achieve both the fast transient response and low power operation. This on-chip VCO generates a clock signal whose frequency is a non-linear symmetric function of the output voltage error. Here, we propose a design technique to realize the symmetric frequency generation with low power consumption. We demonstrate a design example of LDO using our proposed technique in a commercial 65 nm low-power CMOS process. We evaluate the LDO using transistor-level simulation using HSPICE. It achieves 0.03- $11 ~\mu \text{A}$ of quiescent current with an input voltage range of 0.6-1.2 V and an average current efficiency of 99.68% across $50\times $ load range. [ABSTRACT FROM AUTHOR]

Single-phaseauto-reclosing schemes depend on two main characteristics:(i) secondary arc extinction instant (ii) fault type (temporary or permanent). However, secondary arc quenching time greatly varies from no-arc to prolonged-arc generation depending on the secondary arc current and meteorological factors (wind, thermal buoyancy, etc.). Existing solutions face challenges in making reclosing decisions owing to variable secondary arc quenching instant, non-linear arc voltage characteristics, and varying recovery voltage waveform magnitude. To comprehensively address the discussed problems, an approach based on a particle filter algorithm along with a convolutional neural network is developed. Initially, harmonics of compromised phase are online estimated using a particle filter algorithm, and two indices are developed: (i) estimation of the precise moment of secondary arc extinction (ii) fault nature. Then, extensive simulations are carried out with variable arc resistance, line lengths, no-shunt, and shunt configurations to develop a database based on these two indices. Finally, support vector machine, fully connected deep neural network, and the convolutional neural network are applied to the dataset to predict the reclosing decisions. The comparative study of classifiers confirms the effectiveness of the proposed convolutional neural network in terms of overall model and inter-class accuracy under a noisy and noise-free environment. [ABSTRACT FROM AUTHOR]

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates $1.78\times $ better mitigation for multiple input duty cycles compared to the conventional method. [ABSTRACT FROM AUTHOR]

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 μm BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V. [ABSTRACT FROM AUTHOR]

Class-E power amplifiers are widely used in megahertz frequency power conversion systems due to their high efficiency, which can further be enhanced by virtue of wide-bandgap devices such as GaN high-electron-mobility transistors. Here, a GaN-based cross-quadrant mode Class-E amplifier is proposed, which addresses one of the major challenges for such amplifiers, i.e., to achieve both high power and high efficiency with low-voltage-rating devices. By utilizing the reverse conduction of GaN transistors, a cross-quadrant mode Class-E amplifier with small dc-feed inductance is constructed, whose circuit model is derived by virtue of the Laplace transform technique. We demonstrate an experimental prototype operating at 3.11 MHz with a 100-V GaN transistor, achieving an output power of about 6 W with the efficiency being almost 90% when the input voltage is 10 V and the load resistance is 28 $\mathrm{\Omega }$. Compared with conventional Class-E amplifiers, the power conversion capability of the proposed amplifier is increased up to three times from 0.49 to 1.69 with a slight reduction in efficiency. Such cross-quadrant mode amplifiers can be used to improve the power conversion capability and to reduce the peak switch voltage at the same output power level. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

The miniaturization of CMOS have lead to high leakage and process variation at sub-micron technology. Hybrid circuits including CMOS and magnetic tunnel junction (MTJ), a spintronic device have been put forward to conquer aforesaid limitations. MTJs have appeared to be most assuring candidates owing to it’s compatibility with CMOS and almost zero leakage power. In this brief an offset compensating magnetic full adder (OCMFA) (a hybrid circuit of CMOS and MTJ) has been proposed, which compensates the offset voltage occurring due to process variation and mismatch. The proposed OCMFA compensates the offset voltage in the precharge mode by pre-charging the outputs associated with high resistance branch at a higher voltage and that with lower resistance branch at a lower voltage. The asymmetrical pre-charging of output nodes is assisted by the write current, to provide input to MTJs and load connected diodes. Thus, it is robust against process variation and upgrades the performance of MFA. Power, delay, variability, and corner analysis are performed utilizing UMC 40nm CMOS technology kit at the cadence virtuoso platform and the compact model of perpendicular magnetic anisotropy (PMA) MTJ. This brief contributes in the reliability analysis of proposed MFA with the earlier reported MFA. The proposed OCMFA provides 65% lower PDP and shows 84.6% higher reliability as compared to conventional precharge sense amplifier based magnetic full adder (PCSA-MFA). [ABSTRACT FROM AUTHOR]

While the block size of 3-D NAND flash memory increases with the density and capacity, the raw bit-error rates (RBER) of open blocks could be significantly increased. This article conducts a systematic study over reliability issues caused by open blocks, and reports several new observations. We found that the reliability degradation, due to long open time in writing a block, could happen over all layers in a 3-D NAND block, even after the block is closed. To address the reliability issues of open blocks, this article first proposes to adaptively allocate active blocks to serve write requests based on the workload characteristics for open time reduction. We then propose a partial-block refreshing strategy to alleviate the amplified RBER variations in open blocks and, thus, avoid unnecessary refreshing operations in low-RBER layers. Experimental results show that the proposed method can reduce the RBER by 43% through the reduction of the open time by 28% on average, and reduce the extra write operations for refreshing by 23% on average. [ABSTRACT FROM AUTHOR]

Multilevel cell (MLC) NAND flash memory uses the voltages of the memory cells to represent bits, but high voltages cause much more damage on the cells than low voltages. Free space in MLC can be leveraged to reduce the usage of the high voltages and thus extend the lifetime of MLC. However, limited by the conventional data representation rule that represents bits by the voltage of one single cell, the high voltages are used in a high probability. To fully explore the potential of the free space on reducing the usage of high voltages without changing the total density of MLC, we propose a novel data representation aware of damage, named DREAM. DREAM uses the low voltage combinations of multiple cells instead of the voltage of one single cell to represent bits. It enables to represent the same bits through flexibly replacing the high voltages in some cells with the low voltages in other cells when free space is available. Hence, high voltages which cause more damage are less used and the lifetime of the MLC memory is extended. In addition, complementary techniques are proposed to mitigate performance loss induced by DREAM. Theoretical analysis and simulation results demonstrate the effectiveness and efficiency of DREAM. [ABSTRACT FROM AUTHOR]

In this brief an original scheme, exploiting the trans-conductive loop implemented through the bulk terminal of the PMOS transistors of cross-coupled charge pumps, is proposed to achieve the regulation of the output voltage of a charge pump. As compared to the conventional regulation schemes, the proposed one achieves wide regulation ranges in terms of input voltage and clock frequency, while achieving low circuit complexity. The solution is theoretically analyzed and exploited in a design example implemented in a 130-nm CMOS process and supplied by a single silicon photovoltaic cell. Experimental results show the effectiveness of the proposed regulation scheme when operating around the maximum power point. It provides a simple and effective solution with good performance in terms of line and load regulation, equal to $107\mu \text{V}$ /mV and 3.97 mV/ $\mu \text{A}$ , respectively, a power conversion efficiency of about 65% and an outstanding power density of 83 $\mu \text{W}$ /mm2. [ABSTRACT FROM AUTHOR]

In the mm-wave frequency band, the rectifier’s sensitivity is the bottleneck of a wireless-powered IoT transponder’s distance. At a meter’s distance, the received power is weak, and transistors in a front end of a wireless power receiver operate in the weak inversion region. This article presents a mathematical analysis of the mm-wave multi-stage rectifier in the low-power region. A design methodology of a 57–64-GHz fully integrated eight-stage rectifier with a bulk-drain connection in 40-nm CMOS technology is presented. Parasitic effects on a multi-stage rectifier are analyzed. Based on the analysis, an intrinsic threshold voltage modulation is applied to improve the sensitivity. A tree-type power splitter is also proposed for the RF power signal’s phase balance. With this method, the RF signal arrives at each stage with an equal phase, and its suppression at the output is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm input sensitivity at 57 GHz with 1-V dc output voltage. The overall sensitivity from 57 to 64 GHz is better than −4.5 dBm. Compared to other mm-wave silicon-based rectifier state of the arts, the proposed mm-wave rectifier achieves better sensitivity while maintaining a compact size. [ABSTRACT FROM AUTHOR]

Owing to the effect of data retention noise in multi-level-cell NAND flash memory, the initial threshold-voltage distributions and read voltages can no longer be used to accurately calculate log-likelihood ratios (LLRs) as the retention time increases, thus causing retention errors. To solve this problem, we first utilize the so-called “correction factors” to optimize the LLR accuracy by maximizing the achievable rate of a flash-memory system without introducing extra memory-sensing operations. We further prove that the optimization of the correction factors is a convex optimization problem and can be solved analytically. To obtain the optimal correction factors, we propose two retention-error correction schemes, referred to as offline maximum-achievable-rate correction (MARC) algorithm and online MARC algorithm, which enable the flash-memory controller to utilize the corrected LLRs that are stored in a look-up table and correct the inaccurate LLRs in real time, respectively. Motivated by the variation characteristics of the threshold-voltage distributions, we also propose an enhanced expectation–maximization (EM) algorithm to reestimate their corresponding parameters, and then adjust the read voltages. By combining the enhanced EM algorithm with the MARC algorithms, an enhanced EM-based correction strategy is developed to further boost the retention-error endurance of flash memory while avoiding excessive memory-sensing overhead. Theoretical analyses and simulation results illustrate the superiority of the proposed correction mehtods in terms of the robustness against retention errors. [ABSTRACT FROM AUTHOR]

This article presents a self-configurable and self-poweredactive rectifier that operates from 0.25–20 V for energy harvesting applications. The proposed circuit self-startups from a low voltage using a charge pump and amplifies the voltage with a voltage doubler topology to provide succeeding circuits such as boost converters with a higher voltage. When the voltage of the energy harvester reaches a high threshold, the circuit switches its topology to a full-wave rectifier that does not amplify the voltage. The start-up circuit can limit its voltage intake to prevent boosting the high voltage, which may damage the whole circuit. Comparators with a maximum operating voltage of 5.5 V used in the implementation of the rectifier are protected by a diode and resistor based circuit. A piezoelectric energy harvester (PEH) that has a wide open-circuit voltage of 0.4–15 V under the acceleration of 0.04–0.3 g was used to test the circuit. The experiment results showed the rectifier can startup from 0.25 V and switch its topology according to the PEH voltage. The voltage and power conversion efficiencies are over 90% in most cases. [ABSTRACT FROM AUTHOR]

This brief proposes an ultra-low-power current reference in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back-gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/°C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a temperature range of −30°C to 70°C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. [ABSTRACT FROM AUTHOR]

HfO2-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of HfO2 degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage (VTH) states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of VTH states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness (tFE) from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing tFE makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in VTH are reduced for BG read on reducing tFE, which allows us to hold the same number of states even at such a scaled thickness. Finally, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled tFE. We demonstrate that dual-port FeFET with BG read and scaled tFE offers MLC storage of 3 bits. [ABSTRACT FROM AUTHOR]

The influence of SiO2 and SiNx capping layer on threshold voltage (${V}_{t}$) for FinFET with TiAl-based metal gate (MG) is studied. After metal gate-stack formation, SiNx capping is revealed to be able to serve as a new N source, resulting in the diffusion of N into the effective work function (EWF) TiNx layer. Correspondingly, the accumulation of N in the TiNx layer is demonstrated to be able to lower the EWF for both n- and p-FinFETs. Compared to SiO2 capping, SiNx capping can induce $\sim 100$ –150 mV ${V}_{t}$ lowering for short n- and p-FinFETs. No obvious ${V}_{t}$ shift is found for long-channel devices. [ABSTRACT FROM AUTHOR]

This article proposes a new driving scheme based on an n-type low-temperature polycrystalline silicon (LTPS) four-transistor-two-capacitor (4T2C) pixel circuit to improve the quality of motion images of active matrix organic light-emitting diode (AMOLED) displays. The proposed driving scheme can prevent the effect of the lateral leakage current flowing through the OLED common layer by keeping the pixels in the upper and lower row lines in a nonemitting hold period during the program period. The simulation results show that all RGB colors maintain a shooting amount ratio (SAR) below 1% from the first frame when the image is switched from black to white, even for a concentration of the high p-doped hole transport layer (p-HTL). In addition, the parasitic capacitances of the 4T2C pixel circuit that causes OLED current errors are thoroughly analyzed for high luminance uniformity. A 1.5-in 326 pixels per inch (PPI) AMOLED panel based on the proposed driving scheme was fabricated. The results of our measurements show that the SARs of RGB colors are 0.8%, 0.2%, and 0.9%, respectively, and the average ${x}$ -coordinate shift of the color is 0.007 during the transition between black and white images due to the effective suppression of the lateral leakage current. Therefore, we demonstrate that the proposed driving scheme is suitable for AMOLED displays that require high-quality motion images. [ABSTRACT FROM AUTHOR]

In recent years, NAND flash memory has been widely used in mobile devices, laptops, desktops, and data center storage systems due to its low-power consumption, high performance, high density, lightweight, shock resistance, and high-reliability natures. However, as the stacked layers and the storage density increase, flash memory also suffers from a higher raw bit error rate (RBER) and shorter lifetime. Observing that reliable cell states suffer from less data retention errors and program disturbance, we propose a differential evolution coding scheme to increase the probability of storing data in more reliable cell states, thereby reducing the RBER. We conducted the experiments over a development platform of SSD storage device with 3D-TLC charge trap (CT) NAND flash memory. The experimental results showed that the proposed differential evolution algorithm with asymmetric coding scheme could averagely reduce RBER by 48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, asymmetric coding algorithm, asymmetric coding scheme with stripe-pattern elimination algorithm, UAC- $n$ LC, word-line batch score modulation programming, and SCB schemes. [ABSTRACT FROM AUTHOR]

FPGAs are increasingly becoming sensitive to aging effects mainly through BTI phenomena in the latest technology nodes. This phenomenon can be modeled as a shift in the threshold voltage of transistors which leads to performance degradation and reduction in SNM of SRAM cells. To reduce the aging effects on FPGA building blocks, we propose FIFA, a fully invertible FPGA architecture. In this architecture, two small modules are introduced to make the bitstream of logic and routing resources of the FPGA tiles fully invertible. Accordingly, to insert recovery cycles in the lifetime of the transistors, the bitstream stored in the configuration SRAM cells can be inverted occasionally without any changes in the functionality of the design. Using the proposed architecture, it is neither required to repeat the placement and routing procedures to generate multiple configuration bitstreams, nor extra memory is needed to save alternative bitstreams for changing the SRAM cells’ contents. Our experimental results over a set of industrial benchmarks show that by choosing an appropriate switch block arrangement and an optimized flipping frequency, the proposed architecture can improve the aging induced performance degradation by up to 62.5% with acceptable power and area overheads on logic and routing resources. [ABSTRACT FROM AUTHOR]

In this study, the electrical characteristics of top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress (PBS) are investigated. Abnormal two-step degradation and hump effects are observed under PBS. When the self-aligned process is applied during the interlayer dielectric (ILD) deposition, $\text{n}^{+}$ IGZO is formed by hydrogen doping to define the source and drain, which is accompanied by hydrogen diffusion not only into the channel to influence the initial electrical performance but also into the gate insulator (GI), which leads to the degradation under PBS. The diffusion distance in the length and width directions is calculated. Also, the differences in the diffusion distance in the width and length directions can be ascribed to the geometric structure of the top-gate a-IGZO TFTs. The hump occurs after PBS because of the impact of hydrogen diffusion in the width direction. The two-step degradation and its sequences can be ascribed to two mechanisms, including electron trapping and hydrogen diffusion. [ABSTRACT FROM AUTHOR]

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (${V}_{\text {side}}$). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (${V}_{t}$) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm $\times $ 78 nm (width $\times $ length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and ${V}_{t}$ increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. ${V}_{t}$ can be adjusted from ~0.3 to ~1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using ${V}_{\text {side}}$. This high level of tunability allows electronic control of ${V}_{t}$ and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (<10−13 A). [ABSTRACT FROM AUTHOR]

A new deep learning (DL)-based parameter extraction method is presented in this brief; 50k training cases are generated by Monte Carlo simulations of these preselected parameters in Berkeley short-channel IGFET model (BSIM)-common multigate (CMG). DL models are trained using backward propagation with ${C} _{\text {gg}} - {V} _{g}$ and ${I} _{d} - {V} _{g}$ as the input and selected BSIM-CMG parameters as the output. A TCAD simulated FinFET device, calibrated to Intel 10-nm node, is used to test the DL models. The DL-based parameters extraction results show an excellent fit to capacitance and drain current data, with 0.16% rms error in ${C} _{\text {gg}} - {V} _{g}$ and 6.1% rms error in ${I} _{d} - {V} _{g}$ (0.69% rms error in above-threshold-voltage ${I} _{d} - {V} _{g}$), respectively. In addition, devices with a 10% variation in gate length and oxide thickness are successfully modeled with the trained DL model. The results show tremendous promise in using the DL-based models for parameter extraction. [ABSTRACT FROM AUTHOR]

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. [ABSTRACT FROM AUTHOR]

This article presents a new uncompensated analog pulsewidth modulation (PWM) pixel circuit employing pull-up control for micro-light-emitting diode (LED) display. The time of emitting light for the micro-LED working at the constant current is modulated by the analog data voltage. A compensated pixel circuit is also further developed to improve the display uniformity by compensating the threshold voltage shift of PWM thin-film transistor (TFT) and driving TFT. Based on the back-channel etch (BCE) metal oxide TFTs process, $16\times $ GGG $\times29$ LED array with the uncompensated pixel circuit and 16 $\times {G}\,\,\times15$ LED array with the compensated pixel circuit are simultaneously fabricated on the same glass substrate. Compared with the uncompensated pixel circuit array, the display uniformity of the compensated pixel circuit array is improved from 74% to 88%. [ABSTRACT FROM AUTHOR]