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The code base of system software is growing fast, which results in a large number of vulnerabilities: for example, 296 CVEs have been found in Xen hypervisor and 2195 CVEs in Linux kernel. To reduce the reliance on the trust of system software, many researchers try to provide trusted execution environments (TEEs), which can be categorized into two types: non-privileged TEEs and privileged TEEs. Non-privileged TEEs (e.g., Intel SGX) are extensible, but cannot protect security services like virtual machine introspection (VMI) due to the lack of system-level semantics. On the contrary, privileged TEEs (e.g., the secure world of ARM TrustZone) have system-level semantics, but any additional service implemented in the privileged TEE directly increases the TCB of the entire system. In this article, we propose a new design of TEE to support system-level security services and achieve better extensibility with a small TCB. Each TEE instance of the proposed design is named a Colony. Specifically, we introduce a secure monitor for isolation and capability management. Each Colony is assigned capabilities to access only necessary system-level semantics. We use the new TEE to build four security services, including secure device accessing, VMI tools, a system call tracer, and a much more complex service to virtualize ARM TrustZone with multiple Colonies. We have implemented the system on ARMv7 and ARMv8 platforms, in Xen hypervisor and Linux kernel, and perform a detailed evaluation to show its efficiency. 1. This paper is an extended version of the conference paper published in USENIX Security’17: vTZ: Virtualizing ARM TrustZone. A brief summary of differences is in Section. [ABSTRACT FROM AUTHOR]

In this special section we bring you a practice and experience effort in reproducibility for large-scale computational science at SC20. This section includes nine critiques, each by a student team that reproduced results from a paper published at SC19, during the following year’s Student Cluster Competition. The paper is also included in this section and has been expanded upon, now including an analysis of the outcomes of the students’ reproducibility experiments. Lastly, this special section encapsulates a variety of advances in reproducibility in the SC conference series technical program. [ABSTRACT FROM AUTHOR]

Long period digital random sequence plays an important role in reliable communications and high security scenarios. This paper improved the method of generating long period digital random sequences based on the Residue Number System (RNS) and the Chinese Remainder Theorem (CRT), and a sequence mapping method after CRT extension. This paper proves that the period of sequence after mapping will not degenerate if the modulus used in the mapping stage is coprime with the period of the original sequence. By using the parallelism of RNS, the proposed method can generate sequences at high speed with fewer hardware resources. The NIST test results show that the pass rate of each test item is above 98.40%, which meets the NIST test confidence requirements, confirming the randomness of the generated sequences. An image encryption test is given as one of the example applications of the generated sequences. On the theoretical basis, by jointly optimizing the sequence mapping and iteration procedure, a hardware implementation architecture is also presented in this paper. The implementation is based on Xilinx XC7Z020CLG484-3 FPGA and compared with the implementations of classical chaotic maps. The results show that the proposed architecture has longer sequence period with less hardware resource consumption and higher generation speed and is more general. Meanwhile, the proposed architecture has fast phase switching ability, which is about 10 clock periods. This is one of the key attributes when the sequence is used in communication systems. [ABSTRACT FROM AUTHOR]

In this paper, a simple yet effective network pruning framework is proposed to simultaneously address the problems of pruning indicator, pruning ratio, and efficiency constraint. This paper argues that the pruning decision should depend on the convolutional weights, and thus proposes novel weight-dependent gates (W-Gates) to learn the information from filter weights and obtain binary gates to prune or keep the filters automatically. To prune the network under efficiency constraints, a switchable Efficiency Module is constructed to predict the hardware latency or FLOPs of candidate pruned networks. Combined with the proposed Efficiency Module, W-Gates can perform filter pruning in an efficiency-aware manner and achieve a compact network with a better accuracy-efficiency trade-off. We have demonstrated the effectiveness of the proposed method on ResNet34, ResNet50, and MobileNet V2, respectively achieving up to 1.33/1.28/1.1 higher Top-1 accuracy with lower hardware latency on ImageNet. Compared with state-of-the-art methods, W-Gates also achieves superior performance. [ABSTRACT FROM AUTHOR]

This article reproduces the results of the Supercomputing 2019 article, MemXCT: Memory-Centric X-ray CT Reconstruction with Massive Parallelization by Hidayetoğlu et al. as part of the Supercomputing 2020 Student Cluster Competition Reproducibility Challenge. We reproduce the single CPU-GPU performance experiments and the strong scaling experiments and compare the results to the original article. Although we are not able to use the exact HPC system from the original article, we use similar hardware and configurations to recreate the original environment in Microsoft Azure Cloud services. We were not able to demonstrate exact performance characteristics from the original article due to hardware limitations in our environment, but we are able to reproduce similar performance trends for both single-node and scaling experiments. [ABSTRACT FROM AUTHOR]

The paper studies a reconfigurable intelligent surface (RIS)-assisted multi-user uplink massive multiple-input multiple-output (MIMO) system with imperfect hardware. At the RIS, the paper considers phase noise, while at the base station, the paper takes into consideration the radio frequency impairments and low-resolution analog-to-digital converters. The paper derives approximate expressions for the ergodic achievable rate in closed forms under Rician fading channels. For the cases of infinite numbers of antennas and infinite numbers of reflecting elements, asymptotic data rates are derived to provide new design insights. The derived power scaling laws indicate that while guaranteeing a required system performance, the transmit power of the users can be scaled down at most by the factor $\frac{1}{M}$ when $M$ goes infinite, or by the factor $\frac{1}{MN}$ when $M$ and $N$ go infinite, where $M$ is the number of antennas and $N$ is the number of the reflecting units. Furthermore, an optimization algorithm is proposed based on the genetic algorithm to solve the phase shift optimization problem with the aim of maximizing the sum rate of the system. Additionally, the optimization problem with discrete phase shifts is considered. Finally, numerical results are provided to validate the correctness of the analytical results. [ABSTRACT FROM AUTHOR]

This report analyzes the reproducibility of the article “Computing Planetary Interior Normal Modes with A Highly Parallel Polynomial Filtering Eigensolver” by Jia Shi et al. (Shi, 2018). To reproduce the results we perform different weak and strong scaling studies using a series of Mars models. All experimental runs were performed during the SC19 Student Cluster Competition on a four node Intel Skylake cluster. We show that the findings of the original article can be reproduced in a different environment. [ABSTRACT FROM AUTHOR]

Spectre attacks can be catastrophic and widespread because they exploit common design flaws caused by the speculative capabilities in modern processors to leak sensitive data through side channels. Completely fixing the problem would require a redesign of the architecture for transient execution or the implementation of a new design on re-configurable hardware. However, such fixes cannot be backported to old machines with fixed hardware design. Completely replacing those machines will take a long time. Moreover, existing software patches may cause significant performance overhead. This paper proposes to detect Spectre by monitoring deviations in microarchitectural events using hardware performance counters with promising accuracy above 90 percent under a variety of workload conditions. However, the attacker may attempt to evade detection by slowing down the attack or mimicking benign programs. This paper thus compares different evasion strategies quantitatively and demonstrates that it is possible for the attacker to avoid detection when operating the attacks at a lower speed while maintaining a reasonable attack success rate. Then, we show that, in order to resist evasion, the original detector must be enhanced by randomly switching between a set of detectors using different features and sampling periods so we can keep the detection accuracy above 80 percent. [ABSTRACT FROM AUTHOR]

Versatile video coding (VVC) is the next generation video coding standard released in July 2020. VVC introduces new coding tools enhancing the coding efficiency compared to its predecessor high efficiency video coding (HEVC). These new tools have a significant impact on the VVC software decoder with a complexity estimated to two times HEVC decoder complexity. In particular, the adaptive loop filter (ALF) introduced in VVC as an in-loop filter increases both the decoding complexity and memory usage. These concerns need to be carefully addressed regarding the design of an efficient hardware implementation of a VVC decoder. In this paper, we present an efficient hardware implementation of the ALF tool for VVC decoder. The proposed solution establishes a novel scanning order between Luma and Chroma components that reduces significantly the ALF memory. The design takes advantage of all ALF features and establishes an unified hardware module for all ALF filters. The design uses 26 regular multipliers in a pipelined architecture with a fixed throughput of 2 pixels/cycle and fixed system latency regardless of the selected filter. This design operates at 600 MHz frequency enabling to decode on ASIC platform a 4K video at 30 frames per second in 4:2:2 chroma sub-sampling format. [ABSTRACT FROM AUTHOR]

This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder. [ABSTRACT FROM AUTHOR]

Malicious software, popularly known as malware, is widely acknowledged as a serious threat to modern computing systems. Software-based solutions, such as anti-virus software (AVS), are not effective since they rely on matching patterns that can be easily fooled by carefully crafted malware with obfuscation or other deviation capabilities. While recent malware detection methods provide promising results through an effective utilization of hardware features, the detection results cannot be interpreted in a meaningful way. In this paper, we propose a hardware-assisted malware detection framework using explainable machine learning. This paper makes three important contributions. First, we theoretically establish that our proposed method can provide an interpretable explanation of classification results to address the challenge of transparency. Next, we show that the explainable outcome through effective utilization of hardware performance counters and embedded trace buffer can lead to accurate localization of malicious behavior. Finally, we have performed efficiency versus accuracy trade-off analysis using decision tree and recurrent neural networks. Extensive evaluation using a wide variety of real-world malware dataset demonstrates that our framework can produce accurate and human-understandable malware detection results with provable guarantees. [ABSTRACT FROM AUTHOR]

Versatile Video Coding (VVC) is the next generation video coding standard finalized in July 2020. VVC introduces new coding tools enhancing the coding efficiency compared to its predecessor High Efficiency Video Coding (HEVC). These new tools have a significant impact on the VVC software decoder complexity estimated to 2 times HEVC decoder complexity. In particular, the transform module includes in VVC separable and non-separable transforms named Multiple Transform Selection (MTS) and Low Frequency Non-Separable Transform (LFNST) tools, respectively. In this paper, we present an area-efficient hardware architecture of the inverse transform module for a VVC decoder. The proposed design uses a total of 64 regular multipliers in a pipelined architecture targeting Application-Specific Integrated Circuit (ASIC) platforms. It consists in a multi-standard architecture that supports the transform modules of recent MPEG standards including Advanced Video Coding (AVC), HEVC and VVC. The architecture leverages all primary and secondary transforms’ optimisations including butterfly decomposition, coefficients zeroing and the inherent linear relationship between the transforms. The synthesized results show that the proposed method sustains a constant throughput of 1 sample per cycle and a constant latency for all block sizes. The proposed hardware inverse transform module operates at 600 MHz frequency enabling to decode in real-time 4K video at 30 frames per second in 4:2:2 chroma sub-sampling format. The proposed module has been integrated in an ASIC UHD decoder targeting energy-aware decoding of VVC videos on consumer devices. [ABSTRACT FROM AUTHOR]

In this paper, approximate Versatile Video Coding (VVC) fractional interpolation (FI) filters are proposed. The proposed approximate VVC FI filters reduce computational complexity of VVC FI at the expense of very small quality loss. In this paper, four VVC FI hardware implementing the proposed approximate VVC FI filters are also proposed. The proposed approximate VVC FI hardware have higher speed, smaller area, and up to 51% lower power consumption than the exact VVC FI hardware. Therefore, they can be used in consumer electronics devices requiring high speed, small area, low power consuming VVC encoder hardware. [ABSTRACT FROM AUTHOR]

Reconfigurable intelligent surface (RIS) is regarded as a promising technology with great potential to boost wireless networks. Affected by the “double fading” effect, however, conventional passive RIS cannot bring considerable performance improvement when users are not close enough to RIS. Recently, active RIS is introduced to combat the double fading effect by actively amplifying incident signals with the aid of integrated reflection-type amplifiers. In order to reduce the hardware cost and energy consumption due to massive active components in the conventional fully-connected active RIS, a novel hardware-and-energy efficient sub-connected active RIS architecture has been proposed recently, in which multiple reconfigurable electromagnetic elements are driven by only one amplifier. In this paper, we first develop an improved and accurate signal model for the sub-connected active RIS architecture. Then, we investigate the joint transmit precoding and RIS reflection beamforming (i.e., the reflection phase-shift and amplification coefficients) designs in multiuser multiple-input single-output (MU-MISO) communication systems. Both sum-rate maximization and power minimization problems are solved by leveraging fractional programming (FP), block coordinate descent (BCD), second-order cone programming (SOCP), alternating direction method of multipliers (ADMM), and majorization-minimization (MM) methods. Extensive simulation results verify that compared with the conventional fully-connected structure, the proposed sub-connected active RIS can significantly reduce the hardware cost and power consumption, and achieve great performance improvement when power budget at RIS is limited. [ABSTRACT FROM AUTHOR]

The overhead of memory virtualization remains nontrivial. The traditional shadow paging (TSP) resorts to a shadow page table (SPT) to achieve the native page walk speed, but page table updates require hypervisor interventions. Alternatively, nested paging enables low-overhead page table updates, but utilizes the hardware MMU to perform a long-latency two-dimensional page walk. This paper proposes new memory virtualization solutions based on hardware (machine) mode—the highest CPU privilege level in some architectures like Sunway and RISC-V. A programming interface, running in hardware mode, enables software-implementation of hardware support functions. We first propose Software-based Nested Paging (SNP), which extends the software MMU to perform a two-dimensional page walk in hardware mode. Second, we present Swift Shadow Paging (SSP), which accomplishes page table synchronization by intercepting TLB flushing in hardware mode. Finally we propose Accelerated Shadow Paging (ASP) combining SSP and SNP. ASP handles the last-level SPT page faults by walking two-dimensional page tables in hardware mode, which eliminates most hypervisor interventions. This paper systematically compares multiple memory virtualization models by analyzing their designs and evaluating their performance both on a real system and a simulator. The experiments show that the virtualization overhead of ASP is less than 4.5% for all workloads. [ABSTRACT FROM AUTHOR]

In this paper, we identify that memory performance plays a crucial role in the feasibility and effectiveness for performing denial-of-service attacks on shared cache. Based on this insight, we introduce new cache DoS attacks, which can be mounted from the user-space and can cause extreme worst-case execution time (WCET) impacts to cross-core victims—even if the shared cache is partitioned—by taking advantage of the platform’s memory address mapping information and HugePage support. We deploy these enhanced attacks on two popular embedded out-of-order multicore platforms using both synthetic and real-world benchmarks. The proposed DoS attacks achieve up to 111X WCET increases on the tested platforms. [ABSTRACT FROM AUTHOR]

The papers in this special section explore research on the latest topics related to the hardware acceleration of machine learning. [ABSTRACT FROM AUTHOR]

This paper presents hardware-friendly algorithm for Gini-index (GI) cooperative-spectrum-sensing (CSS) algorithm for the data-fusion based cooperative cognitive-radio network. It simplifies the complex computations of sample-covariance-matrix (SCM) elements and test-statistics value of the conventional GI-based CSS algorithm. It delivers excellent detection performance under the realistic scenario of non-uniform dynamical noise and signal-power. Based on GI-based CSS algorithm, three different VLSI architectures are proposed for the cooperative spectrum sensor (CSR): CSR-VLAR1, CSR-VLAR2, and CSR-VLAR3. Here, CSR-VLAR1 is the first-time reported CSR-architecture for the conventional GI-based CSS algorithm. Subsequently, CSR-VLAR2 represents hardware-architecture of the proposed hardware-friendly GI-based CSS algorithm. Eventually, additional architectural optimization has been applied to CSR-VLAR2 that is transformed into the most hardware-efficient VLSI-architecture of CSR, referred as CSR-VLAR3, which is ASIC chip-fabricated in UMC 130 nm-CMOS technology node. Furthermore, both CSR-VLAR1 and CSR-VLAR2 are synthesized and post-layout simulated in the same technology node. Our ASIC-chip of CSR-VLAR3 occupies 0.35 mm2 of core-area and consumes 8.31 mW of total power at 88.8 MHz of maximum clock frequency, when the supply voltage is 1.2 V. Our CSR ASIC-chip has been functionally verified with the aid of real-world signals, using USRPs and FPGAs based test-setup of cooperative cognitive-radio network. Measured results of our design are compared with reported implementations where the proposed CSR is $4.52\times $ hardware-efficient and $2.8\times $ power-efficient than the state-of-the-art CSR-implementations. Thus, our work addresses the key challenge of designing hardware-efficient CSR that delivers excellent detection performance in the real-world scenario. [ABSTRACT FROM AUTHOR]

This paper proposes a discrete Gaussian sampling hardware design that can flexibly support different sampling parameters, that is more efficient (in area-delay product) compared to the majority of earlier proposals, and that has constant execution time. The proposed design implements a Cumulative Distribution Table (CDT) approach, reduces the table size with Gaussian convolutions, and adopts an innovative fusion tree search algorithm to achieve a compact and fast sampling technique—to our best knowledge, this is the first hardware implementation of fusion tree search algorithm. The proposed hardware can support all the discrete Gaussian distributions used in post-quantum digital signatures and key encapsulation algorithms (FALCON, qTESLA, and FrodoKEM), the homomorphic encryption library of SEAL, and other algorithms such BLISS digital signature and LP public-key encryption. Our proposed hardware can be configured at design-time to optimize a single configuration or at run-time to support multiple Gaussian distribution parameters. Our design, furthermore, has constant-time behavior by design, eliminating timing side-channel attacks—this is achieved by reading all table contents at the same time to also reduce the latency. The results on a Xilinx Virtex-7 FPGA show that our solution can outperform all prior proposals in area-delay product by 1.67–235.88×, only falling short to those designed for the LP encryption scheme. [ABSTRACT FROM AUTHOR]

Targeted stimulation of nervous system has become an increasingly important research tool as well as therapeutic modality, and the stimulation signal acquisition based on the expected signal needs a closed-loop system. Due to the difficulty of biological experiments, the real-time simulation of neural activity is of great significance for the mechanism analysis and the performance improvement of neuromodulation techniques. This paper proposes a real-time hardware experimental platform for closed-loop electrophysiology. The platform integrates a neural computing module and a real-time control module on TMS320F28377D digital signal processors (DSP), and it reserves a programmable interface for users to call the required modules and set module parameters simultaneously. The platform has high compatibility and can be used for closed-loop electrophysiological experiments with different models, different control algorithms and different clamps. We implement the thalamocortical relay neural computing model and iteration improves proportional-integral algorithm on the platform for experimental verification in this paper. The neuron firing waveforms of the DSP platform and the MATLAB R2020b simulation waveforms are consistent. Under the same physiological time, the simulation speed of DSP platform is 3 times faster than that of the Intel Core i5-8400 CPU computer, and the neural firing rate of DSP platform is due to the real-time. This platform can be used as a tool to explore the working mechanism of the nervous system. It may promote the development of neuroscience, especially the field of closed-loop neuroscience. [ABSTRACT FROM AUTHOR]

In this paper, a reliable methodology is proposed in order to implement and validate a Model Predictive Control (MPC) scheme on an actual Voltage Source Converter (VSC) integrated in a scale-down multi-terminal DC grid. The objective of the investigated MPC controller is to enable AC frequency support among two asynchronous AC areas through a High Voltage Direct Current (HVDC) grid, while considering physical constraints, such as maximum and minimum DC voltage. A systematic and accurate implementation strategy is proposed, based mainly on the Hardware In the Loop (HIL) and Power Hardware In the Loop (PHIL), leading to the real-life testing on VSC, controlled by a classical microcontroller. The technical problems during the implementation process, as well as the proposed solutions, are described in detail through this paper. This procedure is deemed valuable to bridge the gap between offline simulation and the actual implementation of such advanced control scheme on experimental test rig. [ABSTRACT FROM AUTHOR]

Terahertz (THz) band communications are envisioned as a key technology for 6G and Beyond. As a fundamental wireless infrastructure, THz communication can boost abundant promising applications. In 2014, our team published two comprehensive roadmaps for the development and progress of THz communication networks, which helped the research community to start research on this subject afterwards. The topic of THz communications became very important and appealing to the research community due to 6G wireless systems design and development in recent years. Many papers are getting published covering different aspects of wireless systems using the THz band. With this paper, our aim is looking back to the last decade and revisiting the old problems and pointing out what has been achieved in the research community so far. Furthermore, in this paper, open challenges and new research directions still to be investigated for the THz band communication systems are presented, by covering diverse topics ranging from devices, channel behavior, communication and networking, to physical testbeds and demonstration systems. The key aspects presented in this paper will enable THz communications as a pillar of 6G and Beyond wireless systems in the next decade. [ABSTRACT FROM AUTHOR]

Millimeter wave (mmWave) and massive MIMO systems are intrinsic components of 5G and beyond. These systems rely on using beamforming codebooks for both initial access and data transmission. Current beam codebooks, however, generally consist of a large number of narrow beams that scan all possible directions, leading to large training overhead. Further, these codebooks do not normally account for hardware impairments or possible non-uniform array geometries, and their calibration process is expensive. To overcome these limitations, this paper develops an efficient online machine learning framework that learns how to adapt the codebook beam patterns to the specific deployment, surrounding environment, user distribution, and hardware characteristics. This is done by designing a novel complex-valued neural network architecture in which the neuron weights directly model the beamforming weights of the analog phase shifters, accounting for the key hardware constraints. This model learns the codebook beams through online and self-supervised training avoiding the need for explicit channel state information. This respects the practical situations where the channel is imperfect or hard to obtain. Simulation results highlight the capability of the proposed solution in learning environment and hardware aware beam codebooks, which reduce the training overhead and improve the robustness against possible hardware impairments. [ABSTRACT FROM AUTHOR]

Intelligent reflecting surface (IRS) has been regarded as a promising and revolutionary technology for future wireless communication systems owing to its capability of tailoring signal propagation environment in an energy/spectrum/ hardware-efficient manner. However, most existing studies on IRS optimizations are based on a simple and ideal reflection model that is impractical in hardware implementation, which thus leads to severe performance loss in realistic wideband/multi-band systems. To deal with this problem, in this paper we first propose a more practical and more tractable IRS reflection model that describes the difference of reflection responses for signals at different frequencies. Then, we investigate the joint transmit beamforming and IRS reflection beamforming design for an IRS-assisted multi-cell multi-band system. Both power minimization and sum-rate maximization problems are solved by exploiting popular second-order cone programming (SOCP), Riemannian manifold, minimization-majorization (MM), weighted minimum mean square error (WMMSE), and block coordinate descent (BCD) methods. Simulation results illustrate the significant performance improvement of our proposed joint transmit beamforming and reflection design algorithms based on the practical reflection model in terms of power saving and rate enhancement. [ABSTRACT FROM AUTHOR]

This article addresses polynomial computation with unipolar stochastic logic by exploiting correlation between the bit-streams. The AND-OR, double-NAND, OR-AND and double-NOR circuits are presented for polynomials with all positive coefficients whose sum is less than or equal to one by mathematically analyzing the joint probability distribution of coefficient bit-streams. The NAND-AND expansion is also developed for polynomials with alternatively positive and negative coefficients whose absolute values are decreasing by applying the same idea. Unlike the original methods with multiple uncorrelated random number sources (RNSs) for coefficient bit-stream generation, the presented methods only require a single RNS. Since the RNSs take up huge hardware resource in stochastic circuits, the proposed RNS-sharing techniques for polynomial computation result in a significant reduction of hardware complexity. For the factorization technique in the general polynomials, this paper enhances the original stochastic designs for the second-order polynomial and further presents the simple correlation-dependent circuits. Results show that the proposed architectures are superior to the previous ones by reducing the total number of RNSs. [ABSTRACT FROM AUTHOR]

Following the Unlimited Sampling strategy to alleviate the omnipresent dynamic range barrier, we study the problem of recovering a bandlimited signal from point-wise modulo samples, aiming to connect theoretical guarantees with hardware implementation considerations. Our starting point is a class of non-idealities that we observe in prototyping an unlimited sampling based analog-to-digital converter. To address these non-idealities, we provide a new Fourier domain recovery algorithm. Our approach is validated both in theory and via extensive experiments on our prototype analog-to-digital converter, providing the first demonstration of unlimited sampling for data arising from real hardware, both for the current and previous approaches. Advantages of our algorithm include that it is agnostic to the modulo threshold and it can handle arbitrary folding times. We expect that the end-to-end realization studied in this paper will pave the path for exploring the unlimited sampling methodology in a number of real world applications. [ABSTRACT FROM AUTHOR]

Pedestrian detection is an important issue in an intelligent transportation system and involves complex hardware architecture. This high complexity and low detection accuracy make it a prompt topic of research. This paper proposes a novel feature extractor with its efficient hardware implementation for the real-time pedestrian detection system. The proposed approach termed here as Histogram of All Significant Gradients (HASG) improves the Histogram of Significant Gradients (HSG) technique by the inclusion of diagonal gradients. The diagonal gradients give an add-on feature which improves the detection accuracy of the detection system. The overhead of extra computation is compensated here by the proposition of a hardware architecture that utilizes only integer computation. The arctangent operation which is a floating-point operation is replaced here by a simplified architecture that uses only integer computation units. The proposed hardware architecture is found to have 73.65% reduced hardware consumption in contrast to the existing one. The complete design is implemented on the Artix-7 FPGA device with a maximum achievable clock frequency of 115 MHz. [ABSTRACT FROM AUTHOR]

Shi et al. (2018) proposed a highly parallel polynomial filtering eigensolver for the computation of planetary normal modes. As a challenge at the Student Cluster Competition in The International Conference for High Performance Computing, Networking, Storage and Analysis (SC19), we reproduce the computational efficiency of the polynomial filtering eigensolver on our Intel Xeon machine. We present the weak scalability, scaling of runtime with model size (in a fixed interval) and the strong scalability results in this report. [ABSTRACT FROM AUTHOR]