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An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

In this article, first integrated circuit (IC) implementation of parallel synchronized switching harvesting on inductor (p-SSHI) is presented for triboelectric energy harvester targeting 1 Hz to 5 Hz mechanical motions. It is accompanied by on-chip buck and switched capacitor DC-DC converters, all capable of handling 70 V levels. Unlike piezoelectric harvesters, triboelectric nanogenerators (TENGs) can produce very high open-circuit voltages; thus, the proposed system utilizes this property within the technology limits to maximize the extracted power. An in-house manufactured TENG using steel and polytetrafluoroethylene (PTFE) is modeled for sub-5 Hz motions. The energy is extracted and stored in an external capacitance until its voltage reaches 70 V, which is achieved in three press-and-release mechanical cycles. 70-to-2 V down conversion is carried on by 70-to-10 V buck converter followed by a 10-to-2 V switched capacitor DC-DC converter. A chip is manufactured in $0.18~\mu \text{m}$ HV BCD process with an active area of 6.25 mm2. End-to-end peak efficiency is measured as 32.71% for 1 Hz motion with a 722 $\mu \text{W}$ total power delivery to the load for 4 ms. [ABSTRACT FROM AUTHOR]