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The article discusses developments and innovations in computer displays that are lighter, more durable, and more flexible than liquid-crystal displays (LCD). The article states that the new technology consists of front planes and back planes. According to the article, front plane technology in the form of electronic paper, also called e-paper, is produced by Massachusetts-based E Ink Corporation, and used in digital book readers such as the Amazon Kindle, Barnes & Noble Nook, and Sony Reader Digital Book. The article describes the other front plane technology called organic light-emitting diodes (OLEDs), which emit light and consume more power than e-paper yet have a higher lumen-per-watt rating. The article also discusses various possibilities in incorporating glass in flexible displays.

The article discusses about electronic paper. The story of electronic paper (e-paper), so far, has proved to be what could be termed techno-hyperenthusiasm. Electronically rewritable paper requires two basic components. A substrate and something electrically controllable that can serve as the ink. If the epaper material has good enough image retention, it can be written by a device analogous to a printer, and then taken out and used just like a normal sheet of paper.

Reports on companies that are pioneering technologies for electronic paper and have prototypes at various stages of development in fall 2000. Details of the rigid indoor display board called Immedia by E Ink Corporation; History of electronic paper; Invention of Nick Sheridon of Xerox's Palo Alto Research Centre (PARC) in California called Gyricon; Research at Kent Displays in Ohio on cholesteric liquid crystals; Outlook.

The article reports that researchers at the New University of Lisbon have discovered a way to make paper into a transistor. Details about the research, conducted by professors Elvira Fortunato and Rodrigo Martins, among others, are presented. The important role that transistors play in electronics is also explored.

This issue includes selected papers presented at the IEEE Asia Pacific Conference of Circuits and Systems (APCCAS) 2018 that was held in Chengdu, China, on 26–30 October 2018 and the IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2018 that was held in Bordeaux, France, on 9–12 December 2018. As the flagship conferences of the IEEE Circuits and Systems Society (CASS) in IEEE Regions 8 and 10, respectively, these conferences welcome contributions across the themes within the scope of the Society, including analog, digital and mixed-signal electronics, signal processing, power electronics, communication theory, sensors, circuit theory, and nonlinear circuits and systems. [ABSTRACT FROM AUTHOR]

The article presents information on a new electronic paper. A technique originally used to cut headlight glare in cars' rear-view mirrors has been adapted to create a new electronic paper display for MP3 players and mobile phones. Called a NanoChromic display (NCD), it was shown operating on a converted iPod by Dublin-based company Ntera Ltd. At the heart of an NCD is a layer of a so-called electrochromic material, which is normally transparent but turns blue when a negative charge is applied. In Ntera's new display, an array of transparent electrodes made of metal oxide semiconductor, mounted on a transparent film, allows it to produce images with a resolution of around 0.25 millimeters, or 100 dots per inch.

This article presents the author's experience on the importance of paper as a storage device. At an annual Demo conference, tablemates and I grappled with a topic on the storage of digital photos. I was using the 5.25-inch floppy disk and I have got lots of files into it. But the only drive I own that will read them is in an ancient, closeted machine that may not even boot. Even in the digital world, good old analog paper gets around all problems. Print out a photo or document and short of flame or water, it is likely to be around for a long time. And as anybody who is flipped through photo albums can attest, a photo is essentially self-documenting. At a break, I noticed another Demo attendee pulling out her paper datebook. This professional had been a Palm fashion victim before she chucked her handheld for paper's directness. Old, reliable, low tech paper beat high-tech electronics again. I have personally returned to paper for things like receipts from Web purchases. Once upon a time, I have saved them as files, but overly clever sites kept conspiring with browser to save the pages incorrectly. And even when the file was okay, it was not always on the machine I happened to have with me so that it could serve as a proof in case of a snafu at a rental car lot or hotel.

Discusses how posting work processes on an intranet offered benefits to a contract electronics manufacturer. How the Process Web intranet system facilitates two-way communication between the manufacturing floor and other areas of the plant; Structure of the Process Web; Potentials of the Process Web.

Recently, there has been significant interest in convex relaxations of the optimal power flow (OPF) problem. A semidefinite programming (SDP) relaxation globally solves many OPF problems. However, there exist practical problems for which the SDP relaxation fails to yield the global solution. Conditions for the success or failure of the SDP relaxation are valuable for determining whether the relaxation is appropriate for a given OPF problem. To move beyond existing conditions, which only apply to a limited class of problems, a typical conjecture is that failure of the SDP relaxation can be related to physical characteristics of the system. By presenting an example OPF problem with two equivalent formulations, this paper demonstrates that physically based conditions cannot universally explain algorithm behavior. The SDP relaxation fails for one formulation but succeeds in finding the global solution to the other formulation. Since these formulations represent the same system, success (or otherwise) of the SDP relaxation must involve factors beyond just the network physics. The lack of universal physical conditions for success of the SDP relaxation motivates the development of tighter convex relaxations capable of solving a broader class of problems. Tools from polynomial optimization theory provide a means of developing tighter relaxations. This paper uses the example problem to illustrate relaxations from the Lasserre hierarchy for polynomial optimization and a related “mixed semidefinite/second-order cone programming” hierarchy. [ABSTRACT FROM AUTHOR]

Provides a listing of the editors, board members, and current staff for this issue of the publication. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

The article presents information on one of the long-awaited multimedia computer systems. The consumer electronics industry wants next year to mark the beginning of the end for print and paper publishing. Instead, it foresees text, pictures, animated graphics, moving video, encyclopedic text and sound-collectively known as multimedia being published on interactive compact discs. Factories will mass-produce the discs for well under 1 pound each, using the same pressing machines as they do for music compact discs. They will come in two sizes, 8 and 12 centimeters, depending on the amount of information they hold. A player, connected to a television screen and a stereo sound system, will unravel the multimedia mix under the control of a simple hand-held unit. There will be mains-powered, tabletop units looking like today's compact disc players, for home and office use.

Continuous phase modulation (CPM) is widely employed in digital communication systems due to its high spectral efficiency. The main digital implementations originate in the well-known ROM-based approach. In this approach, the memory size may be very large and depends completely on the modulation parameters. This means that supporting several modulation types would require a proportional increase on the memory resources. In this paper, a new versatile single $h$ and multi- $h$ CPM transmitter is introduced, which can be reconfigured for handling any kind of CPM waveform without noticeable increase in memory. A complete digital architecture is also provided. This represents a truly reconfigurable CPM transmitter, which can be used for software defined radio platforms. Implementation results show that in data rates of more than 20 Mbps as required by the IRIG-106-15 standard, the proposed approach yields a savings of around 1.5 megabits of memory when compared to the ROM approach, at the expense of requiring 15 multipliers. Additionally, for medium-rate implementations as required in the Bluetooth standard, the proposed transmitter offers a savings of about 50 Kbits of memory while requiring only two multipliers. Simulation results confirm that the signals produced by this new approach match those expected from theoretical analysis. [ABSTRACT FROM AUTHOR]

The evolution of electronics towards compact and highly energy-efficient systems requires joint efforts in developing both innovative system architectures and novel devices. Recent developments show that time-based sensor interfaces yield highly-digital architectures, which are compatible with advanced silicon CMOS at highly-scaled technology nodes. Advancements in CMOS time-based sensor interfaces show that new circuit techniques can help to increase performance and robustness. Furthermore, these architectures have successfully been implemented in carbon nanotube technology, a promising technology to further reduce the energy consumption in electronics. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in CMOS and CNT technologies, allowing for scalable and robust designs. Several CMOS and VLSI-compatible CNFET-based sensor interface circuits have been fabricated and validated through measurements, demonstrating the feasibility of these solutions. [ABSTRACT FROM AUTHOR]

This paper discusses the general control problems of dc/dc converters connected in series at the input. As the input voltage is shared by a number of dc/dc converters, the resulting converter relieves the voltage stresses of individual devices and hence is suitable for high input-voltage applications. At the output side, parallel connection provides current sharing and is suitable for high output-current applications. Moreover, series connection at the output side is also possible, resulting in output voltage sharing. Theoretically, from a power balance consideration, one can show that fulfillment of input-voltage sharing implies fulfillment of output-current or of output-voltage sharing, and vice versa. However, the presence of right-half-plane poles can cause instability when the sharing is implemented at the output side. As a consequence, control should be directed to input-voltage sharing in order to ensure a stable sharing of the input voltage and of the output current (parallel connection at output) or output voltage (series connection at output). In this paper, general problems in input-series connected converter systems are addressed. Minimal control structures are then derived and some practical design considerations are discussed in detail. Illustrative examples are given for addressing these general control considerations. Finally, experimental prototypes are built to validate these considerations. [ABSTRACT FROM AUTHOR]

We are considering the problem of controlling a DC-DC switched power converter of the Buck type. The converter involves an inherent control limitation; accordingly the control signal (duty ratio) can only take values in the interval (0, 1). In the relevant literature, such a physical control limitation is generally not taken into account when designing the converter regulators. This is only dealt with in the control implementation stage, placing an isolated limiter between the (linear) controller and the controlled system. Furthermore, the presence of such a limiter is generally ignored when analyzing the closed-loop control system. In the present paper, the control signal limitation is dealt with using a nonlinear regulator that involves an internal limiter. The resulting closed-loop control system is shown to be equivalent to a nonlinear feedback involving a linear dynamics block in closed-loop with a nonlinear static element. Using absolute stability tools, sufficient conditions are established for the involved feedback to be L2-stable. If these conditions are respected when choosing the control design parameters then the regulator meets its objectives (closed-loop stability and output reference tracking). It is worth noting that, though the focus is made on a specific power converter, the paper includes an important theoretical dimension that may be of general interest. [ABSTRACT FROM AUTHOR]

This paper presents a fully differential capacitance sensor employing the CBCM technique to map differential input capacitances into rail-to-rail differential output voltages. The circuit has been designed for measuring capacitances in the ±25-if range, appropriate for sensing live cells using on-chip microelectrodes. An array architecture based on a shielded current routing bus has been developed for incorporating the capacitance measurement circuit into sensor arrays, with each pixel comprising four minimum-size digital transistors, enabling high-density integration. In addition to improving spatial resolution, the shielded current bus also eliminates the need for individual pixel calibration, conserves sensor evaluation speed, and provides protection from junction leakage. The sensor employs a 3-phase clocking scheme that enables on-chip gain tuning. The paper also presents a modified version of the sensor circuit incorporating floating-gate transistors for mismatch compensation and output offset cancellation, performed using a combination of impact-ionized channel hot electron injection and Fowler-Nordheim tunneling mechanisms. Chips comprising both versions of the sensor circuits in test arrays employing the shielded current routing bus were fabricated in a commercially available 2-poly, 3-metal, 0.5-μm CMOS process. The sensor operation was demonstrated by measuring on-chip test capacitances comprising single and interdigitated metal electrodes, configured using different capacitance compensation schemes. The differential sensor in combination with the shielded current bus exhibits a maximum sensitivity of 200 mV/fF, a resolution of 15 aF, and an output dynamic range of, 65 dB. [ABSTRACT FROM AUTHOR]

In this paper, we consider the problem of out-of-band quantization noise suppression in the general family of direct digital-to-RF (DDRF) conversion circuits, where the RF carrier is amplitude modulated by a quantized representation of the baseband signal. Hence, it is desired to minimize the out-of-band quantization noise in order to meet stringent requirements such as receive-band noise levels in frequency-division duplex transceivers. In this paper, we address the problem of out-of-band quantization noise by introducing a novel signal-processing solution, which we refer to as "segmented filtering (SF)." We assess the capability of the proposed SF solution by means of performance analysis and results that have been obtained via circuit-level computer simulations as well as laboratory measurements. Our proposed approach has demonstrated the ability to preserve the required signal quality and power amplifier (PA) efficiency while providing more than 35-dB attenuation of the quantization noise, thus eliminating the need for substantial post-PA passband RF filtering. [ABSTRACT FROM AUTHOR]

In this paper, we propose an adaptive scheme for the stabilization and synchronization of chaotic Lur'e systems with time-varying delay. Based on the invariant principle of functional differential equations, the strength of the feedback controller is enhanced adaptively to stabilize and synchronize chaotic Lur'e systems. The derivative-constraint that the time-varying delay is required to be differentiable and its derivation is less than one can be removed by using LaSalle-Razumikhin-type theorems. The time-varying delay is allowed to be bounded without any additional constraint or unbounded with derivative-constraint. This method is analytical, rigorous and simple to implement in practice. In addition, it is quite robust against the effect of parameters uncertainty and noise. Two examples are provided to show the effectiveness of the proposed scheme. The results of the paper demonstrate the fruitfulness of the modern feedback and adaptive control theory application to the stabilization and synchronization problems for delayed chaotic systems. [ABSTRACT FROM AUTHOR]

The paper treats an inverse problem posed in the time domain for a circuit described by a stiff system of ordinary differential equations (ODEs). Identification of model parameters (circuit elements) is performed by processing transient characteristics measured in the circuit. An illustrative example discussed throughout the paper shows that reducing the identification problem to curve fitting, which is the most general way, may be hardly used for a stiff model due to a ravine shape of the objective functional. Moreover, a necessity of solving the stiff ODE system to get a functional value makes the inverse problem be practically unsolvable. It has been shown that the initial inverse problem may be simplified significantly by taking into account linear relations which are observed between the experimental characteristics measured for a stiff system. The relation coefficients are discussed in the paper with regard to the accuracy of the approximation. Finally the initial identification problem has been reduced to a nonlinear system of algebraic equations which may be easily solved considering different sensitivity of the relation coefficients to the model parameters. The final solution is presented for different levels of "measurement" error involved in the simulation. [ABSTRACT FROM AUTHOR]

In this paper, we show how quantum Boolean circuits can be used to implement the oracle and the inversion-about-average function in Grover's search algorithm. Before illustrating how this can be done, we present the circuit design principle using the satisfiability (SAT) problem as an example. Then, based on this principle, we show the quantum circuits for two different kinds of applications. The first one is searching a phone book. Although this is a typical example of Grover's algorithm, we show that it is impractical as a real-world application. As the second application, we give the quantum circuits for a more practical application—breaking a symmetric cryptosystem. Although these two applications have quite different types of search criteria, they are both one-way functions and the proposed circuits can actually be generalized to any such problems. In this perspective, we conclude this paper by proposing a template of quantum circuits that is capable of searching the solution of a certain class of one-way functions. [ABSTRACT FROM AUTHOR]

Theoretical treatments forecast that bistable CMOS devices using electronic charge as a state variable will operate at their maximum thermal dissipation limit possibly as early as 2012. The problem is further compounded by increasing manufacturing challenges associated with the ever decreasing logic switch dimensions. These challenges require the development of new fabrication strategies that replace or complement current top-down lithography with bottom-up protocols using controlled self-assembly of nanomaterial building blocks. To answer some of these issues, this paper focuses on a new device paradigm consisting of an arene-metal-arene conformational switch, addressable through capacitive, inductive, or resonant-tunneling field coupling. The operating principle is based on voltage-tunable modulation in quantum electron transmission. The switch is open (OFF) when the metal ion is displaced to a position at a C-H bond on the arene ring due to an externally applied bias. Conversely, when the external bias is removed, the metal ion moves to an axis- symmetric position on the arene ring, and the switch is closed (ON). The paper presents a summary of the architecture, operating principle, and advantages of the conformational switch, along with associated findings from proof-of-concept theoretical and experimental studies of its target specifications and performance. The paper also discusses opportunities and challenges related to the integration of conformational switches into hybrid CMOS-molecular and monolithic (all molecular) circuits. [ABSTRACT FROM AUTHOR]

The rapid development of CMOS and non-CMOS nanotechnologies has opened up new possibilities and introduced new challenges for circuit design. One of the main challenges is in designing reliable circuits from defective nanoscale devices. Hence, there is a need to develop methodologies to accurately evaluate circuit reliability. In recent years, a number of reliability evaluation methodologies based on probabilistic model checking, probabilistic transfer matrices, probabilistic gate models, etc., have been proposed. Scalability has been a concern in the applicability of these methodologies to the reliability analysis of large circuits. In this paper, we develop a general, scalable technique for these reliability evaluation methodologies. Specifically, an algorithm is developed for the model checking-based methodology and implemented in a tool called Scalable, Extensible Tool for Reliability Analysis (SETRA). SETRA integrates the scalable model checking-based algorithm into the conventional computer—aided design circuit design flow. The paper also discusses ways to modify the scalable algorithm for the other reliability estimation methodologies and plug them into SETRA's extensible framework. Our preliminary experiments show how SETRA can be used effectively to evaluate and compare the robustness of different circuit designs. [ABSTRACT FROM AUTHOR]

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ‘elements’, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 × 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays. [ABSTRACT FROM AUTHOR]

A Lyapunov approach to the characterization of forced vibration for continuous-time systems was recently proposed in [12]. The objective of this paper is to derive counterpart results for discrete-time systems. The class of oscillatory input signals to be considered include sinusoidal signals, multitone signals, and periodic signals which can be described as the output of an autonomous system. The Lyapunov approach is developed for linear systems, homogeneous systems (difference inclusions), and nonlinear systems (difference inclusions), respectively. It is established that the steady-state gain can be arbitrarily closely characterized with Lyapunov functions if the output response converges exponentially to the steady state. We also evaluate other output measures such as the peak of the transient response and the convergence rate. Applying the results to linear difference inclusions, optimization problems with linear matrix inequality constraints can be formulated for the purpose of estimating the output measures. This paper's results can be readily applied to the evaluation of frequency responses of general nonlinear and uncertain systems by restricting the inputs to sinusoidal signals. Similar to continuous-time systems, it is observed that the peak of the frequency response can be strictly larger than the L2 gain for a linear difference inclusion. [ABSTRACT FROM AUTHOR]

New nanotechnology-based devices are being researched to replace CMOS devices in order to overcome CMOS technology's scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes two new circuit simulation approaches that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance problem. A new tool called NanoSim-RTD is developed based on the proposed new simulation techniques. The experimental results show a speedup of 1.48–37.1 times when compared with existing simulators. Further, this paper demonstrates a new way to design delay-insensitive nanocircuits, and the designs can be verified by using NanoSim-RTD. [ABSTRACT FROM AUTHOR]

We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 × 32 pixels. The convolution processor operates on a pixel array of size 32 × 32, but can process an input space of up to 128 × 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second. [ABSTRACT FROM AUTHOR]

Recently, several approaches for communications using chaos have been presented, often showing less than accept- able performance. In this paper, a short introduction to the topic is given, and it is shown that such methods can be efficient—if the information production related to the chaos in the transmitter is controlled and used for the payload of the communication. The influence of minimum distance aspects, a previously ignored key point, to the design of appropriate controlled schemes are studied. In terms of applicable theory, a link between schemes based on one-dimensional and multidimensional chaotic systems (as presented in this paper) and convolutional codes will be established. In order to support our argument, we give simulation results for some a priori examples and results of search procedure for more powerful modulations. [ABSTRACT FROM AUTHOR]

In this paper, a new Markov-jump-system (MJS)-based secure chaotic communication technique is proposed. An MJS evolves by switching from one state evolution model to another according to a finite state Markov chain. The transmitter in the proposed communication system is an MJS consisting of multiple transmission maps, that is, the transmitter switches from one chaotic map to another during the transmission of data. This switching feature makes it difficult to identify and follow the transmission without knowing the transmitter parameters, i.e., to eavesdrop, thereby increasing the security offered by the inherently secure chaotic communication system. If the chaotic maps used at the transmitter, and the corresponding Markov transition probability matrix of the MJS are known to the (authorized) receiver, then a multiple model estimator can be used to track the MJS transmitter. In this paper, the use of the interacting multiple model (IMM) estimator is proposed as part of the receiver to follow the switching transmitter. The effectiveness of the IMM-estimator-based receiver to follow the switching transmitter is evaluated by means of simulations. A new modulation technique that uses the MJS transmitter is also introduced. Further, it is shown that the same receiver framework, when used as a receiver for chaotic parameter modulation, provides significant performance improvement in terms of bit-error rate compared to a receiver that uses extended Kalman filter. In addition, the seemingly more complex IMM-estimator-based receiver is shown to significantly reduce the computational complexity per transmitted bit, thus resulting in increased data rate. [ABSTRACT FROM AUTHOR]

The paper addresses analytical and practical aspects of integration of equation-based (classical) and signal-derived [artificial neural network (ANN)] dynamic models for transient analysis of large-scale dynamical systems. Our signal-based part is based on two ANNs, and is derived from measurements at boundary points. In this paper, we describe this hybrid modeling technique, and focus on: 1) a least square-based mechanism for on-line correction of dynamic variable predictions that is based on actual operating conditions; 2) the resilience of the algorithm to missing measurements due to failed communication links; and 3) a complete two-way interaction between the differential-algebraic equation based subsystem and the ANN-based subsystem. The paper demonstrates the feasibility of implementing our approach in standard power system software by integrating the ANN-based model with the transient analysis toolbox from Matlab. We illustrate capabilities of the proposed approach for transient analysis on a benchmark multi-machine example derived from the New England/New-York interconnected power system. [ABSTRACT FROM AUTHOR]

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation. [ABSTRACT FROM AUTHOR]

The content addressable memory (CAM) is a memory in which data can be accessed on the basis of contents rather than by specifying physical address. In the paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A ternary CAM cell is capable of storing and matching three values: zero (0), one (1), and don't care (X). The proposed dynamic CAM (DCAM) cells range in the number of transistors from 6 n-type transistors up to 10.5 n- and p-type transistors (one transistor is shared between two cells). The cells are capable of fast match and read operations enhancing the performance of the memory system. Using a 0.25-μm CMOS technology, simulations of the proposed CAM cells were performed to compare their performance. With this technology, the shortest match delay is 89.7 ps for the 7.5 DCAM cell. A complete characterization of the five cells is provided in this paper. These results show that the novel CAM cells outperform existing cells. The compact size and low power dissipation of these ternary CAM cells make them suitable for many applications such as routers, database, and associative cache memories. [ABSTRACT FROM AUTHOR]

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given. [ABSTRACT FROM AUTHOR]

Variable-Structure piecewise-linear nonlinear dynamic feedback systems emerge frequently in power electronics. This paper is concerned with the stability analysis of these systems. Although it applies the usual well-known and widely used approach, namely, the eigenvalues of the Jacobian matrix of the Poincaré map function belonging to a fixed point of the system to ascertain the stability, this paper offers two contributions for simplification as well that utilize the periodicity of the structure or configuration sequence and apply an alternative simpler and faster method for the determination of the Jacobian matrix. The new method works with differences of state variables rather than derivatives of the Poincaré map function (PMF) and offers geometric interpretations for each step. The determination of the derivates of PMF is not needed. A key element is the introduction of the so-called auxiliary state vector for preserving the switching instant belonging to the periodic steady-state unchanged even after the small deviations of the system orbit around the fixed point. In addition, the application of the method is illustrated on a resonant dc-dc buck converter. [ABSTRACT FROM AUTHOR]

This paper presents a very large-scale integration implementation of Galois field arithmetic for high-speed error-control coding applications that is based on the field GF(pm) with in a small integer such as 2 or 3 and p a prime of sufficient value to generate the required field size. In this case, the Galois field arithmetic operations of addition, multiplication, and inversion are based on architectures using blocks that perform integer arithmetic modulo p. These integer arithmetic operations modulo p have previously been implemented with low delay power products through the use of one hot coding and barrel shifters circuits based on transistor arrays. In this paper, the same one hot coding and barrel shifters circuits are used to construct circuits that implement addition, multiplication, and inversion over GF(pm). The circuits for GF(pm) addition and multiplication with p ≠ 2, achieve a lower power-delay product than designs based on GF(2m). Also, the architecture for GF(pm) inversion can be efficiently implemented when in = 2 or in = 3. [ABSTRACT FROM AUTHOR]

Ponders on the prediction that electronic technologies will bring about the reduction in paper. Developments in electronic ink; Production of paper-like devices; Potential of electronic papers.

The article reports that Flexible Display Center at Arizona University has fabricated an active-matrix electronic-paper display on plastic. The effort involves collaboration with DuPont Teijin Films and with National Starch. To withstand the problems in temperature, its designers lowered processing temperature to around 180 degree Celsius and increased the substrate's ability to withstand temperature. Moreover, the result has displayed a good contrast ratio and fine resolution.

This article reports that scientists at Infineon Technologies AG in Erlangen, Germany have fabricated organic transistors and circuits on commercially available cotton-fiber paper. Its fibrous surface is rough, whereas a typical semiconductor substrate such as silicon is smooth.

Reports on the development of electronic-ink displays on flexible plastic sheets by researchers at the Philips Research Laboratories in Netherlands, in a major step toward electronic paper that works like a computer monitor. Components and mechanism of the ink; Pattern of the circuitry; Description of the displays made by the researchers.

Pulsers are usually adopted in ultra-sound applications due to their high efficiency. On the other hand, linear amplifiers would enable apodization profiles with high resolution, beams with low harmonic content and instantaneous changes in transmit energy between pulses. Their use is rather limited when relying on a discrete technology approach, due to high manufacturing costs and space occupation. In view of an increased level of integration, the availability of a BCD technology, capable of watts level driving at high frequency, encourages investigation of linear amplifiers, the topic of this work. Advantages in terms of reliability, space and cost would derive. The proposed amplifier, closed in a feedback loop, uses a high gm low-voltage transconductor driving a high voltage trans-impedance stage operating in class-B. Device parameters vary with signal amplitude making circuit analysis involved. Techniques to analyze large signal frequency response, distortion and stability are proposed in this paper leading to useful design insights. The amplifier has been realized in a BCD6-SOI technology and, from experimental results, it shows the following performances: 90Vpk-pk output swing with better than 60% power efficiency, 720 MHz GBW, and HD2 lower than -35 dB when driving a load made of a 100 Ω resistor shunted with a 150 pF capacitor, emulating the ultrasound transducer. Quiescent power dissipation is 37 mW only. [ABSTRACT FROM AUTHOR]

This Special Issue is a collection of selected papers presented at the IEEE Asia Pacific Conference of Circuits and Systems (APCCAS) 2019 that was held in Bangkok, Thailand, November 11–14, 2019, and the IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2019 that was held in Genova, Italy, on November 27–29, 2019. As the flagship conferences of the IEEE Circuits and Systems Society (CASS) in IEEE Regions 10 and 8, respectively, these conferences welcome contributions across the themes within the scope of the Society, including analog, digital, and mixed-signal electronics, signal processing, power electronics, communication theory, sensors, circuit theory, and nonlinear circuits and systems. [ABSTRACT FROM AUTHOR]

Standalone photovoltaic-battery hybrid power systems are attractive renewable power generation systems, a popular form of which is based on a photovoltaic system and a battery connected to an output dc bus via a buck converter and a bidirectional buck/boost converter, respectively. Due to variation of the available sunlight intensity, the battery voltage and load condition, the system's structures and operating modes are switched from time to time. The dynamic behavior is thus quite complex, and the design for stable operation of the system requires consideration of the stability conditions for all possible operating modes. This paper studies the dynamic behavior of this system and reveals the smooth and non-smooth bifurcation phenomena. Under certain conditions, when the system switches its operating mode, a non-smooth bifurcation, manifested as a jump from stable to unstable behavior, has been observed and verified with full-circuit simulations. Moreover, a detailed analysis based on averaged modes is performed to identify the two types of bifurcation and evaluate the stability boundaries of the system. The results provide useful insights and information about the behavior of the system and the interacting effects of control parameters on the design of the control loops. [ABSTRACT FROM PUBLISHER]

The analysis of complicated circuits containing nonlinear electrical elements is commonly performed via numerical algorithms of simulation programs. However, an analytical solution can be preferable to the numerical approach, particularly for the needs of basic research. This paper introduces a methodology of the analytical solution of voltage/current response of the memristor to its excitation from ideal current/voltage source, with the memristor being characterized by the memristance-charge or memductance-flux relationships. The procedure is explained on examples of a TiO2 memristor with linear dopant drift and of a hydraulic memristor. [ABSTRACT FROM PUBLISHER]

This paper presents a circuit-theoretic foundation of the “memristor,” and clarifies why it is fundamentally different from a 3-terminal device with a similarly-sounding name called the “memistor.” Here we show that while the memristor is a basic 2-terminal circuit element based on classic nonlinear circuit theory, the memistor is an ad hoc 3-terminal gadget devised for one specific application, and does not qualify as a 3-terminal circuit element because it is impossible to predict its behavior when connected with other circuit elements. [ABSTRACT FROM PUBLISHER]

In this paper, two circuit design techniques for lower electromagnetic emission (EME) are demonstrated based on shaping the supply current: 1) a discrete-time EME-SCR with a digital feedback loop to obtain more EME attenuation in the low frequency range starting from 150 kHz. It achieves maximum 30 dB di/dt reduction at high frequency with 60 μA quiescent current and a 230 pF on-chip capacitance. The cutoff frequency is shifted down to 100 kHz, which is about 10x lower compared with the continuous-time implementation. 2) The frequency modulation of the discrete-time EME-SCR's clock to further reduce the EME level in a wide frequency range. Measurement results show the effectiveness of these circuit techniques on the reduction of EME on chip level. [ABSTRACT FROM PUBLISHER]

Quadratic converters have the voltage conversion ratios of two cascaded converters, but with fewer switches. They are not widely used, however, because they are generally less efficient than other converter types, but they can be useful for certain applications. In this paper, the characteristics of quadratic converters are explained, several examples of where they can be used in industrial applications are given, and a new three-phase converter that has been derived from quadratic conversion principles is presented. The feasibility of the new converter is confirmed with results obtained from an experimental prototype. [ABSTRACT FROM AUTHOR]

In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, an efficient optimization technique aligning three-dimensional (3-D) electromagnetic simulator responses with two-dimensional (2-D) electromagnetic simulator responses around space mapped solution, for the electromagnetic design of radiofrequency and microwave 3-D circuits is presented. The interface between 2-D and 3-D electromagnetic simulators is obtained from an inverse linear input space-mapping approach and an output modeling process based on a fuzzy logic technique. It is shown that the technique provides a highly accurate estimation of the 3-D design parameter space of the 3-D radiofrequency and microwave circuits to be designed, for initially fixed design specifications. Designs of first-order, second-order and sixth-order C-band 3-D evanescent rectangular waveguide bandpass filters with dielectric posts show the performance of our approach. [ABSTRACT FROM PUBLISHER]

In this paper, we present a flexible and scalable structure to compensate frequency response mismatches in time-interleaved analog-to-digital converters (TI-ADCs). The flexibility of the structure allows for designing compensation filters independent of the number of channels that can achieve any desired signal-to-noise ratio due to the scalability of the structure. Therefore, the compensation structure may be used to compensate time-varying frequency response mismatches in TI-ADCs, as well as to reconstruct uniform samples from nonuniformly sampled signals. We analyze the compensation structure, investigate its performance, and demonstrate application areas of the structure through numerous examples. [ABSTRACT FROM AUTHOR]

This paper presents the effect of bipolar junction transistors' (BJTs) parasitic elements on the decoding performance of a BiCMOS analog decoder. The transistors' parasitic effects are taken into account to develop a more accurate behavioral model of the computing nodes. The model is applied to double-binary 0.25-μm BiCMOS analog decoders. Behavioral simulations show that the BJTs' parasitic elements deteriorate the error-correcting performance of a stand-alone a posteriori probability (APP) decoder by 0.5 dB compared with the ideal bit error rate (BER). In a turbo scheme, the loss is reduced to 0.2 dB for a BER that is smaller than 10-2. A simple solution based on an nMOS amplifier is proposed to counterbalance the dominant parasitic element. The amplifier reduces the degradation by 0.2 dB for the APP decoder. However, the turbo decoder is improved only for a BER above 10-2. [ABSTRACT FROM AUTHOR]