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III-nitride heterostructure-based metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), compared with Schottky and p-GaN gate HEMTs, have demonstrated significant potential in the next-generation high-power electronic devices due to their exceptional gate reliability. This study presents a comprehensive investigation of threshold voltage (VTH) instability in III-nitride heterostructure-based MIS-HEMTs, with a specific emphasis on the interfaces of the multi-heterostructures. Two widely studied amorphous materials, namely, Al2O3 and SiNx, have been extensively examined as primary gate insulators in GaN-based MIS-HEMTs. To efficiently remove native oxides from the (Al)GaN surface, a novel in situ high-temperature remote plasma pretreatment (RPP) technique has been developed. This technique involves sequential application of NH3/N2 plasmas on the (Al)GaN surface before depositing the gate insulators using plasma-enhanced atomic layer deposition. The remarkable RPP process has proven to be a highly effective method for revealing atomic steps on the GaN surface, irrespective of whether the surface has undergone oxidation or etching processes. To further enhance the interface quality and potentially reduce bulk traps in the gate insulator, optimization of deposition temperature and post-deposition annealing conditions have been explored. Additionally, an electron-blocking layer, such as SiON, is incorporated into the MIS-HEMTs to prevent electron injection into bulk traps within the insulator. Novel characterization techniques including constant-capacitance and isothermal-mode deep-level transient spectroscopy have also been developed to explore the failure mechanisms in MIS-HEMTs. These techniques allow for the differentiation between bulk traps in the GaN epitaxy and those present within the gate insulators. This in-depth physical understanding provides valuable insights into the sources of failure in GaN-based MIS-HEMTs. [ABSTRACT FROM AUTHOR]

Ultrathin oxides (UOs) and ultrathin nitrides (UNs) play a crucial role in forming lattice-mismatched semiconductor heterostructures that are fabricated by using semiconducting grafting approach. The grafting approach has shown its great potential to realize GaN-based heterojunction bipolar transistors by fulfilling the missing high-performance p-type nitrides with other p-type semiconductors. A handful of UO and UN dielectrics readily available by atomic layer deposition (ALD) satisfy the requirements of double-sided surface passivation and quantum tunneling for semiconductor grafting. Due to the states existing between the UO or UN conduction band and that of the GaN, the ALD deposited UO or UN layer can generate significant effects on the surface band-bending of GaN. Understanding the band parameters of the interface between UO or UN and c-plane Ga-face GaN can guide the selection of interfacial dielectrics for grafted GaN-based devices. In this study, we performed x-ray photoelectron spectroscopy measurements to obtain the band-bending properties on c-plane, Ga-face GaN samples coated by different ALD cycles of ultrathin-HfO2 or ultrathin AlN. The valence band spectra of GaN coated with ultrathin-ALD–Al2O3, ALD–HfO2, or PEALD–AlN/ALD–Al2O3 were further analyzed to calculate the valence and conduction band offsets between the ALD dielectrics and the Ga-face GaN under different thicknesses and post-deposition annealing conditions of the dielectrics. [ABSTRACT FROM AUTHOR]

In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(<6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (>108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K. [ABSTRACT FROM AUTHOR]

The p-GaN/AlGaN/GaN heterostructure, predominantly epitaxially grown on large-scale silicon wafers, has been widely used for producing consumer power switching devices and recently manifested favorable for developing GaN-based complementary devices and circuits. This work investigates the hole distribution and transport in this structure based on wide-temperature-range (20–600 K) Hall measurements and TCAD simulations. It is revealed that the p-channel thereof is composed of the bulk holes in the p-GaN and the two-dimensional hole gas (2DHG) at the p-GaN/AlGaN interface, and both substantially contribute to the lateral p-type conduction at room temperature. Their complementary temperature responses lead to conductivity enhancement at both high- and low-temperature regimes. The high-density (1.2 × 1013 cm−2) 2DHG is formed owing to the polarization-induced potential well and the ionization of the Mg acceptors that thermally diffused into the barrier during the epi-growth. Such ionized Mg acceptors would partially deplete the two-dimensional electron gas (2DEG) at the access region in the n-channel side where the p-GaN is removed and result in a trade-off between the carrier density of 2DHG and 2DEG. [ABSTRACT FROM AUTHOR]

A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices. [ABSTRACT FROM AUTHOR]

In this work, a deliberate etching-based top-down approach is proposed to fabricate the GaN nanorod (NR) Schottky barrier diode (SBD). As a key step during the fabrication, the impact of the wet-etching process on device performance is systematically studied. By virtue of the reduced surface states at the sidewall, the performance of NR SBD with the wet-etching process is substantially improved, delivering a forward turn-on voltage of 0.65 V, a current density of ∼10 kA/cm2 at 3 V, an ideality factor of 1.03, an ON/OFF current ratio of ∼1010, and no severe current collapse, along with a reverse breakdown voltage of 772 V. [ABSTRACT FROM AUTHOR]

This article was originally published online on 27 December 2023 with an error in the affiliation. The affiliation appears correct above. All online versions of this article were corrected on 4 April 2024.By Yingjie Wang; Sen Huang; Qimeng Jiang; Xinhua Wang; Zhongchen Ji; Jie Fan; Haibo Yin; Ke Wei; Xinyu Liu; Qian Sun and Kevin J. ChenReported by Author; Author; Author; Author; Author; Author; Author; Author; Author; Author; Author [Extracted from the article]

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. [ABSTRACT FROM AUTHOR]

In this work, the impact ionization-induced OFF-state breakdown is revealed and systematically investigated in 100 V Schottky-type p-GaN gate high-electron-mobility transistors. Impact ionization is found to occur in the peak electric-field region at the source-terminated field-plate edge and is initiated by electrons injected from the source-side two-dimensional electron gas channel through the buffer layer. Hot electrons generated from impact ionization, when being captured by surface traps, could lead to redistribution and peak value reduction of electric-field. Consequently, the sudden rise in the OFF-state leakage current by impact ionization could be self-clamped temporally to avoid catastrophic rupture of the device. The impact ionization is further verified by the increase in dynamic OFF-state leakage current and a negative shift in threshold voltage, both of which result from positively charged holes (generated from impact ionization) drifting toward the gated channel. [ABSTRACT FROM AUTHOR]

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at "use conditions" predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate an easy channel-engineering method using oxygen-plasma treatment followed by in-situ annealing before gate dielectric deposition on GaN. A crystalline GaON nanophase was identified to serve as an optimized channel layer in the gate region of E-mode GaN metal-insulator-semiconductor field-effect transistors (MIS-FETs). The atomic-scale element distribution and crystalline structure of the GaON nanophase were revealed by aberration-corrected scanning transmission electron microscopy. First-principles calculations further correlate the enhanced thermal stability with the atomic observation of the refined structure in the GaON nanophase. Owing to the atomically sharp gate-dielectric/channel interface and low interface trap density (Dit), the boosted performance of the E-mode MIS-FET was achieved with the GaON channel. This study not only validates an approach of local channel modification for high-performance normally off GaN MIS-FETs but also opens possibilities of utilizing this crystalline GaON nanophase as a promising channel material in various GaN devices. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density Dit in MOS structures, Dit in the device with AlN was determined to be in the range of 1011-1012eV-1cm-2, showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. [ABSTRACT FROM AUTHOR]

High quality Al2O3 film grown by atomic layer deposition (ALD), with ozone (O3) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al-O-H and Al-Al bonds in ALD-Al2O3 has been realized by substituting conventional H2O source with O3. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O3-Al2O3 and 2-nm H2O-Al2O3 interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 x 1012cm-2, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance RON,sp of 0.49 mΩ cm². [ABSTRACT FROM AUTHOR]

In this work, we attempt to reveal the underlying mechanisms of divergent V TH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows "deeper" interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insulated-gate III-nitride power switching devices. [ABSTRACT FROM AUTHOR]