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• Multi-level operation of Al 2 O 3 /TiO x memristor devices for neuromorphic system • Analyzing analogue-grade weight modulation by adjusting compliance current up to 64 levels • Precisely controlled device state with compliance current and off-chip learning verification • Evaluating the recognition performance of convolutional neural network considering the number of quantization level and accuracy Multilevel operation is one of the most essential properties for synaptic devices to realize hardware artificial neural networks. Compliance current (I cc) adjustment is a multilevel programming method that can be utilized for a large-scale one-transistor and one-resistor (1T1R) array. It protects the devices from permanent breakdown by regulating abrupt switching. However, according to the reported literature so far, the number of conductance states in the I cc control method is insufficient to implement off-chip-trained neuromorphic systems. Therefore, we experimentally explore the feasibility of a larger number of conductance states using the I cc control method. We fabricated an Al 2 O 3 /TiO x -based resistive switching memory array, observed the conductance change while increasing I cc during set operations, and 64-level conductance states were statistically demonstrated. Furthermore, we verified that the 64-level states showed recognition performance close to that of a software-based neural network through off-chip learning of the convolutional neural network (CNN) structure. The fabricated synaptic device array with the I cc -control programming method is expected to contribute to the development of hardware neural network by reducing the information loss in the transfer process. [ABSTRACT FROM AUTHOR]

• Al 2 O 3 /TiO x based memristor devices for physical unclonable function. • Analyzing conduction mechanisms and origin of device-to-device variation for both states. • Randomness improvement by crossing operation with switching box. • Evaluating the performance of physical unclonable function based on memristor crossbar array with different response-extraction method. In this study, we evaluate the performance of a physical unclonable function (PUF) using Al 2 O 3 /TiO x based memristors. Through a conduction mechanism analysis, it is confirmed that the distribution of high-resistance state (HRS) is wider than that of low-resistance state (LRS) due to the direct-tunneling gap. Furthermore, cycle-to-cycle variation and random telegraph noise (RTN) characteristics which can affect the reliability of the PUF are also analyzed. Since the switching characteristics of the devices are less affected by temperature in the LRS thanks to ohmic conduction, the device state of a whole array is determined as the LRS for a better reliability. In addition, three kinds of response extraction methods are compared by evaluating the diffuseness and uniqueness with 2 × 2 switch block for the improved randomness. Finally, the reliability of the PUF is verified considering the measured conductance dependency on temperature and noise effect, and the bit error rates are compared between two states. [ABSTRACT FROM AUTHOR]

On-chip learning in neuromorphic systems, wherein both training and inference are performed on memristive synaptic devices, has been actively studied recently. However, on-chip learning is often affected by the weight-update linearity of memristive synaptic devices. Herein, we fabricated a Pt/Al 2 O 3 /TiO x /Ti/Pt stacked memristor device with excellent switching and reliability characteristics. Its weight-update linearity was analyzed via nonlinear A fitting through an on-chip simulation of the modified National Institute of Standards and Technology (MNIST) dataset. We confirmed the excellent recognition accuracy and low-fluctuation characteristics of the proposed model based on its similar characteristics to software learning. We obtained the perfect linear model and two types of nonlinear model characteristics of the memristor through incremental step pulse programming and performed an on-chip simulation. In addition, the characteristics of the measured cycle-to-cycle variation were reflected in the on-chip learning and were analyzed. We expect the low-fluctuation nonlinear model developed herein to be useful for on-chip learning owing to its excellent learning characteristics. • TiO x /Al 2 O 3 -based memristor for on-chip training of neuromorphic system • Analyzing the effect of nonlinear weight-update in memristive devices • Evaluating the performance of pattern recognition depending on linearity of weight-update • Low-fluctuation nonlinear model achieved by engineering training pulse [ABSTRACT FROM AUTHOR]

Recently, hardware-based neural network using memristive devices, so called neuromorphic system, has been extensively studied. Especially, on-chip (in situ) learning methods where training occurs inside hardware structure itself have been proposed and optimized based on memristor crossbar arrays regarding the linearity of weight-update characteristics. In this study, we analyze the effect of conductance overlap region of memristor on the recognition accuracy for on-chip learning simulation. The effect of conductance overlap region on recognition accuracy for modified national institute of standards and technology (MNIST) dataset is studied with an identical potentiation/depression pulse applied to Pt/Al 2 O 3 /TiO x /Ti/Pt stacked memristor. The overlap range can be varied by different pulse amplitude, and the training characteristics of memristive neural network is significantly dependent on the weight-update overlap region. • Ti/Pt/Al 2 O 3 /TiO x /Ti/Pt stacked memristor devices for neuromorphic system • Evaluating reliability including endurance and retention characteristics • Learning characteristics depending on pulse amplitude regarding linearity and weight overlap region • Analyzing effect of learning characteristics on recognition accuracy for on-chip training [ABSTRACT FROM AUTHOR]