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The evolution characteristics of the heat reservoir of surrounding rock in subway tunnels have been analyzed by a scaled model experimental test for 17 years from new to long-term operation with periodic and dynamic air temperature conditions. According to its variation characteristics with time, soil temperature distribution with time is divided into the dynamic expanding period and the dynamic stable period. The evolution characteristics of soil temperature is varied with depth and the heat storage and release are pointed out. It has been found that the soil heat reservoir thickness is 20m with the peak temperature of the soil heat reservoir 22.7℃ and the soil heat reservoir characteristic thickness 2m. All of these works provides references to solve the tunnel temperature problems in long-term subway operation. [ABSTRACT FROM AUTHOR]

After the development of TLC (Triple level cell) NAND, QLC (Quad level cell) technology will be one of the solutions for next generation NAND flash product. QLC (4 bits/cell) NAND's data levels are up to 16 levels which bring the narrower and tighter voltage ranges and worse performance. This paper studies QLC program and read mechanisms, and presents five types of program algorithms for writing data in QLC cells. Correspondingly, the enhanced Gray coding methods for data mapping based on these different program algorithms are researched. They will be beneficial to data reading. After simulating with changing cell voltages to generate the data errors in the QLC model, the paper presents four enhanced Gray codings to match 16 voltage levels for different program algorithms and read operations. This study will improve the efficiency and keep balance in system-level application for the data error correction of QLC 4 pages which are mapped in the same wordline (WL). [ABSTRACT FROM AUTHOR]

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (I ON ), off current (I OFF ), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (L g ) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (V th ) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi 2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically. [ABSTRACT FROM AUTHOR]

—In this paper, a class-F 23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F 23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoM T of 206.4 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper presents a fractional- N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel the quantization noise (Q-noise) and achieve true-fractional delay. By tuning DTC compensation, spur and Q-noise are suppressed by 14 dB. To speed up the locking process of the ADPLL, a counter-based coarse PLL is integrated to monitor and compensate for large frequency and phase jump while consuming almost zero power. The proposed ADPLL is implemented in a 40-nm standard CMOS process, occupying a silicon area of 0.36 mm2. When TDC offset calibration is turned on, the in-band noise is suppressed by 20 dB. The measured results show 0.78-ps rms jitter and −40-dBc in-band fractional spur are achieved, corresponding to a figure of merit (FOM) of −235 dB. [ABSTRACT FROM AUTHOR]

For boost power converter with Sensorless Current Mode (SCM) control, the inductor current is acquired by current estimator instead of current sensing. Without consideration of parasitics, the estimator is low-accurate, which affects system Small Signal Model (SSM) and degrades the control performance. In this paper, the issue is studied in frequency domain, and solved by a Corrective Frequency Compensation for Parasitics (CFCP) strategy. First, transfer functions for power converter, current estimator and current mode controller are given for frequency-domain analysis. Second, without consideration of parasitics, conventional proportional integral compensation is used to improve the system stability. Furthermore, with consideration of parasitics, converter main pole is replaced by two poles while a zero emerges at the origin. In order to cancel out the influence, the proposed CFCP strategy adopts a second-order transfer function to correct zero/pole variation induced by parasitics. Finally, steady state performance and transient response of the converter are improved, which are verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

Nowadays, deep learning algorithm has been widely used for automatic electrocardiogram (ECG) classification. However, most algorithms can only classify single heartbeat, which requires complex heartbeat extraction preprocessing. In addition, the traditional software implementation on CPU or GPU platform faces the challenge of low computing efficiency and high resource consumption. In this work, a deep one-dimensional (1D) U-net is proposed, which can classify the original continuous ECG segment at the pixel level. And an efficient hardware architecture is presented to implement the 1D U-net. A two-stage pipeline Winograd structure is designed to increase computing efficiency. A 3D processing element (PE) array is developed to improve resource utilization and overall throughput. Implemented on Xilinx Zynq ZC706 board, experimental results show that the proposed 1D U-net achieves an average accuracy of 95.55% for the pixel-level classification of five heartbeats. In terms of hardware performance, resource efficiency and computing efficiency reach 8.27 GOPS/kLUT and 123% respectively at 200 MHz clock frequency. [ABSTRACT FROM AUTHOR]

A high-linearity CMOS power amplifier (PA) operating at 2.45 GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance ( C gs ) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2 dB, a maximum output power of 30.7 dB m with 29% of peak power added efficiency (PAE) and −30 dBc third-order intermodulation (IMD3) product at 26.4 dB m output power, reaching to excellent tradeoffs between efficiency and linearity. [ABSTRACT FROM AUTHOR]

This paper presents an accurate ISF-based phase noise analysis method for LC/Ring oscillators. The proposed method can simultaneously quantify the effect of flicker noise and thermal noise on phase noise. The impulse sensitivity function (ISF) tool is used to evaluate the effect of flicker noise sources. An equivalent thermal noise resistor is utilized to assess the thermal noise contribution and simplify the analysis process. Based on the proposed method, the phase noise performance of a voltage-controlled oscillator (VCO) with source damping resistors is discussed. Simulated in 180-nm TSMC and 110-nm HHGRACE CMOS processes, the accuracy of the proposed method is verified. The predicted phase noise performance is consistent with the simulation results in 1/ f 3 and 1/ f 2 region, achieving 1-dB accuracy in diverse oscillator topologies. [ABSTRACT FROM AUTHOR]