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This article proposes a controller for dc–dc converters to achieve fast load-transient responses. The controller is developed for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of operation. The main idea is developed for buck converters, but it is shown that the proposed controller can be applied to other topologies, such as the noninverting buck–boost converter. The controller derivation, analysis, and experimental verifications are provided in both CCM and DCM, and its performance is compared with other methods. The main advantage of the proposed controller is that it minimizes the recovery times associated with load-transient responses in dc–dc converters while maintaining component sizes and other system parameters within the acceptable range. The proposed controller can be used to minimize load transients in electronic portable devices and electric vehicle charging. [ABSTRACT FROM AUTHOR]

This article proposes a methodology for critical path selection and delay sensor insertion for aging monitoring in field-programmable gate arrays (FPGAs). The aging information can be used to reconfigure FPGAs to achieve better performance or wear leveling. To filter out the paths aging less aggressively, our methodology decides based on both physical-level parameters [e.g., path delay, process variation, temperature, static stress (duty cycle), and dynamic stress (switching activity) as well as aging-relevant parameters (e.g., fan-out, and endpoint physical location)]. After selection of an optimal set of paths, age sensors, introduced in our earlier work, are placed in a distributed fashion throughout the FPGA area to provide aging information of its various parts as they are being used. Accurate aging models for FPGAs are required to determine the contribution of the above-mentioned parameters in aging. In this article, ASICs’ aging models are adapted for FPGAs through measurement-based fitting approach. The experimental results using various benchmarks reveal that our algorithm selects paths with a minimum error. [ABSTRACT FROM AUTHOR]

In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several alternative configurations for each LUT. Alternative configurations are obtained by LUT input reordering. These alternative configurations are rotationally loaded into the FPGA. Experimental results shows that our method achieves 263 and 14.1 percent Mean Time To Failure (MTTF) improvement for Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI), respectively. Additionally, due to changing only local routings, our method imposes up to 1 percent performance overhead to the systems. [ABSTRACT FROM AUTHOR]

This article proposes and demonstrates a fault-detection method to locate interturn short circuits (ITSCs) in the stator windings of a brushless doubly fed induction machine (BDFIM). The detection of ITSC is important in machine health prognostics as ITSC is an early stage fault that may lead to other faults such as coil-to-coil and coil-to-ground. BDFIM consists of power and control windings in the stator that are magnetically coupled through a nested-loop rotor winding. Existing ITSC detection algorithms use rotor slot harmonics in stator current spectra as fault indicators for only conventional doubly fed induction machines. However, these algorithms cannot be applied to BDFIM due to its different stator/rotor winding structure. This article primarily proposes a new analytical formulation for the nested-loop rotor slot harmonics (NRSHs) as ITSC fault indicators in BDFIMs. Using NRSHs, a detection algorithm is also proposed to detect and locate ITSC in power/control windings of BDFIMs. The proposed algorithm is verified based on numerical analysis of a BDFIM using the finite-element method. The accuracy of the proposed fault-detection algorithm is also experimentally investigated and demonstrated using a BDFIM test rig. Both numerical and experimental test results confirm effectiveness of the proposed ITSC fault-detection algorithm. [ABSTRACT FROM AUTHOR]

In this paper, new steady-state analysis is proposed for a series resonant converter (SRC) that provides closed-form expressions for converter waveforms. Using the proposed analysis, explicit equations are obtained to design the converter components. It is shown that an SRC can be modeled through a nonlinear differential equation with discontinuous inputs. A Laplace-based theorem (LBT) is provided to obtain the steady-state analytic solution of the resonant converter differential equations. Using the LBT, a flowchart is proposed to analyze the converter where the nonlinearity of differential equation is removed by defining intermediate variables. The variable duty ratio SRC is analyzed using the proposed flowchart. Accurate, closed-form, and explicit equations for converter waveforms, voltage gain, current phase lag, zero voltage switching, and discontinuous conduction mode boundaries are derived. The proposed analysis is compared with conventional methods and its accuracy is validated through simulations and experimental results. Moreover, using the proposed method, a novel procedure is provided for the optimal design of the converter and is compared with conventional design approaches. [ABSTRACT FROM AUTHOR]

A new inverter control approach, called enhanced virtual synchronous machine (eVSM), is proposed based on the VSM concept. Unlike existing VSM approaches, the eVSM does not emulate the rotating inertia based on an assumption of the unlimited energy storage, but it deploys the physically existing inertia of the dc-link element. The eVSM adopts an innovative way of enlarging the inertia utilization range, which obviates the need for having a large dc-link element or a dedicated battery storage system, while still providing the same inertia response of an equivalent synchronous machine. Theoretical developments and numerical results presented in this paper confirm that the proposed eVSM can present a stabilizing support to the grid similar to a synchronous machine despite the small size of its dc-link element. Moreover, its transient responses can be improved beyond those of conventional synchronous machines thanks to the possibility of more flexibly adjusting damping and governor functions. [ABSTRACT FROM AUTHOR]

This paper presents an instantaneous torque control method for cascaded doubly fed induction machines (CDFIMs) with a rated torque-sharing ratio feature under steady-state operation. A CDFIM includes two coupled main and auxiliary doubly fed induction machines, and the rated torque-sharing ratio herein means that the machine torques are proportional to the machine ratings. The proposed method is established based on transferring the torque equations of the two machines into the rotor-flux reference frame of the auxiliary machine. Then, the instantaneous torque and the rated torque-sharing ratio are controlled via the stator current components of the auxiliary machine, while machine fluxes are within allowable ranges. To verify the method and evaluate its capabilities, the suggested method is used for the speed control of a CDFIM experimental setup including two 4-kW doubly fed induction machines and a 4-kW dc machine to apply a sudden mechanical load change to the CDFIM. Further, a case study including 12-kW and 4-kW DFIMs is also simulated to evaluate the performance of the torque control method for a CDFIM with different machine ratings. The test results confirm that the proposed control schemes achieve the desired performances without exceeding the ratings of the machines under various test scenarios. [ABSTRACT FROM AUTHOR]

This paper proposes a linear and efficient transmitter prototype based on pulsed load modulation (PLM) power amplifier (PA). The proposed transmitter setup utilizes the complex delta–sigma (DS) modulation as a signal processing technique instead of the envelope DS modulation for higher linearity performance. Using the complex DS modulation technique reduces the in-band quantization noise significantly at the output of the modulator and consequently, enhances the linearity of the transmitter. To validate the proposed technique, the linearity and efficiency performance of the complex DS modulator (CDSM)-based transmitter are compared with the performance of its envelope DS modulator (EDSM) counterpart in measurement. For this paper, an efficient and linear PLM PA is designed and fabricated using GaAs E-pHEMT transistors. For a Long-Term Evolution (LTE) uplink standard signal with 3-MHz bandwidth and 7-dB peak-to-average power ratio, the CDSM-based transmitter achieves the drain efficiency and power added efficiency of 46% and 42%, respectively, at an average output power of 25.1 dBm. The comparison measurement study of EDSM-based transmitter and the CDSM-based transmitter with the LTE uplink signal shows about 11-dB improvement in the signal-to-noise and distortion ratio of the output signal. The measurement results for LTE signals were able to pass the spectral requirements defined by the standard without applying predistortion techniques. [ABSTRACT FROM AUTHOR]

A fast and robust fixed switching frequency peak current controller for DC–AC converters is presented. The proposed method tends to mimic the switching behavior of pulse width modulation (PWM) techniques, so it features all the advantages of peak current controllers (such as simplicity, fast transient, and optimum dynamic response), with the superiority of fixed switching frequency and harmonic free output. The proposed method is a generalized approach that can be applied to different PWM schemes. The method is specifically elaborated for single-phase distributed generation applications, using various inverter topologies and mimicking different PWM schemes. Moreover, adaptive bands are proposed to provide active damping for the controller, to extend use of the proposed method for inverters with LCL output filters. Feasibility and performance of the controller is shown by means of simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a highly scalable sensor design for late transition detection in FPGA based platforms. Transition delays occur because of aging mechanisms such as Biased Temperature Instability (BTI) and Hot Carrier Injection (HCI). We propose a sensor clock (SCLK) that is a function of minimum slack time of a set of paths selected for age monitoring. There will be one such clock for many sensors as are needed in an entire FPGA. Our proposed sensor architecture makes it possible for a single SCLK to be shared by all sensors. Additionally, the proposed sensor occupies one slice (basic FPGA logic block), which leads to low area, power, and performance overhead. Using Artix-7-based board, experimental results demonstrate that the proposed aging sensor detects aging earlier than existing sensors and provides less power and performance overheads. [ABSTRACT FROM AUTHOR]

This paper presents a fast and robust $DQ$ current controller to regulate the output power of single-phase grid-connected inverters. The proposed method generates the grid current orthogonal component without introducing any additional dynamics or distortions to the control loop. Moreover, its operation does not depend on the system parameters. The proposed method exhibits improved steady-state and dynamic performances in comparison with the inverters equipped with the conventional orthogonal signal generation techniques. Its improved characteristics make the proposed controller suitable for smart inverter applications, to provide advanced grid functionalities as demanded by recently revised standards. Simulation and experimental results show the feasibility and performance of this control structure. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive investigation of various reference frames and their relative speeds in cascaded doubly-fed induction machines (CDFIMs). Then, a compact space-phasor model of CDFIMs in the natural and arbitrary reference frames is presented that is useful for performance analysis of CDFIMs based on rotating phasors. The merits of the proposed model compared with existing models are using a common (single) reference frame for all machines and parts of CDFIMs, and the model formulation is independent of the rotor angle position. The reference frames in the suggested model can be fixed on the common rotor of the CDFIM machines for dynamic analysis or it can be fixed on the stator/rotor flux of each cascaded machines useful for CDFIMs controller design. A two-axes equivalent circuit for a CDFIM is also presented, which enables analysis of CDFIMs in commercially available power circuit simulation software tools. The validity of the model is verified via the investigation of an experimental setup and consists of two mechanically coupled 4-kW DFIMs and a 4-kW dc machine as a load. The setup is investigated under various test scenarios, including free acceleration, load (torque) change, and frequency step change conditions. [ABSTRACT FROM AUTHOR]