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This paper describes a flow control of the dye in the paper mill with the quasi-Z-source indirect matrix converter (QZSIMC) fed induction motor drive. More than a decade the voltage-source inverter (VSI) and current-source inverter (CSI) have been used to control the speed of the induction motor, which in turns controls the flow of dye. Recently, the matrix converter (MC) has been an excellent competitor for the VSI or CSI for its compactness. The voltage transfer ratio of the VSI, CSI, and MC has been limited to 0.866. Thus, the efficiency of these converters is less. To improve the voltage transfer ratio the quasi-Z-source network (QZSN) is to be used between voltage source and indirect MC (IMC). The modification in the shoot-through duty ratio of the QZSN varies the voltage transfer ratio greater than 0.866. Different voltage transfer ratios are needed for different voltage sag conditions. For a variation of the duty ratio of the QZSN, the fuzzy logic controller has been presented. To control the IMC vector control with space vector modulation has been presented. This paper proposes the implementation of QZSIMC adjustable speed drive for the flow control of dye in paper mill during different voltage sag conditions. A 4-kW prototype has been built and the effectiveness of the proposed system is verified with simulation results and experimental setup. Simulation is done in MATLAB, Simulink platform. Experimental setup is done with the aid of a TMS320F2812 (Texas Instrument) processor. The experimental results validate the maintenance of the speed of an induction motor at the set condition, thus controlling the perfect flow of dye in paper manufacturing technology. [ABSTRACT FROM AUTHOR]

Supercapacitors have drawn numerous attentions in recent years since they can deliver relatively high power and energy densities. This article introduces an all-printed paper based surface mountable supercapacitor (SMS), which could withstand the reflow soldering process when integrated into microelectronic systems. The device was fabricated by screen printing and stencil printing processes, contributing to low cost and large-scale fabrication. Furthermore, building electronic devices on ubiquitous paper substrates had advantages of light weight, low cost, and eco-friendliness, etc. Based on activated carbon electrode material and ionic liquid electrolyte, the capacity of the supercapacitor could reach 14 mF at the device volume of 3.2 mm ? 2.5 mm ? 0.175 mm, besides, the specific volumetric capacity was superior than most of the commercial SMS devices. [ABSTRACT FROM PUBLISHER]

The work reported in this paper aims at developing an algorithm for system operators to solve a robust security-constrained AC optimal power flow (R-SC-ACOPF) problem, which also optimizes the settings of discrete controllers including load tap changers (LTCs) and shunt capacitor banks (SCBs). An iterative algorithm involving a master problem and a number of sub-problems is proposed. The master problem selects the optimal discrete controllers’ settings by taking into account primal SC-ACOPF constraints based on the single-component worst contingencies identified by the sub-problems. Each sub-problem is a bi-level max-min problem used to find the current worst contingency. The overall objective is to minimize the total cost, including generation and load shedding cost, while satisfying all relevant constraints. The master problem and sub-problems allow representing LTC tap positions, SCB status, and contingencies using binary variables. Two case studies are presented as applications of this novel technique. [ABSTRACT FROM AUTHOR]

In recent years, there is an increased use of passive filters in both transmission and distribution systems due to the proliferation of power electronic devices. However, the problem of filter design has not been well addressed in the past and one example is the application of high-pass filters in a filter package. Three types of HP filters are widely used to mitigate multiple harmonics, i.e., 2nd HP filter, 3rd HP filter and C-type filter. There is still a lack of research to clearly reveal the characteristics of each filter, which makes it difficult for the designer to select the optimal filter topology under different circumstances. The main goal of this paper is to solve the problem of how to select a proper configuration among three HP filter candidates for a given harmonic problem. Unlike the conventional optimization-based filter studies, this paper investigates three HP filters in an analytical way. As a result, the paper provides a deep insight into the inherent characteristics of the filter and the conclusions drawn in the paper are universal; thus can be used in different applications, ranging from low voltage levels to high voltage levels. The research results lead to a recommended application scope of each HP filter, which is very useful to guide the design of filter packages and help designers to evaluate the design results. [ABSTRACT FROM AUTHOR]

This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this paper proposes a unit-length capacitor implementation, which minimizes the number of components and thus minimizes area, while also achieving good linearity (integral non-linearity of 0.39 LSB, differential non-linearity of 0.55 LSB, and SFDR of 75 dB) despite using a small LSB capacitor of 125 aF. The 10-b SAR ADC occupies only $36 \times 36\,\,\mu \text{m}$ , thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively. Besides the ADC, a passive analog FIR filter is added to implement an anti-aliasing filter. The topology is based on a passive charge-sharing network and thus only consumes power for the clock phase generation and switch drivers. A 4 $\times $ time-interleaved 15-tap passive FIR filter is implemented, which can realize >42 dB out-of-band rejection and 4 $\times $ decimation while occupying only $53\times 90\,\,\mu \text{m}$. The filter and the ADC together consume 39.2 $\mu \text{W}$ for an output rate of 10 MS/s. [ABSTRACT FROM AUTHOR]

This paper presents a measurement-based method for real-time determination of the wind farms or wind turbines that contribute most significantly to a subsynchronous resonance (SSR) event. The method is based on the concept of subsynchronous power (SSP). This paper has shown that it is the SSP that drives the SSR. By monitoring the direction and amount of SSPs produced by different wind farms or turbines, the most critical wind farms or turbines can be identified and quantified. A dq0 transform-based algorithm is developed to calculate the SSP in real time. The method overcomes the interference of fundamental frequency components and non-steady-state SSR components on the extraction of the SSP component. Several test cases have demonstrated the usefulness of the proposed concept and method. [ABSTRACT FROM AUTHOR]

Frequency Domain Spectroscopy (FDS) is mainly used to determine the moisture in the paper-oil insulation systems in power transformers and Oil-Impregnated-Paper (OIP) bushings. Another application of this method is detection of puncture developing in the paper layer between the adjacent conductive foils in the condenser core. The paper presents theoretical calculations of tan? frequency response in the case of short circuit of conductive layers in bushing's condenser core and their experimental verification, with the help of paper-oil insulation capacitor. Furthermore, examples of measurements of real bushings in operation that agree with the proposed idea are described. [ABSTRACT FROM AUTHOR]

This paper reports the demonstration of human integrated electronic devices, such as oscillators and RC filters, by utilizing flexible capacitor fabricated using few layer MoS2 grown on Al foil via hydrothermal method as electrodes and cellulose paper as a dielectric material. There are no reports of MoS2 on flexible substrate being utilized as capacitor electrode and further applied human interactive devices. Advantage of using MoS2 on Al foil is the enhanced capacitance upon strain due to the piezoelectric property of few layered MoS2 over monolayer MoS2. As the applied strain increases, increase in the capacitance was observed, which is systematically explained by piezoelectric property of MoS2, change in physical dimensions, and air gap between MoS2–Al foil and cellulose paper. Upon application of external strain on capacitor, range of frequencies can be generated by oscillator circuit and the mathematical operations such as differentiation and integration are observed for different input signal using RC filter circuits. Further, the fabricated flexible MoS2 capacitor was integrated to human hand and the corresponding frequency modulation with hand movement was recorded. Such a simple technique for fabrication of flexible variable capacitor is a major step ahead in wearable electronics having applications in digital electronics and sensors. [ABSTRACT FROM PUBLISHER]

Presents comments on the paper, ?Towards Power Centric Analog Design? by Christer Svensson, IEEE Circuits and Systems Magazine, vol. 15, no. 3, pp. 44?51, Sept. 2015. [ABSTRACT FROM PUBLISHER]

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance (${C} _{\text {inner}}$). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application. [ABSTRACT FROM AUTHOR]

This paper proposes unconventional control techniques for a portable power supply consisting of electric double-layer capacitors (EDLCs), a dc–dc converter, and a low-impedance load such a plasma load. Between the EDLCs and the plasma load consuming high power, a dc–dc converter is required to control the output voltage from the rapidly decreasing voltage of EDLCs. In addition, the dc–dc converter should maintain a set point by responding to arcs occurred in plasma process. This paper proposed hybrid analog and digital controls for a nonideal boost converter which was setup by theoretical analysis. The proposed system is verified with experiment and simulation. As a result, the proposed control method can maintain the constant output voltage longer than a traditional analog pulsewidth modulation control. [ABSTRACT FROM AUTHOR]

A new modular pulsed-power source with fast rise time and step-wise arbitrary output waveform generation is currently under development to drive the Gepulste Elektronenstrahlanlage device investigated at the Institute for Pulsed Power and Microwave Technology (IHM). Acknowledging the complex design procedures necessary to set up a modular pulsed-power source for voltages of up to 120 kV, this paper focuses on the circuit design for a single stage and its validation prior to the generator assembly. Using a semiconductor-based Marx generator topology, the stages are designed to have an output voltage of 1 kV with a pulse current of up to 600 A. When connected to an ohmic load, the measured current rise times are in the order of 46 ns resulting in the current rise rates of up to 10 kA/ $\mu \text{s}$ using the commercial devices. The step-wise arbitrary output waveform is created by generating the switching commands on the stage using a microprocessor and a fast optical synchronization unit. Effective stage shielding is verified by operating the stage in a 100-kV, 2.5-kA electromagnetic interference test bed. This paper presents the design considerations and the corresponding measurements. [ABSTRACT FROM AUTHOR]

Virtual synchronous generator (VSG)-based control approaches for AC machine drivers have attracted much attention in recent years. The contradiction between the strong motor loading capacity and the small DC voltage fluctuation is disregarded in previous studies. A larger virtual inertia is required to raise the torque gain and drive the motor with heavier loads, thus resulting in greater DC voltage variations. A systematic method is proposed for the optimal design of the virtual inertia for VSG-based motor starting systems to achieve the maximal motor loading capacity and the low DC voltage fluctuation in this paper. Firstly, the relationship between the virtual inertia and the loading capacity is revealed on the basis of the closed-loop analysis. Considering the DC voltage variation, the constraint on the maximal value of the virtual inertia is proposed from the energy-balance perspective despite the unknown contribution of the DC capacitors to the virtual inertia. To fully exploit the energy storage capacity of the DC capacitors and raise the upper limit of the virtual inertia under the same permitted DC voltage variation, a modified DC voltage reference is introduced. Extensive simulation and experimental results are presented to validate the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable dc–dc converter for maximum thermoelectric generator (TEG) energy harvesting in a battery-powered duty-cycling wireless sensor node. The proposed dc–dc converter adopts discontinuous energy harvesting, which operates in single-input dual-output (SIDO) boost, battery-TEG pile-up buck (BTPB), dual-phase buck–boost (DPBB), and battery supplied buck modes with a single shared inductor. Fabricated in a 65-nm CMOS process, the converter adopts an adaptive dead-time controller for zero-voltage switching (ZVS) and an adaptive switch size (ASS) with maximum power point tracking (MPPT) to maximize efficiency in a wide TEG voltage range. The SIDO boost mode achieves 88.5% and 81.1% peak end-to-end efficiency with maximum and no-load conditions (only charging the battery), respectively. The combination of BTPB and DPBB modes to maximize the TEG power extraction during the battery-powered operation results in up to 44% saving in battery power. The battery-supplied buck mode achieves 93.3% peak efficiency. [ABSTRACT FROM AUTHOR]

This paper proposes a bio-signal instrumentation amplifier (Bio-IA) with fast recovery and constant bandwidth for wearable bio-sensors. To shorten the offset calibration time of the Bio-IA and reduce the loss of bio-signal in the calibration process, a digital-controlled DC servo loop (DCDSL) with fast recovery is designed, which achieves a larger offset calibration range and a faster calibration speed. The proposed programmable gain amplifier (PGA) with constant bandwidth uses dual-biased pseudo-resistor (PR) to stabilize the passband width under different gains, effectively preventing the loss of low-frequency signals. Besides, this paper analyzes the noise of the DCDSL and the noise of dual-biased PR for the first time. The presented Bio-IA was implemented in a 0.18- $\mu \text{m}$ CMOS process, occupying a core area of $849 ~\mu {\sf m}\times 451 ~\mu {\sf m}$. The measured results show that the Bio-IA can calibrate a DC offset of ±511 mV, and the response time is less than 70 ms when the offset polarity changes suddenly. When the gain of the Bio-IA varies from 26 to 40 dB, its passband width remains constant, and the high-pass and low-pass cut-off frequencies are 0.4 Hz and 200 Hz, respectively. The input-referred noise over the range of 0.1-200 Hz is $0.72~\mu $ Vrms. The proposed Bio-IA consumes $5.5~\mu \text{W}$ from 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

The fourteen papers in this special section focus on high performance light emitting diode (LED) drivers. In recent years, as the fourth generation of light source, light-emitting diodes (LEDs) have been widely used in many applications such as street lighting, automotive, and residential lighting because of their long lifetime, low maintenance requirement, and environment friendliness. As the performance of LEDs will be influenced obviously by the drivers, researchers have shown a growing interest in optimizing the drivers. Although these problems such as current balancing, eliminating electrolytic capacitor, and improving the topologies are not new, the high-frequency high-efficiency trend of LED drivers has given rise to additional challenges. These papers provide an insight on some of the newly emerging challenges and potential solutions to overcome those issues. [ABSTRACT FROM PUBLISHER]

The paper considers the problem of sub-synchronous resonances (SSR) in doubly fed induction generators connected to the grid through series-compensated lines. The existence of oscillations is observed on a laboratory test-bed in various conditions, with instabilities developing in the worst-case scenario. Despite the limitations of a small-scale test-bed, the ability to investigate problems and solutions in ways that would not be possible on a full-scale system is very valuable. In particular, the paper demonstrates the significant effect of the choice of dq reference frame on the severity of SSR. Stator-aligned algorithms are found to be significantly more resonant than grid-oriented algorithms, as evidenced in experiments as well as using an analysis method proposed in the paper. From this observation, an algorithm is proposed to emulate a grid-alignment using stator voltages and currents, but without measurements of the grid and series-capacitor voltages. Two control laws are then presented to regulate the active and reactive powers generated, resulting in well-damped transient responses. SSR oscillations are found to be eliminated in experime, as well as simulations of a full-scale system and using a frequency response analysis of the closed-loop system. The effectiveness of the proposed control schemes is verified through experiments for different compensation levels and varying speeds. Within the assumptions made in the design, the proposed controllers are global. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive self-tuned current controller design for an LCL-filtered LC-tuned single-phase shunt hybrid active power filter (HAPF), which offers adaptability and flexibility of the control system to filter parameters changes. System modelling and online identification of parameters are presented. Then, a systematic self-tuned controller (STC) design is proposed to calculate the controller parameters and obtain the final control law adaptively. The exact HAPF parameters design is described and the overall closed-loop stability evaluation with considering digital control delay is discussed in this paper. To confirm the theoretical achievements, simulations and experimental tests on a real prototype system are performed. The results are in good accordance and demonstrate the effectiveness and superior performance of the suggested control technique. Furthermore, a comprehensive comparison between the proposed control technique and other controllers is provided to show the superiority of the proposed system from different aspects. [ABSTRACT FROM AUTHOR]

The grid-forming converter is an important unit in the future power system with more inverter-interfaced generators. However, improving its performance is still a key challenge. This paper proposes a generalized architecture of the grid-forming converter from the view of multivariable feedback control. As a result, many of the existing popular control strategies, i.e., droop control, power synchronization control, virtual synchronous generator control, matching control, dispatchable virtual oscillator control, and their improved forms are unified into a multivariable feedback control transfer matrix working on several linear and nonlinear error signals. Meanwhile, unlike the traditional assumptions of decoupling between AC and DC control, active power and reactive power control, the proposed configuration simultaneously takes all of them into consideration, which therefore can provide better performance. As an example, a new multi-input-multi-output-based grid-forming (MIMO-GFM) control is proposed based on the generalized configuration. To cope with the multivariable feedback, an optimal and structured $\mathcal {H}_{\infty }$ synthesis is used to design the control parameters. At last, simulation and experimental results show superior performance and robustness of the proposed configuration and control. [ABSTRACT FROM AUTHOR]

In renewable energy micro-source applications, a wide range of voltage conversion of the step-up converter is an essential part to equalize the typical low voltage of micro-source with DC-bus voltage of Inverter or motor drives. In order to meet this purpose, an ultra-voltage gain step-up DC-DC converter is proposed in this paper. The proposed converter has made an arrangement of the regenerative-boost fed switched inductor and capacitor configurations. Thereby, due to such an organization of structure, the proposed converter can develop an extremely high voltage-gain even at lower duty ratios. In addition, it has the advantage of lower switching stress across all power semi-conductive diodes. Furthermore, this paper describes the steady-state analysis and comparative features of the converter with existing recent literature. Finally, to validate theoretical analysis and test the feasibility and suitability of the proposed ultra-gain converter, the experimental results were observed by a 500 W fabricated prototype. [ABSTRACT FROM AUTHOR]

Conventional half bridge modular multilevel converter (MMC) system will suffer great over-current when there is a dc side fault. Therefore, topology study in sub-modules with dc side fault blocking capability have become one of the hotspots in MMC field. However, fault blocking topologies using conventional IGBT devices must employ more semiconductors than half bridge topology. The extra semiconductor devices employed in the topology will lead to the increase of cost and conduction loss. To reduce the conduction loss of the fault blocking topology, a novel sub-module topology is proposed in this paper. The proposed topology employs reverse blocking devices to form the low conduction loss path. Conduction loss analysis is conducted in this paper to show the priority of the proposed topology. Simulation and experiment results verified the dc fault blocking capability of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper analyzes the unsymmetrical operation of the dc/dc MMC caused by parametric uncertainty. The unsymmetrical operation is referred to as the condition in which parameters involved in ac power generation are not equal in the phase-legs of the converter. Because existing models in the literature cannot exhibit the unsymmetrical operation of the dc/dc MMC, new detailed and simplified steady-state models are developed in this paper. In the developed models, the connection between the operation of different phase-legs shows itself when the dc-link impedance is considered. Using the developed models, the parameters that can force the converter to operate in unsymmetrical conditions are identified, and the maximum variation that the converter can tolerate is found. It is shown that even a small parameter variation leads to the leakage of the ac circulating current into the dc-link, which is not acceptable. By conducting various case studies, the impacts of the dc-link length, the transmitted power, and the conversion ratio on the unsymmetrical operation of the dc/dc MMC are characterized. The results showed that the converter would be more sensitive to the parameter variation as these parameters increase. Comparative analysis and simulation results confirm the validity and effectiveness of the presented models and analysis method. [ABSTRACT FROM AUTHOR]

A modular multilevel converter control system, based on converter energy storage, is proposed in this paper for two different control modes: active power and dc voltage. The proposed control system decouples the submodule (SM) capacitor voltages from the dc bus voltage. One of the practical applications is the management of active redundant SMs. A practical HVDC system with 401-level MMCs, including 10% redundancy in MMC SMs, is used for validating and demonstrating the advantages of the proposed control system. This paper also presents a novel capacitor voltage balancing control based on \max–\min functions. It is used to drastically reduce the number of switchings for each SM and enhances computational efficiency. [ABSTRACT FROM AUTHOR]

The linear induction launcher consists of two parts: the barrel section and the projectile section. The barrel contains of a long coaxial sectionalized group of coils that are energized by a capacitor bank or generator sets. This paper deals with the design, implementation, and experimental test of a coreless axial-flux permanent magnet (AFPM) pulsed alternator with a flywheel system as an energy source for linear induction coil launchers. The proposed coreless AFPM generator has a low internal inductance and resistance of stator windings without compensation windings when compared with the conventional iron core machines. This paper describes the coreless AFPM generator configuration and shows the simulation findings. [ABSTRACT FROM AUTHOR]

This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. This paper gives a detailed analysis for the reasons of poor linearity for passive-charge-sharing SAR ADCs and proposes solutions. The proposed ADC architecture with one-reference-cap-per-bit and short switches addresses the issue of signal-dependent reference voltage droop during SAR ADC bit trials and orthogonalizes the bit weights. The calibration technique presented further calibrates the ADC to 16-bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the digital-to-analog converter (DAC) capacitor array, the first reported in this type of SAR ADC. This paper provides the foundation of building a precision SAR ADC out of on-chip reference capacitors. Measurement result from a prototype test chip shows ±0.8 LSB (16-bit level) integrated non-linearity at 1 MSPS. [ABSTRACT FROM AUTHOR]

This paper describes a systematic approach to design field-programmable gate array (FPGA) package for high-power applications. As the power consumption is up to multihundred watts, not only the heat dissipation becomes a challenge, but the temperature-induced reliability concerns also mount up in the high current and noise-sensitive packages. Two most profound phenomena are substrate electromigration (EM) and package decoupling capacitor time-dependent dielectric breakdown (TDDB). The impact of EM is on maximum current-carrying capability, and impact of TDDB is on voltage noise suppression capability. However, we find both traditional static way of EM calculation and the legacy design considerations are oversimplified and insufficient for high-power products. In this paper, we report an enhanced methodology to derive substrate EM failure rate from composite current and temperature distributions. Moreover, we incorporate capacitor TDDB into the design flow to optimize capacitor lifetime for effective voltage noise suppression. In the end, we apply the electrical and thermal co-design to a 16-nm, 200-A, high-power FPGA meeting all current and dynamic noise specifications. [ABSTRACT FROM AUTHOR]

This paper presents the design, and implementation of a new CMOS capacitive sensor and proposes the applicability of the sensor in monitoring the dried DNA mass for the emerging DNA memory technologies. The concept of DNA-based data storage has shown to be a promising solution with an ultra-high data density storage capability of gigabytes per nanogram mass of DNA. There are several drawbacks in achieving a ubiquitous technology and existing research has mostly addressed the translation of digital data to synthesized nucleotides, the physical storage of DNA, and reading out the data via sequencing, as well as computational processes. In this paper, we tackle the challenge of monitoring the physical storage of dried DNA material by developing a CMOS capacitive sensor that detects the dried DNA mass and inherits the highly integrable nature of CMOS chips with other parts to develop a DNA storage system. The successful detection of down to 45 ng $/ \boldsymbol {\mu }\text{L}$ mass of dried DNA has been successfully shown with the experimental results that consist of five runs for five different concentrations. Based on the results, the detection range of sub-pico Mol has been achieved which is compatible with the concentrations of DNA used in DNA memory technologies. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive investigation of several important error sources for the successive-approximation register (SAR) analog-to-digital converters (ADCs). The error sources that we discuss in this paper include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential nonlinearities (INL/DNL) of SAR ADCs that are resulted from these error sources are analyzed and addressed. A diagnostic procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also offered and recommended in this paper. [ABSTRACT FROM AUTHOR]

In a previous paper, we introduced a modified Steinmetz equation to account for dc-bias field effects, which requires only a simple dc permeability measurement to predict total power loss. In this paper, we expanded our investigation to include Finemet nanocrystalline material and found that our modified Steinmetz formalism was effective in predicting dc-bias-related losses for this system as well. In this paper, it was observed that Finemet cores exhibit lower losses than Metglas cores under identical test frequencies and bias fields. In addition, we show that a full characterization of the dc loss component necessitates the consideration of higher order ( $n>1$ ) harmonic components. In order to quantify these higher frequency loss components, a dc–dc converter-based test system was built to intentionally introduce inductor current harmonics by varying the filter capacitance and parasitic inductance of the test system. Both core types were evaluated under fundamental frequencies of 20 to 150 kHz and dc-bias fields of up to 1.3 kA/m, with the inclusion of distorted waveforms obtained by varying filter capacitance. At higher frequencies, the Metglas cores were found to exhibit greater loss fractions associated with the higher order harmonic components. A detailed summary of the measured core loss characteristics for both core types is included and discussed. This paper includes the details of the measurements, the modified Steinmetz relation, and the loss extraction algorithm used for analysis. [ABSTRACT FROM PUBLISHER]

This paper highlights an immediate need for renewable generation developers, manufacturers, utilities and industry standardization institutes to jointly address a challenge of capacitor switching transient immunity in inverter-based wind or solar farms. The need was identified from wide-area operation records which showed partial or full generation loss in coincidence with routine utility-owned capacitor switching. The lack of a clear industry guideline has caused confusion to all involved parties. This paper recommends all entities to address this challenge collaboratively through enhanced equipment specification, design, and test before a well-defined industry guideline becomes available. [ABSTRACT FROM PUBLISHER]

Some inverter-fed motors, particularly at higher power ratings, are supplied with a shaft brush in order to help mitigate bearing currents. As more inverters are applied to motors in Class I Division 1/Zone 1 and Class I Division 2/Zone 2 locations, there is a need to understand whether a shaft brush can be safely applied in such an environment. This paper addresses the physics of why this is a concern and a methodology to evaluate the relative safety of two example cases. These issues are considered from the perspective of users, manufacturers of inverters and motors, and certifying bodies. The question posed in the title of this paper is answered by considering whether the addition of a shaft brush to an inverter-fed motor in a Class I hazardous location makes the system more safe or less safe. [ABSTRACT FROM PUBLISHER]

This paper presents an evolution of control systems of Modular Multilevel Converters (MMCs) focusing on the internal voltages and currents dynamics. MMCs have passive components inside the converter that create extra dynamics compared to conventional VSCs. Some control schemes that do not consider these internal dynamics may still stabilize the system asymptotically thanks to the linearisation in the modulation step. However these control schemes are less robust because they are prone to poor damped oscillations on the dc side of the converter. The MMC circuit and energy relationships are presented in this paper. Along with a gradual development of the energy based control, the important roles of each internal dynamics are clearly demonstrated. Experimental results are presented to show the impacts of the linearisation in the modulation step on the system behaviour. [ABSTRACT FROM AUTHOR]

Filter capacitors are among the most serious noise sources in HVDC converter stations, and there are still no satisfactory noise reduction measures. This paper proposes the use of the mass tuning (MT) method to adjust the vibration frequency response characteristics and to realize vibration control and noise reduction. First, the theoretical model of the MT structure is developed based on continuum mechanics. Based on the theoretical model, it is revealed that inserting an MT component into the capacitor element package will cause a decrease in the resonant frequencies and antiresonant frequencies. Furthermore, the movement degree of the resonant frequencies increases as the position of the MT component becomes closer to the package end, while the movement degree of the antiresonant frequency is the largest when the MT component is located in the middle of the package model. The vibrations and the noise levels of an example MT capacitor are then compared with the results of an original capacitor. The comparison results show that the MT scheme designed in this paper can achieve a noise reduction effect of 12–15 dB(A). The proposed reduction method is proven to be both effective and efficient. [ABSTRACT FROM AUTHOR]

DC microgrid has attracted more and more attention due to its unique characteristics, but the development of a dc microgrid is also facing some challenges, such as interruption and isolation of short-circuit fault currents. Therefore, the dc circuit breaker plays an important role in ensuring the normal work of a dc microgrid. In this paper, a novel bidirectional dc solid-state circuit breaker is proposed to realize the bidirectional flow of energy, which ensures the higher operating efficiency of the dc microgrid. Compared with other solid-state circuit breakers, the proposed novel topology has simpler structure, common ground, and fewer components. First, this paper makes a detailed analysis of the different working stages of the circuit when the fault occurs in combination with simulation results of the circuit topology. Then, the standard of selecting the components through the calculation and analysis of the circuit is given in this paper. Finally, the performance of the novel bidirectional solid-state circuit breaker is verified by experiments. [ABSTRACT FROM AUTHOR]

Mobile, wearable, and Internet-of-Things (IOT) electronic systems are typically powered by a single-cell lithium-ion (Li-ion) battery. Increasing demand for battery life and the constraint of the overall platform size impose an emerging desire for an efficient and compact power conversion stage that can directly deliver power from the battery, which ranges from 3.2 to 4.2 V, to the supplies of application/communication processors in the range of 1 V. The switched capacitor (SC) converter, though promising in some ways for this application, is inefficient at voltage regulation and is limited in capacitor utilization. This paper presents a hybrid dc–dc converter topology that eliminates charge sharing losses with a small inductor. The necessary inductance can be realized by PCB traces, which shows the potential for a compact system-in-package (SiP) solution. The designed converter is implemented in Texas Instruments’ 0.15- $\mu \text{m}$ CMOS process with a nominal 3:1 conversion ratio. It supports a 3.2–4.2-V input voltage with a continuous output regulation of 0.8–1.5 V. The peak efficiency is 87.2% with 83.4% efficiency at a power density of 0.46 W/mm2. This paper also presents an effective methodology of developing the large-signal model and small-signal dynamics for the generalized N:1 converter topology. A tight load line-based controller is integrated into the designed chip and experimentally verified with a transient performance of 50-mV voltage overshoot/undershoot under 400-mA on-die load step. [ABSTRACT FROM AUTHOR]

Nonlinear transmission lines (NLTLs) are passive networks with the capability of modulating baseband pulses. These networks are used for generating RF pulses at high-power levels. NLTLs have a unique performance in high-power RF pulse generation among all the generators based on the solid-state technology. A high-power rectangular pulse is injected to the line, gradually evolved into an oscillatory pulse while propagating through the network, and finally, in the form of a high-power RF pulse, is delivered to the load. Properly terminating an NLTL, in order to transfer the maximum available RF power to the load, is an important problem. In this paper, an accurate analysis is presented, which gives a closed-form formula for the output RF power in lossy NLTLs. Using this analysis, optimal resistive terminating load for RF applications of NLTLs is extracted. The output central frequency is also investigated in this paper. All the obtained theoretical results are verified by SPICE simulations and measurements in two implemented NLTLs. [ABSTRACT FROM AUTHOR]

This article investigates energy storage requirements in the submodules of a class of converters known as hybrid cascaded modular multilvel converters (HC-MMCs). The complexities arising from the usage of different submodule types and their non-conventional arrangement necessitate detailed analysis of submodule capacitor voltage ripples, which are needed for development of guidelines for sizing submodule capacitors. This paper characterizes electric charge variations in the submodule capacitors to derive expressions for capacitor voltage ripples, and to determine the energy storage requirements of the converter. The paper uses detailed electromagnetic transient (EMT) simulations and experimental results on a laboratory-scale MMC setup to verify and validate its findings. [ABSTRACT FROM AUTHOR]

This paper presents a generalized restructured topology for boost, buck-boost and its derived dc/dc converters with rearranging branches to enhance the reliability of the converter. This paper instigates the derivation of state-of-the-art topologies with reduced capacitor voltage stress. Mainly in the restructured topology, the capacitor branch is rearranged in the converter and this redesign venture results in profuse advantages like a better choice of the capacitor with low voltage rating, low equivalent series resistance and reduced voltage stress of the converter. The investigation of the capacitor voltage stress and reliability test is carried out. No extra components are required in this method, the same component count as the conventional converter is maintained. In comparison with the conventional converters, the restructured topology shows the identical output voltage with decreased capacitor voltage stress. Besides reduced voltage stress, the capacitor losses are also less and this allows the capacitor to perform better. As a consequence, the efficiency and lifetime are improved and extended. A detailed illustration of the significance of this restructured concept is presented with a validating analysis. Experimental results from a 600 W prototype are presented with different duty cycles for validating and highlighting the special features of the restructured topology. [ABSTRACT FROM AUTHOR]

The risk of unstable subsynchronous oscillations (SSO) in DFIG-based wind parks radially connected to transmission lines with series capacitive compensation is typically assessed with numerous electromagnetic transient (EMT) simulations, which is a time-consuming process. However, not all operating scenarios present risk of SSO and require such a detailed investigation. This paper proposes two charts based on impedance equivalents of wind generators obtained through frequency scans to quickly map which combinations of parameters can create unstable SSOs and which combinations are risk-free. With the information, engineers can immediately filter out scenarios with no risk of instability and conduct detailed studies on fewer scenarios that are truly critical. These charts can be obtained with simple equations that use only information readily available in practice to engineers, without the need to run any computer simulation. The charts also reveal the key operating conditions that can increase the risk of an unstable SSO and provide real-time quantitative insights into how close a wind park is to an instability. Application examples are provided to illustrate how this approach can help engineers speed up studies to identify the risk of SSO. [ABSTRACT FROM AUTHOR]

Multilevel converters (MLCs) are pioneers in the field of electrical energy conversion. From the classification of MLCs, modular multilevel converter (MMC) is top-rated due to its attractive structure and performance. The modular nature and no need for isolated DC resources are two significant advantages of this converter. However, the need for many sensors to control its performance is a considerable drawback. In addition, the internal circulating current in the MMC causes losses, decreases efficiency, and increases the voltage ripple of capacitors. This paper proposes combining a new capacitor voltage sorting method and an open-loop controller based on arms energy estimation to control the MMC using two voltage sensors in the arms and one current sensor at the output. The proposed method ensures continuous voltage balancing of the capacitors and removes multiple voltage sensors from sub-modules (SMs). The simulation and experimental results verify the accuracy and effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]